JPH08214036A - Orthogonal detection circuit - Google Patents

Abstract

PURPOSE: To apply digital orthogonal detection to a phase modulation signal with a simple configuration and low power consumption. CONSTITUTION: A frequency of a sampling clock CK used to apply digital conversion to a phase modulation signal S20 is set to be a multiple of four of a carrier wave frequency of the phase modulation signal. Thus, 1st and 2nd orthogonal clock signals CI, CQ orthogonal to each other are expressed in a simple numeral string and then the configuration of an orthogonal clock generating means 36 generating the 1st and 2nd orthogonal clock signals is simplified and the entire configuration is simplified and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Fields of Industrial Application Conventional Technology (FIGS. 5 to 7) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 4) Action Example (1) Operating Principle of Quadrature Detection Circuit (2 ) First Example (FIGS. 1 and 2) (3) Second Example (FIG. 3) (4) Third Example (FIG. 4) (5) Other Examples Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature detection circuit, which is suitable for application to a quadrature detection circuit for quadrature detection of a signal phase-modulated in a CDMA (Code Division Multiple Access) type digital cellular telephone device. is there.

[0003]

2. Description of the Related Art Conventionally, in a CDMA digital cellular telephone device, transmission data is phase-modulated and transmitted by using a modulation circuit as shown in FIGS. 5 and 6, for example. For example, as shown in FIG. 5, BPSK (Bina
In the case of the modulation circuit 1 of the ry Phase Shift Keying) modulation method, the transmission data generated by the data generator 2 is first output to the multiplier 3, where the transmission data and the PN code (Pseu) are output.
do Noise code) The PN code (data value "1" or "-1") generated by the generator 4 is multiplied to spread the spectrum of the transmission data. Then, the modulation circuit 1 outputs the spread spectrum transmission data S1 to the multiplier 5, where the transmission data S1 is multiplied by the carrier wave S _C (= cos (ω ₁ t)) generated by the oscillator 6. . As a result, the modulation circuit 1 changes the phase of the carrier wave S _C by 0 or π in accordance with the transmission data S1, so-called B.
A PSK-modulated modulation signal S2 is obtained.

Incidentally, the data value of the PN code output from the PN code generator 4 is not "1" or "-1", but
In the case of “1” or “0”, the exclusive OR circuit is used instead of the multiplier 3.

Further, as shown in FIG. 6, QPSK (Quadra
In the case of the modulation circuit 10 of the ture phase shift keying) modulation method, the transmission data generated by the data generator 2 is distributed and output to the multipliers 11 and 12. The multiplier 11 is PN
The first PN code generated by the code generator 13 is multiplied by the transmission data, and the resultant spread spectrum transmission data S10 is output to the multiplier 14. The multiplier 14 multiplies the carrier wave S _C (= cos (ω ₁ t)) generated by the oscillator 15 by the transmission data S10, and the resulting modulated signal S11.
Is output to the adder 16.

On the other hand, the multiplier 12 multiplies the second PN code generated by the PN code generator 17 by the transmission data, and outputs the spectrum spread transmission data S12 obtained as a result to the multiplier 18. The multiplier 18 is a delay circuit 19 and has a π /
The carrier wave S _C ′ (= sin (ω ₁ t)) delayed by two phases is multiplied by the transmission data S12, and the resultant modulated signal S13 is output to the adder 16.

Thus, in the modulation circuit 10, the phase of the carrier wave S _C is 0, π / 2, π or 3π by adding the modulated signal S11 and the modulated signal S13 by the adder 16.
/ 2, so-called QPSK-modulated modulation signal S
You get 14. Incidentally, the modulation circuit 10 as shown in FIG. 6 is generally called a balanced type modulation circuit.

The modulated signal phase-modulated by the above-mentioned modulation circuit is demodulated on the receiving side by using, for example, a quadrature detection circuit 20 as shown in FIG. In the quadrature detection circuit 20, first, the phase-modulated modulation signal S20 is input to the multipliers 21 and 22. The multiplier 21 multiplies the modulation signal S20 by the oscillation signal S21 (= cos (ω ₂ t)) having the same frequency as the carrier wave S _C generated by the oscillator 23, and the detection signal S22 obtained as a result is fed to the low-pass filter ( LPF) 24. The low-pass filter 24 removes unnecessary harmonic components from the detection signal S22 and outputs only the baseband signal S23 as an analog digital converter (A /
D) Output to 25. The analog digital converter 25 digitally converts the baseband signal S23 at a predetermined sampling frequency to obtain in-phase component detection data D _i .

On the other hand, the multiplier 22 has a delay circuit 26 of π / 2.
The phase-delayed oscillation signal S24 (= sin (ω ₂ t)) is multiplied by the modulation signal S20, and the resultant detection signal S25 is output to the low pass filter (LPF) 27. The low-pass filter 27 removes unnecessary harmonic components from the detection signal S25 and outputs only the baseband signal S26 to the analog digital converter (A / D) 28. The analog digital converter 28 digitally converts the baseband signal S26 at a predetermined sampling frequency to obtain quadrature component detection data D _q . Incidentally, the detection data D _i and D _q in the spread spectrum state are demodulated to the original data by a despreading circuit (not shown) provided in the subsequent stage of the quadrature detection circuit 20.

[0010]

In the quadrature detection circuit 20 described above, the analog oscillator 23 and the multiplier 21,
Since the quadrature detection is performed using 22, the two oscillation signals S
There is a problem that the detection accuracy changes depending on the quadrature accuracy of S21 and S24. For example, if the quadrature accuracy of the oscillation signals S21 and S24 deteriorates, the detection accuracy may deteriorate accordingly.

As a method for solving this, there is a method in which a quadrature detection circuit is digitalized and a modulated signal is detected by digital processing. However, if the quadrature detection circuit is digitalized, the orthogonality of the two oscillation signals can be guaranteed, but on the other hand, the circuit scale and power consumption may increase.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a quadrature detection circuit which has a simple structure and low power consumption and is capable of digitally quadrature detecting a phase modulation signal.

[0013]

In order to solve such a problem, in the present invention, the input phase modulation signal is subjected to analog digital conversion, and the phase modulation data obtained as a result thereof are orthogonal to each other. In a quadrature detection circuit that digitally performs quadrature detection using a clock, analog digital conversion means for converting a phase-modulated signal into digital data with a sampling clock that is four times the carrier frequency, and a numerical sequence that is orthogonal to each other A quadrature clock generating means for generating a first quadrature clock and a second quadrature clock having the same clock rate as the sampling clock of the digital converting means is provided, and the quadrature clock generating means is used for the phase-modulated data analog-digitally converted by the analog digital converting means. The first and second orthogonal clocks generated in And to obtain the first and second detection data by multiplying.

Further, according to the present invention, the quadrature for digitally quadrature-detecting the input phase-modulated signal by analog-digital conversion and using the first and second quadrature clocks which are orthogonal to each other, the resulting phase-modulated data are orthogonally detected. In the detection circuit, analog digital conversion means for converting the phase modulation signal into digital data with a sampling clock of four times the carrier frequency, phase modulation data analog-digital converted by the analog digital conversion means, and the phase modulation data are encoded. First data selection means for obtaining the first detection data by selecting the selection data based on the count value of the counter means, the inverted phase modulation data having been inverted and the data value "0" are input as the selection data; Phase modulation data, inverted phase modulation data and data value "0" are selected data. Is input and a second data selecting means for obtaining a second detection data by selecting the selection data based on the count value of the counter means is provided as,
The phase-modulated signal is digitally quadrature-detected.

Further, in the present invention, the input phase modulation signal is subjected to analog digital conversion, and the phase modulation data obtained as a result is subjected to digital quadrature detection using first and second quadrature clocks which are orthogonal to each other. In the detection circuit, analog digital conversion means for converting the phase modulation signal into digital data with a sampling clock of 4 times the carrier frequency, and phase modulation data analog-digital converted by the analog digital conversion means and the phase modulation data are encoded. Inverted data of the inverted phase modulation is inputted as selection data, and the first data selection means for obtaining the first detection data by selecting the selection data based on the count value of the counter means for counting the sampling clock, Selectable phase modulation data and inverted phase modulation data And a second data selection means for obtaining the second detection data by selecting the selection data based on the count value of the counter means so that the phase modulation signal is digitally quadrature-detected. did.

[0016]

The sampling clock for digitally converting the phase-modulated signal is set to four times the carrier frequency of the phase-modulated signal, so that the first and second orthogonal clocks that are orthogonal to each other are represented by a simple numerical sequence. This makes it possible to easily multiply the phase modulation data by the first and second quadrature clocks and simplify the structure of the quadrature clock generation means for generating the first and second quadrature clocks. Can be Therefore, the configuration can be simplified as a whole and the power consumption can be reduced.

By setting the sampling clock for digitally converting the phase-modulated signal to four times the carrier frequency of the phase-modulated signal, the first and second orthogonal clocks that are orthogonal to each other can be represented by a simple numerical sequence. Since it can be expressed, the multiplication means of the phase modulation data and the first and second quadrature clocks can be configured by the simple data selection means, and the multiplication means can be reduced.
Therefore, the configuration can be simplified as a whole and the power consumption can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Operation Principle of Quadrature Detection Circuit First, the operation principle of the quadrature detection circuit according to the present invention will be described.
In the case of this embodiment, the quadrature detection circuit performs an analog digital conversion on the phase-modulated modulation signal, and multiplies the resulting digital data by a quadrature clock to perform digital quadrature detection. At that time, the quadrature detection circuit sets the sampling frequency at the time of analog digital conversion to four times the carrier wave of the modulation signal, thereby setting the quadrature clock to “0”, “1”, “−1” or “1”, By expressing only "-1", the multiplier used for multiplication can be simplified or reduced to simplify the configuration and realize low power consumption.

Here, the operating principle will be specifically described.
First, the modulation signal r (t) phase-modulated by the modulation circuit 10 as shown in FIG. 6 is transmitted data d (t), PN
The first PN code generated by the code generator 13 is pni
(T), pnq (t) is the second PN code generated by the PN code generator 17, and co is the carrier wave S _C generated by the oscillator 15.
s (ωt), carrier wave S delayed by π / 2 in the delay circuit 19
If the _C 'and sin (ωt), the following equation

[Equation 1] It is represented by.

When the sampling frequency of the quadrature detection circuit is set to 4 times the carrier wave S _C (or S _C ′), the modulation data r (i) after the analog digital conversion of the modulation signal r (t) is expressed by the following equation.

[Equation 2] It is represented by. Modulation data r represented by the equation (2)
For (i),

(Equation 3) If the first orthogonal clock CI shown in is multiplied and the result is converted to the sum form,

[Equation 4] As shown in, the detection data ri (i) of the in-phase component is obtained.

For the modulation data r (i) represented by the above equation (2), the following equation

(Equation 5) When the first orthogonal clock CI shown in is multiplied by the second orthogonal clock CQ which is orthogonal, and the result is converted into the sum form,
The following formula

(Equation 6) The quadrature component detection data rq (i) is obtained as shown in FIG. Detection data ri (i), r obtained in this way
q (i) is passed through a low-pass filter to remove unnecessary harmonic components,

(Equation 7)

(Equation 8) As shown in, the baseband detection data ri (i), r
q (i) is required.

By substituting i = 0, 1, 2, 3, ... For the first and second orthogonal clocks CI, CQ, respectively, the first orthogonal clock CI is "1, 0, -1,
0, ..., ”And the second orthogonal clock CQ is a numerical sequence of“ 0, 1, 0, -1 ,. Therefore i
= 0, 1, 2, 3, ...
And the second orthogonal clocks CI and CQ can be represented by "0", "1", and "-1", which facilitates multiplication.

The above-mentioned first and second orthogonal clocks C
I = 0.5, 1.5, 2.5, 3.5 for I and CQ respectively ...
, The first orthogonal clock CI is “1 / √2,
The numerical value sequence is “−1 / √2, −1 / √2, 1 / √2, ...”, and the second orthogonal clock CQ is “1 / √2, 1 / √2.
, −1 / √2, −1 / √2,… ”.
If this result is multiplied by √2, the first orthogonal clock C
I is a numerical sequence of "1, -1, -1, 1, ...", and the second orthogonal clock CQ is "1, 1, -1, -1, ...".
Becomes the numerical sequence of. Therefore, i = 0.5, 1.5, 2.5, 3.5,
.., the first and second quadrature clocks CI and CQ can be represented by "1" and "-1", whereby multiplication can be easily performed.

As described above, in the quadrature detection circuit according to the present invention, the sampling frequency for analog digital conversion is set to 4 times the carrier wave S _C , whereby the first and second quadrature clocks CI and CQ are set to "0". , "1",
The multiplication is simplified by expressing with only "-1" or "1" and "-1".

(2) First Embodiment In FIG. 1, reference numeral 30 generally indicates a quadrature detection circuit according to the present invention, in which a phase-modulated modulation signal S20 is input to a bandpass filter (BPF) 31. The bandpass filter 31 removes unnecessary signal components such as noise from the modulation signal S20 and extracts only the target signal component, and the resulting modulation signal S30 is converted into an analog digital converter (A /
D) Output to 32.

The analog digital converter 32 is the oscillator 3
The modulated signal S30 is analog-digital converted by operating based on the clock CK generated in 3 (that is, the clock CK is used as a sampling clock), and the resulting modulated data D _AD is output to the multipliers 34 and 35. In this case, the oscillator 33 uses the carrier frequency of the modulated signal S20 of 4
A clock CK having a doubled frequency is generated. As a result, the analog digital converter 32 carries out analog digital conversion of the modulation signal S20 at a frequency four times as high as the carrier frequency.

The clock CK generated by the oscillator 33
Is also input to the quadrature signal generator 36. The quadrature-phase signal generator 36 generates first and second quadrature clocks CI and CQ which are numerical sequences that are orthogonal to each other based on the clock CK and have the same clock rate as the clock CK. In this case, the first and second orthogonal clocks CI, CQ
The period of the numerical value sequence is 4 times the sampling period of the analog digital converter 32.

That is, the quadrature-phase signal generator 36 is based on the above-mentioned principle, and the first quadrature clock CI is "1,
A clock composed of "0, -1, 0, ..." is generated as a second orthogonal clock CQ, and a clock composed of "0, 1, 0, -1, ..." is generated. Then, the quadrature signal generator 36 outputs the first quadrature clock CI to the multiplier 34,
The quadrature clock CQ of is output to the multiplier 35.

The multiplier 34 multiplies the modulation data D _AD by the first quadrature clock CI, and the resulting detection data D
_{The DETi} is output to the low pass filter (LPF) 37. The low pass filter 37 removes unnecessary harmonic components from the detection data D _DETi . As a result, the in-phase component detection data D _{i in} the baseband can be obtained. Further, the multiplier 35 multiplies the modulation data D _AD by the second quadrature clock CQ, and the detection data D _DETq obtained as a result is _fed to a low pass filter (LP).
F) Output to 38. The low pass filter 38 removes unnecessary harmonic components from the detected data D _DETq . As a result, the quadrature component detection data D _{q in} the baseband is obtained.

The quadrature phase signal generator 36 has the structure shown in FIG. 2 and inputs the clock CK to the 2-bit counter 40. The counter 40 counts the input clock CK and outputs the count value (2 bits) to the selectors 41 and 42 as the selection control signal S40. In this case, the counter 40 is 2
Since it consists of bits, its count value is "00, 0
This is repeated in sequence with 1, 10, 11 ”as one cycle.
That is, the counter 40 is the analog digital converter 32.
The clock CK used as the sampling frequency is divided by four to generate the selection control signal S40 having a cycle four times as long as the sampling cycle of the analog digital conversion.

The selector 41 has selection data CI0 to CI3.
, Respectively, and the selector 41 selects the selection data CI0 to CI3 according to the selection control signal S40 and outputs it as the first orthogonal clock CI. At this time, the selector 41 outputs the selection data CI0 when the selection control signal S40 is "00", the selection data CI1 when the selection control signal S40 is "01", and the selection data CI2 when the selection control signal S40 is "10". , The selection control signal S40 is "1.
When it is "1", the selection data CI3 is selected. Accordingly, the selection data CI0 is set to the data value "1", the selection data CI
1 is the data value "0", and the selection data CI2 is the data value "-".
1 "and the selection data CI3 are set to the data value" 0 ", respectively, so that the selector 41 selects" 1, 0,-".
A first orthogonal clock CI consisting of 1, 0, ...

The selector 42 has selection data CQ0 to CQ0.
Q3 is respectively inputted, and the selector 42 selects the selection data CQ0 to CQ3 according to the selection control signal S40 and outputs it as the second quadrature clock CQ. At this time, the selector 42 outputs the selection data CQ0 when the selection control signal S40 is "00", the selection data CQ1 when the selection control signal S40 is "01", and the selection data S40 is "10".
When the selection control signal S40 is "1"
When it is "1", the selection data CQ3 is selected. Therefore, the selection data CQ0 is changed to the data value "0", the selection data CQ
1 is set to the data value "1", the selection data CQ2 is set to the data value "0", and the selection data CQ3 is set to the data value "-1".
A second quadrature clock CQ consisting of 0, -1, ...

In the above configuration, the quadrature detection circuit 30 first converts the modulation signal S20 into the analog digital converter 3
2, analog digital conversion is performed and modulation data D _{AD is obtained.}
Get. In this case, the clock CK generated by the oscillator 33
By setting the frequency of 4 times the carrier frequency of the modulation signal S20, the modulation signal S20 is subjected to analog digital conversion at a sampling frequency of 4 times. Then, in the quadrature detection circuit 30, the first and second quadrature clocks C orthogonal to each other with respect to the modulation data D _AD thus obtained.
Detection data D obtained by multiplying I and CQ respectively
_DETi and D _DETq are passed through low-pass filters 37 and 38, respectively, to _obtain in-phase component detection data D _i and quadrature component detection data D _q .

In this case, the sampling frequency of the analog digital conversion is set to 4 times the carrier frequency of the modulation signal S20, so that the first quadrature clock CI and the second quadrature clock CQ are set to "0", "1" and It can be expressed by "-1". Because the sampling frequency is set to four times the carrier frequency of the modulated signal S20, the first quadrature clock CI and s represented by the cos wave
The phase angle of the second quadrature clock CQ represented by the in-wave can be set to “0, π / 2, π, 3π / 2, ...”, whereby the first and second quadrature clocks CI, CQ
Can be represented by "0", "1" and "-1".

In this way, in the quadrature detection circuit 30, the first and second quadrature clocks CI and CQ are set to "0" and "1".
And "-1" makes it easy to multiply the modulation data D _AD by the first quadrature clock CI and the modulation data D _AD by the second quadrature clock CQ. In addition, the quadrature detection circuit 30 uses the three data as the first data.
And the second quadrature clocks CI and CQ can be represented, so that the quadrature phase signal generator 36 for generating the first and second quadrature clocks CI and CQ is composed of only the selectors 41 and 42 and the counter 40. As a result, the entire configuration can be simplified and power consumption can be reduced as compared with the related art.

Thus, according to the above configuration, the sampling frequency for analog digital conversion is set to 4 times the modulation signal S20, whereby the first and second quadrature clocks CI and CQ are set to "0". ",""1" and "-1" represent the digital quadrature detection of the modulated signal S20 with a simple configuration and low power consumption.

(3) Second Embodiment FIG. 3 showing parts corresponding to those in FIG. 1 and FIG.
In 50, reference numeral 50 indicates a quadrature detection circuit as a whole, which is configured in substantially the same manner as the first embodiment except that a selector is used instead of the multiplier. In the case of this embodiment, the selector 51
Sign inversion modulation data D _AD 'in the analog-to-digital converter 32 modulated data D _AD converted analog-to-digital, the modulated data D _AD by the sign inverter 52 as the selection data is (= -D _AD) and a data value "0 Has been entered. The selection control signal S40 generated by the counter 40 is input to the selector 51. The selector 51 selects the modulation data D _AD , D _AD 'or the data value "0" according to the selection control signal S40 and outputs it as the detection data D _DETi .

In this case, the selector 51 outputs the selection control signal S4.
When 0 is “00”, the modulation data D _AD is selected and the selection control signal S
When 40 is "01", the data value is "0", and when the selection control signal S40 is "10", the modulation data D _AD '(= -D _AD )
When the selection control signal S40 is "11", the data value "0" is selected. As a result, the selector 51 causes the detection data D consisting of "D _AD , 0, -D _AD , 0, ...".
Output _DETi . That is, the selector 51 outputs the modulation data D _AD
Will be output by multiplying the first orthogonal clock CI by "1, 0, -1, 0, ...".

[0040] Similarly, modulation data D _AD to selector 53 and the analog-to-digital conversion in analog-to-digital converter 32 as selected data, modulation data D _AD with the modulated data D _AD negated by sign inverter 52 '( =-
D _AD ) and the data value “0” are input, and the selection control signal S40 generated by the counter 40 is also input. The selector 53 selects the modulation data D _AD , D _AD 'or the data value "0" according to the selection control signal S40 and outputs it as the detection data D _DETq .

In this case, the selector 53 outputs the selection control signal S4.
When 0 is “00”, the data value “0” is set, and the selection control signal S
When 40 is "01", the modulation data D _AD , when the selection control signal S40 is "10", the data value "0", and when the selection control signal S40 is "11", the modulation data D _AD '(=-
D _AD ) respectively. As a result, the selector 53 causes the detection data D consisting of "0, D _AD , 0, -D _AD , ..."
Output _DETq . That is, the selector 53 controls the modulation data D _AD.
Will be output by multiplying by the second orthogonal clock CQ consisting of "0, 1, 0, -1, ...".

The detection data D _DETi and D _DETq thus obtained are low pass filters 37 and 38, respectively.
, And unnecessary harmonic components are removed here. As a result, the quadrature detection circuit 50 obtains baseband in-phase component detection data D _i and quadrature component detection data D _q .

In the above configuration, in the quadrature detection circuit 50, the modulation signal S20 is subjected to analog digital conversion at a sampling frequency that is four times the carrier frequency of the modulation signal S20, and the resulting modulation data D _AD is selected as selection data. Input to the devices 51 and 53. In the quadrature detection circuit 50, the modulation data D _AD is input to the sign inverter 52 to invert the sign, and the resulting modulation data D _AD '(= -D _AD ) is input to the selectors 51 and 53 as selection data. To do. Further, in the quadrature detection circuit 50, the data value “0” is set as the selection data.
Is input to the selectors 51 and 53. And the quadrature detection circuit 5
At 0, the modulation data D _AD ,
For the selectors 51 and 53 to which D _AD '(= -D _AD ) and the data value "0" are input, "00, 01, 10, 11,
.. is input to control the selection operation of the selectors 51 and 53.

That is, in the selector 51, the modulation data D _AD is selected when the selection control signal S40 is "00", the data value "0" is selected when the selection control signal S40 is "01", and the selection data S40 is set to "10". , The modulation data D _AD '(=
-D _AD ) causes the data value "0" to be selected when the selection control signal S40 is "11". Thereby, the same "D _AD , 0,-" as the result of multiplying the modulation data D _AD by the first quadrature clock CI consisting of "1, 0, -1, 0, ...".
It is possible to obtain detection data D _DETi consisting of D _AD , 0 ,.

In the selector 53, when the selection control signal S40 is "00", the data value "0", when the selection control signal S40 is "01", the modulation data D _AD, and when the selection control signal S40 is "10", Data value "0" when the selection control signal S40 is "11" and the modulation data D _AD '(=-
D _AD ) respectively. As a result, the modulation data D
_AD and "0,1,0, -1, ..." result obtained by multiplying the second orthogonal clock CQ made in the same "0, D _AD, 0, -
It is possible to obtain the detection data D _DETq consisting of D _AD ,.

In this way, the quadrature detection circuit 50 sets the sampling frequency for analog digital conversion to four times the carrier frequency of the modulated signal S20 to set the first and second quadrature clocks CI, CQ to "0". , "1"
, And the modulated signal S20 is quadrature detected by utilizing the fact that it can be expressed by "-1". As a result, in the quadrature detection circuit 50, the modulation data D _AD , D _AD '(= -D
_AD ) and selectors 51 and 53 to which the data value "0" is input
Desired detection data D _DETi , just by controlling the selection operation of
D _DETq can be obtained, and the number of multipliers can be reduced. Therefore, in the quadrature detection circuit 50, the overall configuration can be made much simpler than in the first embodiment, and the power consumption can be reduced.

Thus, according to the above configuration, the modulation data D _AD , D _AD '(=-
D _AD ) or selectors 51 and 53 for selecting the data value "0"
By providing the modulation data D _AD and “1, 0, −
It is possible to obtain the detection data D _DETi similar to the result of multiplication with the first quadrature clock CI consisting of 1, 0, ..., And the modulation data D _AD and “0, 1, 0, −1 ,. … ”
The detection data D _DETq similar to the result of multiplication with the second quadrature clock CQ can be obtained, and the number of multipliers can be reduced. Thus, the quadrature detection circuit 50 capable of performing the digital quadrature detection of the modulation signal S20 with a simple structure and low power consumption can be realized.

(4) Third Embodiment In FIG. 4 in which parts corresponding to those in FIG. 3 are designated by the same reference numerals, reference numeral 60 denotes a quadrature detection circuit as a whole, and a selector 61.
And 62 as modulation data D _AD , D _AD '
Only (= -D _AD ) is input, and the first quadrature clock CI is "1, -1, -1, 1, ... As described in" (1) Operating principle of quadrature detection circuit ". ", And the second orthogonal clock CQ is" 1, 1, -1, -1, ... ".
This is an example of a case corresponding to. That is, in this embodiment, the first quadrature clock CI and sin represented by the cos wave are used.
The phase angle of the second quadrature clock CQ represented by the wave is defined as "π /
4, 3π / 4, 5π / 4, 7π / 4, ... ”.

The selector 61 receives the modulation data D _AD or D _AD 'in accordance with the selection control signal S40 output from the counter 40.
_Is selected and output as detection data D _DETi . In this case, the modulated data D _AD when the selector 61 is the selection control signal S40 of "00", the modulated data D _AD 'when the selection control signal S40 of "01", the selection control signal S40 of "10"
, The modulation control data D _AD 'and the selection control signal S40 are "1.
When it is “1”, the modulation data D _AD is selected. This causes the selector 61 to display “D _AD , −D _AD , −D _AD , D _AD , ...
The detection data D _DETi of "..." is output. That selector 61 "1 modulated data D _AD, -1, -1,1, ...
.., which is multiplied by the first orthogonal clock CI.

Similarly, the selector 62 selects the modulation data D _AD or D _AD 'in accordance with the selection control signal S40 output from the counter 40 and outputs it as the detection data D _DETq .
In this case, the selector 62 indicates that the selection control signal S40 is "00".
When, the modulation data D _AD is selected and the selection control signal S40 is “0.
1 ", the modulation data D _AD , the selection control signal S40 is" 10 ", the modulation data D _AD ', and the selection control signal S4.
When 0 is "11", the modulation data D _AD 'is selected. This causes the selector 62 to display “D _AD , D _AD , −D _AD , −
The detection data D _DETq consisting of D _AD , ..., _Is output. That is, the selector 62 adds "1, 1, -1,-" to the modulation data D _AD.
That is, the data obtained by multiplying the second quadrature clock CQ consisting of 1, ...

In the above configuration, in the quadrature detection circuit 60, the modulation signal S20 is subjected to analog digital conversion at a sampling frequency which is four times the carrier frequency of the modulation signal S20, and the resulting modulation data D _AD is selected as selection data. Input to the containers 61 and 62. In the quadrature detection circuit 60, the modulation data D _AD is input to the sign inverter 52 to invert the sign, and the resulting modulation data D _AD '(= -D _AD ) is input to the selectors 61 and 62 as selection data. To do. Then, in the quadrature detection circuit 60, the selection control consisting of "00, 01, 10, 11, ..." For the selectors 61, 62 to which the modulation data D _AD , D _AD 'is input as the selection data in this way. The signal S40 is input to control the selection operation of the selectors 61 and 62.

That is, in the selector 61, when the selection control signal S40 is "00" and "11", the modulation data D
The _AD, respectively to select the modulated data D _AD 'when the selection control signal S40 of "01" and "10". This results in the same "D" as the result of multiplying the modulated data D _AD by the first orthogonal clock CI consisting of "1, -1, -1, 1, ...".
Detection data D consisting of _AD , -D _AD , -D _AD , D _AD , ... "
_You can get _DETi .

In the selector 62, when the selection control signal S40 is "00" and "01", the modulation data D
The _AD, "10" is the selection control signal S40, respectively is selected modulation data D _AD 'when "11". Thus, the same "D _AD , D _AD , -D _AD , -D as the result of multiplying the modulation data D _AD by the second quadrature clock CQ consisting of" 1, 1, -1, -1, ... ". It is possible to obtain the detection data D _DETq consisting of _AD ,.

In this way, in the quadrature detection circuit 60, the sampling frequency of the analog digital conversion is set to four times the carrier frequency of the modulated signal S20 to set the first and second quadrature clocks CI and CQ to "1". And-
The modulated signal S20 is quadrature detected by utilizing the fact that it can be expressed by "1". As a result, in the quadrature detection circuit 60, desired detection data D _DETi , D _{DETq can be obtained} only by controlling the selection operation of the selectors 61, 62 to which the modulation data D _AD , D _AD '(= D _AD ) are input as selection data. Can be obtained, and the number of multipliers can be reduced. Therefore, in the quadrature detection circuit 60, since the selection data is smaller than that in the second embodiment, the entire configuration can be simplified and the power consumption can be reduced.

Thus, according to the above configuration, the modulation data D _AD or D _AD '(=
Since the selectors 61 and 62 for selecting D _AD ) are provided, the result obtained by multiplying the modulation data D _AD by the first quadrature clock CI consisting of “1, −1, −1, 1, ... Similar detection data D _DETi can be obtained, and detection data D _similar to that obtained by _multiplying the modulation data D _{AD by} the second quadrature clock CQ consisting of "1, 1, -1, -1, ...". _DETq
Can be obtained, and the number of multipliers can be reduced. Thus, it is possible to realize the quadrature detection circuit 60 capable of performing the digital quadrature detection of the modulation signal S20 with a simple configuration and low power consumption.

(5) Other Embodiments In the above-described first embodiment, a clock consisting of "1, 0, -1, 0, ..." Is generated as the first orthogonal clock CI, and the second orthogonal clock CI is generated. Orthogonal clock CQ is "0, 1,
The case where the clock consisting of 0, -1, ... "Is generated. However, the present invention is not limited to this, and the first quadrature clock CI as described in" (1) Operation principle of quadrature detection circuit ". To generate a clock consisting of "1, -1, -1, 1, ..."
Even when a clock composed of "-1, -1, ..." Is generated, the same effect as the above case can be obtained. Incidentally, in this case, the data values of "1" and "-1" may be input to the selector of the quadrature phase signal generator,
This can further simplify the configuration.

In the above embodiment, the case where the unnecessary signal component of the modulated signal S20 is removed by the bandpass filter 31 has been described, but the present invention is not limited to this.
The unnecessary signal component may be removed by using a low-pass filter.

Further, in the above-mentioned embodiment, the case where the clock CK supplied to the analog digital converter 32 is the sampling frequency itself of the analog digital converter 32 has been described, but the present invention is not limited to this.
For example, if the analog digital converter requires an operating clock with a frequency higher than the sampling frequency, the frequency of the clock CK may be increased accordingly. However, in that case, it is necessary to further divide the frequency by the counter 40 by an amount corresponding to the increased frequency of the clock CK.

Further, in the above-mentioned embodiments, the case where the present invention is applied to the quadrature detection circuit used in the digital cellular telephone device has been described, but the present invention is not limited to this, and the phase-modulated modulated signal is digitally applied. The present invention can be widely applied to a quadrature detection circuit that detects a signal.

[0060]

As described above, according to the present invention, the sampling clock for digitally converting the phase-modulated signal is set to four times the carrier frequency of the phase-modulated signal. The second orthogonal clock can be represented by a simple numerical sequence, which can simplify the configuration of the orthogonal clock generating means for generating the first and second orthogonal clocks, thus simplifying the overall configuration. It is possible to reduce the power consumption.

By setting the sampling clock for digitally converting the phase-modulated signal to four times the carrier frequency of the phase-modulated signal, the first and second orthogonal clocks orthogonal to each other can be represented by a simple numerical sequence. Since it can be expressed, the multiplication means of the phase modulation data and the first and second quadrature clocks can be configured by a simple data selection means, which can reduce the multiplication means and thus The configuration can be simplified as a whole and the power consumption can be reduced. As a result, it is possible to realize a quadrature detection circuit capable of performing digital quadrature detection of a phase modulation signal with a simple configuration and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a quadrature detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a quadrature phase signal generator of the quadrature detection circuit.

FIG. 3 is a block diagram showing a configuration of a quadrature detection circuit according to a second embodiment.

FIG. 4 is a block diagram showing a configuration of a quadrature detection circuit according to a third embodiment.

FIG. 5 is a block diagram showing a modulation circuit of a BPSK modulation method.

FIG. 6 is a block diagram showing a modulation circuit of a QPSK modulation method.

FIG. 7 is a block diagram showing a conventional quadrature detection circuit.

[Explanation of symbols]

20, 30, 50, 60 ... Quadrature detection circuit, 21, 2
2, 34, 35 ... Multiplier, 23, 33 ... Oscillator, 2
5, 28, 32 ... Analog digital converter, 24,
27, 37, 38 ... Low-pass filter, 31 ... Band-pass filter, 36 ... Quadrature phase signal generator, 40 ...
... Counter, 41, 42, 51, 53, 61, 62 ...
Selector, 52 ... Sign invertor.

Claims (20)

[Claims] 1. An analog digital converting means for converting an input phase-modulated signal into digital data at a sampling clock which is four times the carrier frequency of the phase-modulated signal, and a numerical sequence which is orthogonal to each other A quadrature clock generation means for generating first and second quadrature clocks having the same clock and clock rate; and a first quadrature clock for multiplying the phase modulation data converted by the analog digital conversion means by the first quadrature clock. 1 multiplication means, second multiplication means for multiplying the phase modulation data converted by the analog digital conversion means by the second quadrature clock, and multiplication by the first multiplication means. Obtained by the multiplication of the first filter means for removing unnecessary harmonic components from the first detected data and the second multiplication means. Quadrature detection circuit, characterized in that it comprises a second filter means for removing unnecessary harmonic components from the second detection data. 2. A third filter means for removing unnecessary signal components from the input phase modulated signal, the third filter means being provided in the preceding stage of the analog digital converting means. Quadrature detection circuit. 3. The quadrature detection circuit according to claim 2, wherein the third filter means is a bandpass filter. 4. The quadrature detection circuit according to claim 1, wherein the first and second filter means are low-pass filters. 5. The orthogonal clock generation means outputs a repetitive data string of "1, 0, -1, 0" as the first orthogonal clock and "0, 1, 0" as the second orthogonal clock. , -1 "is output as a repeated data string.
Alternatively, the quadrature detection circuit according to claim 2. 6. The quadrature clock generation means receives a 2-bit counter means for counting the sampling clock and "0", "1" and "-1" as selection data, and counts the counter means. By selecting the selection data based on the value, a first data selecting means for generating a first orthogonal clock composed of a repeated data sequence of "1, 0, -1, 0", and "0" as the selection data. , "1", and "-1" are input, and the selection data is selected based on the count value of the counter means, whereby a second repeated data string of "0, 1, 0, -1" is formed. 6. The quadrature detection circuit according to claim 5, further comprising: second data selecting means for generating the quadrature clock. 7. The orthogonal clock generation means is "1, -1, -1, 1" as the first orthogonal clock.
Output a repetitive data string of "1, 1, -1, -1" as the second orthogonal clock.
The quadrature detection circuit according to claim 1 or 2, wherein the repetitive data string of is output. 8. The orthogonal clock generation means receives 2-bit counter means for counting the sampling clock and "1" and "-1" as selection data, and based on the count value of the counter means. By selecting the selection data, first data selecting means for generating a first orthogonal clock composed of a repeated data sequence of "1, -1, -1, 1", and "1" and " -1 "is input and the selection data is selected based on the count value of the counter means to generate a second orthogonal clock composed of a repeated data sequence of" 1, 1, -1, -1 ". The quadrature detection circuit according to claim 7, wherein the quadrature detection circuit comprises a second data selection unit. 9. An analog digital conversion means for converting an input phase modulation signal into digital data at a sampling clock of 4 times the carrier frequency of the phase modulation signal, and the analog digital conversion means. A sign inverting means for inverting the sign of the phase modulation data, a 2-bit counter means for counting the sampling clock, the phase modulation data as selection data, and an inverting phase modulation data for inverting the sign by the sign inverting means. And a data value “0” are input, and the selection data is selected based on the count value of the counter means,
First data selection means for generating first detection data, the phase modulation data as selection data, the inverted phase modulation data whose sign is inverted by the sign inverting means, and the data value "0" are input. By selecting the selection data based on the count value of the counter means,
Second data selection means for generating second detection data different from the first detection data; first filter means for removing unnecessary harmonic components from the first detection data; and second detection means. A quadrature detection circuit, comprising: a second filter means for removing unnecessary harmonic components from the data. 10. The third filter means provided in the preceding stage of the analog digital converting means, for removing an unnecessary signal component from the input phase modulation signal, according to claim 9. Quadrature detection circuit. 11. The quadrature detection circuit according to claim 10, wherein the third filter means is a bandpass filter. 12. The quadrature detection circuit according to claim 9, wherein the first and second filter means are low-pass filters. 13. The first data selecting means sequentially outputs the phase modulation data, the data value "0", the inverted phase modulation data, and the data value "0" based on the count value of the counter means. The quadrature detection circuit according to claim 9, wherein the first detection data is generated by repeatedly selecting. 14. The second data selecting means, based on the count value of the counter means, the data value “0”, the phase modulation data, the data value “0”,
10. The quadrature detection circuit according to claim 9, wherein the second detection data is generated by repeatedly selecting the inverted phase modulation data in order. 15. An analog digital converting means for converting an input phase modulated signal into digital data with a sampling clock four times as high as a carrier frequency of the phase modulated signal, and the analog digital converting means. A sign inverting means for inverting the sign of the phase modulation data, a 2-bit counter means for counting the sampling clock, the phase modulation data as selection data, and an inverting phase modulation data for inverting the sign by the sign inverting means. Is inputted and selects the selection data based on the count value of the counter means to generate first detection data, the phase modulation data as the selection data, and the code. The inverted phase modulation data whose sign is inverted by the inverting means is input, and the counter Second data selection means for generating second detection data different from the first detection data by selecting the selection data based on the count value of the means, and unnecessary harmonics from the first detection data. A quadrature detection circuit comprising first filter means for removing a component and second filter means for removing an unnecessary harmonic component from the second detection data. 16. The method according to claim 15, further comprising a third filter means provided before the analog digital converting means to remove an unnecessary signal component from the input phase modulation signal. Quadrature detection circuit. 17. The quadrature detection circuit according to claim 16, wherein the third filter means is a bandpass filter. 18. The quadrature detection circuit according to claim 15, wherein the first and second filter means are low-pass filters. 19. The first data selection means repeatedly and sequentially selects the phase modulation data, the inverted phase modulation data, the inverted phase modulation data, and the phase modulation data based on the count value of the counter means. The quadrature detection circuit according to claim 15, wherein the first detection data is thereby generated. 20. The second data selecting means repeatedly and sequentially selects the phase modulation data, the phase modulation data, the inversion phase modulation data, and the inversion phase modulation data based on the count value of the counter means. The quadrature detection circuit according to claim 15, wherein the second detection data is generated thereby.