JP2000236285A - Cdma radio receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of the CDMA(code division multiple access) radio receiver. SOLUTION: This CDMA radio receiver which performs quadrature demodulation and spread demodulation converts the output of an analog filter 101 into a digital signal 120 by an A/D converter 102, then inputs the result to a digital signal process part 104, and then only one A/D converter 102 is needed although two converters were needed conventionally, thereby reducing the power consumption. Furthermore, an quadrature demodulation and spread demodulation part 106 performs quadrature demodulation and spread demodulation at the same time to reduce the power consumption, without requiring an analog mixer which has large power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CDMA radio receiver for receiving and demodulating quadrature modulated and spread modulated signals.

[0002]

2. Description of the Related Art Recently, CDMA (Code Division Multiple Access: CDMA), which is resistant to interference and interference, has been used as a communication system for mobile communication systems.
e Access) communication system is receiving attention. This C
The DMA communication system is a communication system in which a transmitting side spreads a signal to be transmitted with a spreading code and transmits the signal, and a receiving side performs despreading using the same spreading code as the spreading code to obtain an original signal. is there.

Here, a signal transmitted as information is called a symbol, and the transmission rate of this symbol is called a symbol rate. The chip rate, which is the transmission rate of the spreading code for spreading the symbol, is several tens to several hundred times the normal symbol rate. Here, the chip is a unit of data constituting the spreading code.

In a communication system using such a CDMA system, QPSK (Quadra) is used as a modulation system.
FIG. 6 shows a part of a conventional CDMA radio receiver using a true phase shift keying (modulation) scheme.
Shown in

[0005] The CDMA radio receiver, a signal from the transmitter and received by the wireless unit, quadrature demodulation and spread demodulation and outputting data after converting the analog input signal 118 of frequency f _IF by a down-conversion 13
I have one.

The conventional CDMA radio receiver includes an analog filter 101 for limiting the band of the analog input signal 118, a quadrature demodulator 606, an A / D
It has converters 601 and 602, an oscillator 603, and a digital signal processing unit 604.

[0007] The quadrature demodulation unit 606 includes an analog filter 1
01 for quadrature demodulation of the signal band-limited by the analog mixers 607 and 610 and the oscillator 6
09 and 610.

The oscillators 609 and 610 generate and output signals of sin ωt and cos ωt whose phases are different by π / 2, respectively. The analog mixers 607 and 608 generate analog I signals and Q signals, respectively, by multiplying the signals generated by the oscillators 609 and 610 and the signals band-limited by the analog filter 101.

The oscillator 603 generates and outputs a signal having a clock frequency fs. A / D converters 601, 60
Reference numeral 2 converts analog I signals and Q signals into digital signals by sampling them at a sampling frequency fs, and outputs the digital signals. Here, although not shown in FIG. 6, when analog I signals and Q signals are input to A / D converters 601 and 602, LPFs are usually used.
(Low PassFilter).

The signal processing unit 604 includes a spread demodulation unit 605
, Baseband demodulation section 115 and next-stage signal processing section 11
6 and a control unit 117.

The spread demodulation unit 605 includes a spread code generation unit 112 and mixers 611 and 612.

The spreading code generator 112 includes a controller 117
, And generates and outputs a spreading code for performing despreading. The mixer 611 includes an I signal that is a digital signal output from the A / D converter 601;
The multiplication with the spreading code generated by the spreading code generator 112 is performed. Mixer 612 includes a Q signal that is a digital signal output from A / D converter 602,
The multiplication with the spreading code generated by the spreading code generator 112 is performed.

The demodulation section 115 outputs the despread I signal,
A signal is input and QPSK demodulation is performed. The next-stage signal processing unit 116 performs signal processing such as decoding on the signal demodulated by the baseband demodulation unit 115 to obtain output data 131 such as audio data, video data, FAX data, and PC data. I have.

The control unit 117 includes a spreading code generation unit 112
, The operation of selecting a spreading code from a plurality of spreading codes, the synchronization of a received signal with the spreading code, and the like, and the processing to the next-stage signal processing unit 116 are performed.

In this conventional CDMA radio receiver, after the analog input signal 118 is band-limited by the analog filter 101 and quadrature-demodulated by the quadrature demodulation unit 606,
A / D converters 601 and 602 convert analog signals into digital signals. Then, the I and Q signals converted into digital signals are spread-demodulated by the spread demodulation section 605, and output as output data 131 processed by the baseband demodulation section 115 and the next-stage signal processing section 116.

In the CDMA communication system, since the signal transmitted from the transmitter is spread-modulated, the frequency band of one channel is wider than that in the FDMA communication system. Therefore, a CDMA radio receiver that receives a CDMA wave requires a high sampling frequency for its A / D converter.
The power consumption of the / D converter becomes very large. The conventional CDMA radio receiver shown in FIG. 6 requires two A / D converters 601 and 602, so that the power consumption of the entire CDMA radio receiver is large.

In the conventional CDMA radio receiver, multiplication of analog signals is performed in quadrature demodulation section 606 to perform quadrature demodulation, and multiplication of digital signals is performed in spreading demodulation section 605 to perform spread demodulation. Have done. The analog mixers 607 and 608 that perform multiplication between analog signals consume more power than the digital mixers 611 and 612 that perform multiplication between digital signals. Conventional CD shown in FIG.
In the MA radio receiver, two analog mixers 607, 6
08, the power consumption of the entire CDMA radio receiver has increased.

[0018]

The above-described conventional CDM
The A radio receiver has a problem that it requires two A / D converters and an analog mixer to perform quadrature demodulation and spread demodulation, and thus consumes a large amount of power.

An object of the present invention is to provide a CD with reduced power consumption.
To provide a MA radio receiver.

[0020]

To achieve the above object, a CDMA radio receiver according to the present invention is a CDMA radio receiver for receiving and demodulating quadrature modulated and spread modulated signals, It has an A / D converter for converting a received signal into a digital signal by A / D conversion, and a digital signal processing unit for performing quadrature demodulation and spread demodulation simultaneously by digitally processing the digital signal.

Further, in the CDMA radio receiver according to the present invention, the digital signal processing unit performs quadrature demodulation and spread demodulation simultaneously by multiplying the digital signal by predetermined data, thereby obtaining an I signal and a Q signal. Quadrature demodulation
It has a spread demodulation unit.

Further, the CDMA radio receiver of the present invention
The quadrature demodulation / spreading demodulation unit generates a spreading code for performing spreading demodulation; and (1, 0,-)
(1, 0) signal is repeatedly generated and output (1, 0,
-1, 0) generator, a (0, 1, 0, -1) generator that repeatedly generates and outputs a signal of (0, 1, 0, -1), and the spreading code and (1, 0) , −1, 0), and a first mixer that multiplies the spread code by (0, 1,
0, -1), the output of the first mixer is multiplied by the digital signal, and
It comprises a third mixer for outputting as a signal, and a fourth mixer for multiplying the output of the second mixer by the digital signal and outputting as a Q signal.

In the present invention, the analog reception signal is converted to an A / D signal.
After the conversion, the quadrature demodulation and the spread demodulation are simultaneously performed in the digital signal processing unit, so that the A / D converter is compared with the case where spread demodulation and I / Q conversion are performed in the radio unit and then A / D conversion is performed. , And by simultaneously performing spread demodulation and quadrature demodulation, an analog mixer is not required and low power consumption can be realized.

[0024]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a CDMA radio receiver according to one embodiment of the present invention. Components denoted by the same reference numerals as in FIG. 6 indicate the same components.

Referring to FIG. 1, the CDMA of the present embodiment
The wireless receiver includes an analog filter 101, an A / D converter 102, an oscillator 103 that supplies a sampling clock having a frequency fs to the A / D converter 102, and a digital signal processing unit 104.

The A / D converter 102 converts the signal of the frequency f _IF band-limited by the analog filter 101 based on the sampling clock from the oscillator 102 into an A / D signal.
By performing the conversion, the digital signal 120 is generated and output. Here, the frequency fs of the sampling clock generated by the oscillator 102 is four times as high as f _IF , and four times oversampling is performed.

The digital signal processing unit 104 includes a quadrature demodulation / spreading demodulation unit 105 for quadrature demodulation and spread demodulation of the digital data 120 received from the A / D converter 102, a baseband demodulation unit 115, and a next-stage signal processing unit. 116 and a control unit 117.

The digital signal processing unit 104 comprises a DSP or CPU, a ROM and a RAM when implemented by software, and a gate array or an FPGA (Field Program) when implemented by hardware.
It may be configured by logic such as mmable Logic Array).

The quadrature demodulation / spreading demodulation unit 105 includes mixers 106, 107, 108, and 109, a spreading code generator 112, a (1, 0, -1, 0) generator 110,
(0, 1, 0, -1) generator 111.

The (1,0, -1,0) generator 110
1, 0, -1, 0 signals are repeatedly generated and output,
The (0, 1, 0, -1) generator 111 outputs 0, 1, 0,-
1 is repeatedly generated and output.

The mixer 108 includes a spread code generator 112
Is multiplied by the signal of 1, 0, -1, 0 generated by the (1, 0, -1, 0) generator 110, and the result of the multiplication is output.

The mixer 109 includes a spreading code generator 112
Is multiplied by the signal of 0, 1, 0, -1 generated by the (0, 1, 0, -1) generator 110, and the result of the multiplication is output.

The mixer 106 multiplies the digital signal 120 by the output from the mixer 108 and outputs the multiplication result to I
It is output as a signal 126.

Mixer 107 multiplies digital signal 120 by the output from mixer 109, and outputs the multiplication result as Q
It is output as a signal 127.

Next, the operation of the CDMA radio receiver according to this embodiment will be described with reference to FIG.

The analog input signal 118 is a signal that has been spread-modulated and band-limited by the analog filter 101 first.

Next, the band-limited signal is supplied to the oscillator 10
The A / D converter 102 samples and quantizes the signal by the sampling clock of the sampling frequency fs generated in Step 3. At this time, the sampling frequency fs is four times the center frequency _fIF of the signal band-limited by the analog filter 101. A
The digital signal 120 (data rate fs) sampled by the / D converter 102 is input to the digital signal processing unit 104.

The spreading code generator 112 includes a controller 117
, A spread code for despreading and spreading and demodulating the spread modulated signal is generated and output.

(1,0, -1,0) generator 110,
(0,1,0, -1) generated by the generator 111,
(1, 0, -1, 0) signal and (0, 1, 0, -1)
Is equivalent to an analog signal having a frequency fs / 4 and shifted in phase by π / 2. Quadrature demodulation can be performed by multiplying these signals by the digital signal 120. (1, 0,-)
It is an existing technology that quadrature demodulation can be easily performed by multiplying the signals of (1, 0) and (0, 1, 0, -1).

In the present embodiment, the quadrature demodulation / spreading demodulation section 105 shifts the phase by (π / 2) of the same frequency as the center frequency f _IF of the input signal to perform quadrature demodulation.
The multiplication of the (0, -1, 0) signal and the (0, 1, 0, -1) signal and the multiplication of the spreading code are simultaneously performed. That is, the mixers 108 and 109 generate the spread code
And the (1, 0, −1, 0) signal and the (0, 1, 0, −1) signal of which the phase is shifted by π / 2 phase of the frequency f _IF , respectively. The signals are multiplied and multiplied by the digital signal 120 in the mixers 106 and 107 to obtain despread I and Q signals 126 and 127.

I and Q signals 126 and 127 after quadrature demodulation
Is input to the baseband demodulation unit 115 and demodulated, and the next-stage signal processing unit 116 outputs the output data 13 such as audio data, video data, FAX data, and PC data.
Converted to 1.

Next, signal waveforms at each part of the quadrature demodulation / spreading demodulation unit 105 in the CDMA radio receiver of this embodiment are shown in FIGS. 2 (a) to 2 (g) and 3 (a) to 3 (g). 2A to _2G show the case where fs = f _tip , and FIGS. 3A to _3G show the case where fs = 2f _tip .

In this embodiment, FIG. 2A shows the digital signal 120, and D0 to D12 show the data sequence of the digital signal 120. FIG. 2B shows (1,
0, −1, 0) representing the output of the generator 110 and FIG.
Denotes the output of the (0,1,0, -1) generator 111.
The dashed lines in the figure are sin and cos waves having a frequency of fs / 4, and from this figure, the signal of (1, 0, -1, 0) and (0, 1, 0, -1) are fs / 4 It can be understood that the sin and cos waves of the above are equivalent to those sampled at the sampling rate of fs. In the present embodiment,
Since the center frequency f _IF of the digital signal 120 is fs / 4, the I and Q signals can be obtained by performing quadrature demodulation by multiplying the digital signal 120 by these signals.

FIG. 2D shows a part of the spread code generated by the spread code generator 112.
In FIG. 2, the chip rate f _tip of the spreading code is
It is equal to the sampling frequency fs of the A / D converter 102. FIG. 2E and FIG. 2F are diagrams of FIG. 2 described above.
2B shows signal waveforms obtained by multiplying the signals shown in FIGS. 2C and 2D, respectively.
08 and 109.

FIG. 2G shows a case where the data strings D0 to D12 of the digital signal 120 shown in FIG. 2A are output as I and Q signals 126 and 127 after quadrature demodulation and spread demodulation. Indicates the destination of the data. That is, D0 is I
As data, D1 is multiplied by -1 and output as Q data.

As can be seen from FIGS. 2A to 2G, the relationship between these signals is constant irrespective of the signals to be subjected to spread demodulation and quadrature demodulation, and can be calculated in advance.

As described above, the quadrature demodulation / spreading demodulation unit 105 of the present embodiment performs the operation simply by selecting and multiplying the digital signal 120 by −1, 0, and 1 simply. It can be seen that the signal 126 and the Q signal 127 are obtained.

FIGS. 3A to _3G show fs = 2f _tip.
3 shows waveforms of the respective sections in the quadrature demodulation / spreading demodulation section 105 in the case of FIG.

FIGS. 3 (a) to 3 (c) show FIGS.
The same signal waveform as in FIG. 2 (c) is shown.

FIG. 3D shows a part of the spread code generated by the spread code generator 112.
In FIG. 3, the chip rate f _tip of the spreading code is
The frequency is fs / 2, which is half the sampling frequency of the A / D converter 102. FIG. 3 (e), FIG.
3 (f) shows signal waveforms obtained by multiplying the above-described signals of FIGS. 3 (b), 3 (c) and 3 (d), respectively, from the mixers 108 and 109 in FIG. This is the output signal.

FIG. 3G shows a case where the data strings D0 to D12 of the digital signal 120 shown in FIG. 3A are output as I and Q signals 126 and 127 after quadrature demodulation and spread demodulation. Indicates the destination of the data. That is, D0 is-
D1 is output as I data by multiplying by 1, and D1 is output as Q data by multiplying by -1.

As can be seen from FIGS. 3A to 3G, the relationship between these signals is constant irrespective of the signals subjected to spread demodulation and quadrature demodulation, and can be calculated in advance.

As described above, the sampling frequency fs of the A / D converter 105 is set to the chip rate f _{tip of the} spread code.
Is twice as simple as digital signal 1
It can be seen that the I signal 126 and the Q signal 127 can be obtained only by selecting and multiplying -1, 0, and 1 for 20. This indicates that the same can be said when the sampling frequency fs is an integral multiple of _ftip .

As described with reference to FIGS. 2G and 3G, the quadrature demodulation / spreading demodulation unit 105 in FIG.
Very simply, for digital signal 120, -1,
The operation of selecting only 0 and 1 and multiplying the I signal 12
6. The Q signal 127 is obtained. FIG. 4 is a block diagram for conceptually explaining the operation of the orthogonal demodulation / spreading demodulation unit 105.

Referring to FIG. 4, quadrature demodulation / spreading demodulation section 105 has an inverter 401 and a switch 402.

The inverter 401 outputs the digital signal 12
A signal of -1 times 0 is output to the switch 402. The switch 402 multiplies the digital signal 120 by 1, 0, -1 by selecting either the digital signal 120 or the signal from the inverter 401 which is -1 times the digital signal 120, or not outputting either signal. ,
They are output as an I signal 126 and a Q signal 127, respectively.
The selection logic performed by the switch 402 is performed in the mixers 106 and 107 shown in FIG.

FIG. 2 (g) or FIG.
It can be seen that the operation during reception is reduced by switching the switch 402 using the relationship (g).

Next, with reference to FIG. 5, the frequency relationship between the frequency f _IF of the signal after passing through the analog filter 101 and the digital signal 120 that is the signal after A / D conversion will be described.

FIG. 5A shows that the frequency f _{IF of} the signal output from the analog filter 101 is _equal to the sampling frequency fs.
FIG. 5B shows a case where the frequency f _{IF of} the signal output from the analog filter 101 is ／ times the sampling frequency fs.

In the case shown in FIG. 5A, the analog filter 101 in FIG. 1 has a low-pass filter characteristic as shown in FIG.

FIG. 5B shows that the frequency f _IF of the signal 119 in FIG. 1 is 5/4 of the sampling frequency fs.
The case of double is shown. At this time, the analog filter 101 of FIG. 1 has the band of the band-pass filter band of FIG.
In the signal 120 after the D sampling, the center signal frequency is turned back to fs / 4. Similarly, even when the frequency f _IF of the signal 119 in FIG. 1 is ４ and ／ of the sampling frequency fs, the center signal frequency is fs / 4. Therefore, when the signal frequency of the A / D input is (１ ／) × i times (i: odd number) the sampling frequency of the A / D converter, the method described in this embodiment may be used. I can see what I can do.

When the signal frequency of the A / D input is A / D
The method described in the present embodiment can also be used when the sampling frequency is (１ ／) * m times (m: even number) the sampling frequency of the D converter.

As described above, the CD of the present embodiment
In order to use the MA radio receiver, the signal frequency f _IF input to the A / D converter is (１ ／) * k times (k: an integer) the sampling frequency fs of the A / D converter 102, and A / D D
The condition is that the sampling frequency fs of the converter 102 is an integral multiple of the chip rate of the spreading code.

In the present embodiment, a spreading code for spread demodulation is multiplied by a (1, 0, -1, 0) signal and (0, 1, 0, -1) signal for quadrature demodulation. ,
Spread demodulation and quadrature demodulation are performed simultaneously by multiplying the obtained signal by the digital signal 120. However, the present invention is not limited to such a case, and the spread code and (1, 0,- 1, 0) generator 110 or
A signal obtained by multiplying the signal output from the (0, 1, 0, -1) generator 111 is stored in advance, and the stored signal is multiplied by the digital signal 120 to perform spread demodulation. Orthogonal demodulation may be performed simultaneously.

[0065]

As described above, the CDMA of the present invention
The wireless receiver requires only one A / D converter and has an effect that power consumption can be reduced by eliminating the need for an analog mixer and an LPF.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a part of a configuration of a CDMA wireless receiver according to an embodiment of the present invention.

FIG. 2 shows a quadrature demodulation / spreading demodulation unit 105 in FIG.
FIG. 8 is a diagram for explaining the operation when fs = f _tip .

FIG. 3 shows a quadrature demodulation / spreading demodulation unit 105 in FIG.
FIG. 8 is a diagram for explaining the operation when fs = 2f _tip .

FIG. 4 is a block diagram conceptually illustrating the operation of quadrature demodulation / spreading demodulation section 105 in FIG.

FIG. 5A shows that the frequency f _{IF of} the signal output from the analog filter 101 is equal to 1 of the sampling frequency fs.
A / D-converted digital signal 1
Shows the frequency of 20, the frequency of FIG. 5 (b) when the frequency f _IF of the signal outputted from the analog filter 101 is 5/4 times the sampling frequency fs, the digital signal 120 after A / D conversion FIG.

FIG. 6 is a block diagram showing a configuration of a conventional CDMA radio receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Analog filter 102 A / D converter 103 Oscillator 104 Digital signal processing unit 105 Quadrature demodulation / spreading demodulation unit 106-1109 Mixer 110 (1, 0, -1, 0) generator 111 (0, 1, 0, -1) ) Generator 112 Spreading code generator 115 Baseband demodulator 116 Next stage signal processor 117 Controller 118 Analog input signal 120 Digital signal 126 I signal 127 Q signal 131 Output data 401 Inverter 402 Switch 601, 602 A / D converter 604 Digital signal processing unit 605 Spread demodulation unit 606 Quadrature demodulation unit 607, 608 Analog mixer 609, 610 Oscillator 611, 612 Mixer

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 10, 2000 (2004.1.
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

2. A method for simultaneously performing orthogonal demodulation and spread demodulation.
A stage , a spreading code generator for generating a spreading code for performing spread demodulation, and a (1, 0, -1, 0) generator for repeatedly generating and outputting a signal of (1, 0, -1, 0) (0, 1, 0, -1) generator for repeatedly generating and outputting a signal (0, 1, 0, -1); and the spreading code and (1, 0, -1, 0) A first mixer that multiplies the spread code by a signal of (0, 1, 0, −1); an output of the first mixer and the digital signal; multiplied by a third mixer output as the I signal, said second multiplying the output of the mixer and the said digital signal, the fourth mixer with claim 1, characterized in that consists of outputting the Q signal CDMA radio receiver.

Wherein the digital signal processing unit, according to claim 2, further comprising a control unit that performs synchronous control type selection and the digital signal of the spreading code which the spreading code generating section generates and spreading code C
DMA radio receiver.

4. A hand performing spread demodulation with the orthogonal demodulation simultaneously
The stage includes a spreading code for performing spreading demodulation and (1, 0, -1,
A first storage means for storing data obtained by multiplying the signal of (0), a spreading code for performing spread demodulation, and (0, 1, 0,-).
A second storage unit for storing data obtained by multiplying the signal of 1), and a first mixer for multiplying the digital signal by the data stored in the first storage unit and outputting an I signal When the second data stored in the storage means and multiplying the digital signal, CDMA radio receiver of the second mixer with claim 1, characterized in that consists of the output as a Q signal.

Wherein said digital signal processing unit, the despread I signal, and a baseband demodulator for performing QPSK demodulation enter the Q signal, signal to signal demodulated by the baseband demodulation unit The CDMA radio receiver according to any one of claims 1 to 4 , further comprising a next-stage signal processing unit for obtaining output data by performing processing.

Claims (7)

[Claims] 1. A CDMA radio receiver for receiving and demodulating quadrature-modulated and spread-modulated signals, wherein the A / D converter converts the received signals into digital signals.
A CDMA radio receiver comprising: a converter; and a digital signal processing unit that performs quadrature demodulation and spread demodulation simultaneously by digitally processing the digital signal. 2. The digital signal processing section has a quadrature demodulation / spreading demodulation section that performs quadrature demodulation and spread demodulation simultaneously by multiplying the digital signal by predetermined data to produce I and Q signals. The CDMA radio receiver according to claim 1. 3. The method according to claim 1, wherein the predetermined data includes a spreading code for performing spreading demodulation, and (1, 0, −1,
0), and (0, 1, 0,-)
3. The CD according to claim 2, wherein the data obtained by multiplying the signal of (1) by a repeated signal.
MA radio receiver. 4. The quadrature demodulation / spreading demodulation unit generates a spreading code for performing spreading demodulation, and a signal of (1, 0, −1, 0) is repeatedly generated and output. A (1, 0, -1, 0) generator; a (0, 1, 0, -1) generator that repeatedly generates and outputs a signal of (0, 1, 0, -1); A first mixer for multiplying the signal of (1, 0, -1, 0) by a second mixer for multiplying the spreading code by a signal of (0, 1, 0, -1); A third mixer that multiplies the output of the first mixer by the digital signal and outputs the result as an I signal; and a fourth mixer that multiplies the output of the second mixer by the digital signal and outputs the result as a Q signal. 3. The CDMA radio receiver according to claim 2, comprising a mixer. 5. The digital signal processing unit further comprises a control unit for selecting a type of a spread code generated by the spread code generation unit and controlling synchronization between the digital signal and the spread code. C
DMA radio receiver. 6. The quadrature demodulation / spreading demodulation unit includes a spreading code for performing spreading demodulation and (1, 0, −1,
A first storage means for storing data obtained by multiplying the signal of (0), a spreading code for performing spread demodulation, and (0, 1, 0,-).
A second storage unit for storing data obtained by multiplying the signal of 1), and a first mixer for multiplying the digital signal by the data stored in the first storage unit and outputting an I signal 3. The CDMA radio receiver according to claim 2, further comprising: a second mixer that multiplies the data stored in the second storage unit with the digital signal and outputs the result as a Q signal. 7. A baseband demodulation unit for receiving the despread I signal and Q signal and performing QPSK demodulation, and a digital signal processing unit for receiving a signal demodulated by the baseband demodulation unit. 7. The CDMA radio receiver according to claim 1, further comprising a next-stage signal processing unit for obtaining output data by performing processing.