JP3864034B2 - Wave shaping digital filter circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a waveform shaping digital filter circuit, and more particularly to a configuration in which waveform shaping of a transmission signal in a digital communication wireless system is performed by a digital filter.
[0002]
[Prior art]
In a digital radio communication system, there is a method for performing waveform shaping of a transmission signal with a digital filter (hereinafter referred to as a digital waveform shaping filter method). An example of a transmission unit using the digital waveform shaping filter method (hereinafter referred to as a conventional filter use example) will be described with reference to FIG.
[0003]
The system configuration shown in FIG. 24 includes a baseband signal generator 101, upsamplers 102 and 104, a waveform shaping filter 103, a low pass filter (LPF) 105, an intermediate frequency generator 106, an orthogonal converter 107, and a digital / analog converter. (D / A) 108 and a band pass filter (BPF) 109 are provided. The processing from the baseband signal generator 101 to the orthogonal transformer 107 is digital, and the bandpass filter 109 and the subsequent signal processing are analog.
[0004]
Up-samplers 102 and 104, waveform shaping filter 103, and low-pass filter 105 are arranged corresponding to each of I channel (I-ch) and Q channel (Q-ch).
[0005]
The baseband signal generator 101 generates baseband signals for I channel (I-ch) and Q channel (Q-ch) based on the input data. In practice, QPSK baseband signals (QPSK: Quadrature Phase Shift Keying) are generated in parallel by the number of multiples of 1 to 40 based on the input data series. The number of multiplexing is determined by an upper layer (not shown). These signals are spread using different spreading codes, added together, and output. Here, the chip rate of the spreading code is Fcp. In the example shown in FIG. 24, Fcp = 3 MHz. The output I-band and Q-channel baseband signals are spread spectrum signals of chip rate Fcp taking values of 0, ± 1, ± 2,.
[0006]
The upsampler 102 receives a chip rate Fcp signal, performs upsampling Nfos times, converts the signal to a sampling rate Fsa, and outputs the signal. For these values, equation (1) holds.
[0007]
Fsa = Fcp × Nfos (1)
In the above example, Nfos = 4 and Fsa = 12 MHz. Hereinafter, Nfos is referred to as the oversampling number of the waveform shaping filter.
[0008]
The relationship between the input signal to the upsampler 102 and the output signal will be described with reference to FIG. In the figure, symbol 321 represents chip data and symbol 322 represents a “0” value. As shown in FIG. 25, an upsampler converts an input signal INx that changes every chip cycle Tcp (= 1 / Fcp) into an output signal OUTx that changes every sampling cycle Tsa (= 1 / Fsa). In the output signal OUTx, a value “0” is inserted between each chip data 321 generated every chip cycle Tcp (= 1 / Fcp).
[0009]
The waveform shaping filter 103 limits the bandwidth of the input baseband signal. The conventional waveform shaping filter 103 includes a shift register unit 410, a multiplication unit 420, and an adder 430, as shown in FIG. The shift register unit 410 includes a plurality (11) of registers D. Multiplier 420 includes a multiplier corresponding to each register.
[0010]
In the waveform shaping filter 103, the input signal is shifted by the shift register unit 410, the tap coefficients W1 to W11 are multiplied by the multiplication unit 420, and all the output values of the multiplication unit 420 are added by the adder 430 and output.
[0011]
The spectrum of the output signal of the waveform shaping filter 103 is shown in FIG. In the figure, the horizontal axis represents frequency and the vertical axis represents power density. As shown in FIG. 27, it can be seen that the band-limited output signal 611 exists around the baseband. A folded spectrum 612 is generated around the sampling rate Fsa = 12 MHz.
[0012]
The impulse response of the waveform shaping filter 103 is shown in FIG. In the figure, the horizontal axis represents time and the vertical axis represents the output value. As shown in FIG. 28, during the impulse response of the waveform shaping filter 103, the values of the tap coefficients W1 to W11 are output in order for each sampling period Tsa. If the tap number of the filter is N tap, N tap = 11 in this example. The duration of the impulse response is expressed by equation (2).
[0013]
Duration time = Tsa × Ntap (2)
Here, the chip length Ncd of the impulse response of the waveform shaping filter is defined by Expression (3).
[0014]
Tcp × Ncd = Tsa × Ntap (3)
In the above example, Ncd = 2.75. Moreover, Formula (4) is materialized.
[0015]
Ntap = Nfos × Ncd (4)
The operation of the upsampler 104 shown in FIG. 24 is basically the same as the operation of the upsampler 102. The upsampler 104 receives a signal of the sampling rate Fsa, performs unsampling of Nifos times, converts it to a signal of the sampling rate Fifos, and outputs it. Equation (5) is established for such a value.
[0016]
Fifos = Fsa × Nifos (5)
In the above example, Nifos = 5 and Fifos = 60 MHz.
[0017]
The spectrum of the output signal of the upsampler 104 is shown in FIG. In the figure, the horizontal axis represents frequency and the vertical axis represents power density. As shown in FIG. 29, in addition to the desired spectrum 711 in the vicinity of the baseband, a folded spectrum 712 is generated at each sampling rate Fsa = 12 MHz.
[0018]
The low-pass filter 105 shown in FIG. 24 attenuates these folded spectra and extracts a desired baseband spectrum. The low-pass filter 105 has a frequency characteristic indicated by a broken line 713 in FIG. Since this filter is a digital filter, there is also a pass band around the operating frequency Fifos = 60 MHz.
[0019]
The spectrum of the output signal of the low-pass filter 105 is shown in FIG. In the figure, the horizontal axis represents frequency and the vertical axis represents power density. The spectrum 812 of the output signal becomes a folded spectrum attenuated by the low pass filter 105. The degree of attenuation depends on the performance of the low-pass filter 105.
[0020]
The intermediate frequency generator 106 shown in FIG. 24 generates an intermediate frequency of the frequency Fif. In this example, Fif = 15 MHz.
[0021]
The quadrature converter 107 performs quadrature modulation of the intermediate frequency using the input I-channel and Q-channel baseband signals. The processing so far is performed digitally.
[0022]
The spectrum of the output signal of the orthogonal transformer 107 is shown in FIG. In the figure, the horizontal axis represents frequency and the vertical axis represents power density. Since the orthogonal transformer 107 performs multiplication of the intermediate frequency, a spectrum is generated around the frequency ± Fif + m × Fifos + n × Fsa (where m and n are integers). Among these, a spectrum 911 generated around the intermediate frequency Fif = 15 MHz is a desired spectrum. The remaining spectrum 912 is a folded spectrum and is unnecessary. The desired spectrum is extracted by the band pass filter 109.
[0023]
The bandpass filter 109 shown in FIG. 24 receives the output of the digital / analog converter 108 that receives the output of the orthogonal transformer 107 and extracts a desired desired spectrum. The band pass filter 109 has a frequency characteristic indicated by a hatched line 913 in FIG.
[0024]
The digital transmission signal thus generated is converted into an analog signal by the digital / analog converter 108, and an unnecessary frequency is cut by the band-pass filter 109.
[0025]
Since the digital waveform shaping filter method described above performs band limiting processing digitally, it is possible to configure an arbitrary impulse response filter that cannot be realized with an analog filter. Further, in the conventional configuration described above, processing up to the orthogonal transformation is performed digitally. However, the orthogonality between the I channel and the Q channel is good, and high-precision modulation can be performed. In order to perform digital up to quadrature modulation, it is also necessary to perform filtering processing digitally. Furthermore, these digital systems perform communication using a plurality of wireless communication systems by switching a plurality of data relating to the hardware configuration of the modulator / demodulator corresponding to different wireless communication systems in the same wireless engine. It has a high affinity with software radios. For these reasons, it is considered that the adoption of the digital waveform shaping filter method will greatly advance in the future.
[0026]
[Problems to be solved by the invention]
However, the conventional waveform shaping digital filter described above has the following problems. FIG. 32 shows details of the output of the shift register unit 410 and the output of the multiplication unit 420 in FIG. Referring to FIG. 32, since the input data is up-sampled, an actual meaningful value is present in an average of Ncd out of all Ntap registers at a certain moment, and other Ntp-Ncds. = Ncd × (Nfos−1) register values are “0”.
[0027]
Since the output of the multiplier corresponding to the register containing “0” is also “0”, these Ncd × (Nfos−1) multipliers do not function.
[0028]
Furthermore, the input of the adder corresponding to these is also “0”, which is not functioning. The ratio of the registers, multipliers, and adders that are actually functioning to the inputs of all the registers, multipliers, and adders is Ncd / Ntap = 1 / Nfos.
[0029]
That is, as the oversampling number Nfos of the waveform shaping filter is increased, the proportion of the actually functioning portion is reduced, and the number of useless (non-operating) circuits is increased.
[0030]
On the other hand, when the oversampling number Nfos of the waveform shaping filter is increased, the following advantages occur.
[0031]
As an example, first consider the case where Nfos = 4 is set to Nfos = 10 in the above-described conventional filter use example. Since it is a required specification, Ffp = 3 MHz and Fifos = 60 MHz are assumed to be the same as before because of restrictions on circuit element performance. Therefore, Nfos × Nifos = Fifos / Fcp = 20 is also constant. Nifos = 5 is Nifos = 2. Further, depending on the spectrum interval, Fif = 15 MHz is set to Fif = 21 MHz.
[0032]
The spectrums of the output signals of the waveform shaping filter 103, the upsampler 104, the low-pass filter 105, and the orthogonal transformer 107 at this time are shown in FIGS. 33, 34, 35, and 36, respectively. In any of the figures, the horizontal axis represents frequency and the vertical axis represents power density. When FIG. 33, FIG. 34, FIG. 35, and FIG. 36 are compared with the spectra shown in FIG. 27, FIG. 29, FIG. 30, and FIG. Therefore, it can be seen that by increasing the oversampling number Nfos, the performance required for the low-pass filter and the band-pass filter is also reduced as indicated by the broken lines 723 and 923, respectively.
[0033]
As a further example, consider the case where Nfos = 20 and Nifos = 1. The spectrums of the output signals of the waveform shaping filter 103, the upsampler 104, the low-pass filter 105, and the orthogonal transformer 107 at this time are shown in FIGS. 37, 38, 39, and 40, respectively. In any of the figures, the horizontal axis represents frequency and the vertical axis represents power density. The spectra in FIGS. 37, 38, and 39 are all the same. If the sampling rate Fifos = 60 MHz of the orthogonal transformer 107 and the sampling rate Fsa = 60 MHz of the waveform shaping filter 103 are made the same as in this example, the upsampler 104 and the low-pass filter 105 are not necessary. Furthermore, the performance required for the bandpass filter is further relaxed as indicated by a broken line 933. Furthermore, since the generation frequency of the folding frequency becomes wide, it is possible to access different frequency channels 934 by changing the intermediate frequency Fif = 15 MHz generated by the intermediate frequency generator 106 to Fif = 20 MHz and Fif = 10 MHz. .
[0034]
In this method, since the frequency channel is switched by the digital unit, it is possible to switch the frequency with high performance such as 1 / hundreds of millions, and since the switching time is remarkably shortened to several clocks, frequency hopping, etc. Therefore, it is possible to cope with a modulation system that requires complicated frequency switching.
[0035]
Because of these various advantages, there is an increasing demand for a waveform shaping filter having a large oversampling number Nfos regardless of the above-described problems.
[0036]
Therefore, in order to keep the filter performance above a certain level, it is necessary to increase the oversampling number Nfos while keeping the chip length Ncd of the impulse response of the waveform shaping filter and the number of quantization bits of the signal to be processed above a certain value. .
[0037]
However, in order to create such a filter, as described above, the number of non-functional multipliers Ncd × (Nfos−1) although the number Ncd of multipliers that function at a certain moment does not change much. ) Greatly increases. The same applies to the inputs of registers and adders. That is, the useless circuit scale must be increased.
[0038]
In order to cope with such a problem, there is a circuit size reduction method using a ROM (Read Only Memory) as shown in Japanese Patent Laid-Open No. 11-251963 (Direct Spread Spectrum Digital Filter). In order to perform filtering of a modulation signal such as 40 × 40 QAM (QAM: Quadrature Amplitude Modulation) shown in the above-described conventional filter use example, the required ROM capacity becomes enormous and difficult to realize. is there.
[0039]
Accordingly, the present invention has been made to solve such problems, and an object of the present invention is to provide a waveform shaping digital filter circuit having a smaller oversampling number Nfos with a smaller circuit scale.
[0040]
[Means for Solving the Problems]
A waveform shaping digital filter circuit according to an aspect of the present invention is a waveform shaping digital filter circuit that shapes a waveform of a signal, a register that shifts input data, output data from the register based on output data from the register, and With the same number of types of tap coefficients as the number of oversampling Product A variable tap coefficient multiplier for output and an adder for adding all the results multiplied by the variable tap coefficient multiplier are provided.
[0041]
Preferably, the variable tap coefficient multiplier includes a tap coefficient multiplier that calculates a product of input data and a tap coefficient, and a multiplication result sequential output unit that sequentially outputs output data of the tap coefficient multiplier.
[0042]
More preferably, the multiplication result sequential output unit includes a selector that sequentially selects and outputs the output data of the tap coefficient multiplier. Alternatively, the multiplication result sequential output unit includes a shift register that loads the output data from the tap coefficient multiplier and outputs the data while shifting the data sequentially.
[0043]
Preferably, the variable tap coefficient multiplier includes a tap coefficient sequential output unit that sequentially outputs tap coefficients, and a multiplier that calculates a product of an output of the tap coefficient sequential output unit and input data.
[0044]
More preferably, the tap coefficient sequential output unit includes a selector that sequentially selects and outputs the tap coefficients. Alternatively, the tap coefficient sequential output unit includes a shift register that loads tap coefficients and outputs the tap coefficients while sequentially shifting them.
[0045]
Therefore, according to the above configuration, it is possible to realize a waveform shaping digital filter circuit having a large oversampling number Nfos with a smaller circuit scale. The effect of reducing the circuit scale in comparison with the conventional filter increases as the filter oversampling number Nfos increases.
[0046]
In addition, the upsampler 102 inserted in the previous stage of the waveform shaping filter is not necessary in the related art, and the circuit scale can be reduced.
[0047]
Furthermore, the number of data shift registers and the number of inputs of the adder are approximately 1 / Nfos of the oversampling number Nfos, and the circuit scale can be reduced.
[0048]
A waveform shaping digital filter circuit according to a further aspect of the present invention is a waveform shaping digital filter circuit that shapes a waveform of a signal, a register that shifts input data, a sign inverter that multiplies input data by “−1”, and An inverted data register for shifting the output of the sign inverter, and a register Output data from And output data from the inverted data register By multiplying the output data corresponding to the sign of the tap coefficient by the absolute value of the tap coefficient. , The product of the output data from the register and the same number of types of tap coefficients as the number of oversampling Sequentially Output Multiple A variable tap coefficient multiplier; Multiple Variable tap coefficient multiplier The product received from And an adder for adding.
[0049]
Preferably, the variable tap coefficient multiplier is a register From Output data and Inverted data register From Output data A plurality of output data corresponding to the sign of the tap coefficient and the absolute value of the tap coefficient. A tap coefficient multiplier; Multiple A multiplication result sequential output device for sequentially outputting output data from the tap coefficient multiplier.
[0050]
More preferably, the multiplication result sequential output unit is Multiple A selector that sequentially selects and outputs the output data from the tap coefficient multiplier is included. Or the multiplication result sequential output device Multiple It includes a shift register that loads output data from the tap coefficient multiplier and outputs the data while shifting the data sequentially.
[0051]
Preferably, the variable tap coefficient multiplier includes a tap coefficient sequential output unit that sequentially outputs an absolute value of the tap coefficient, output data from the register when the sign of the tap coefficient is positive, and a negative sign of the tap coefficient. Select output data of inverted data register at a certain time Then output And the product of the output from the tap coefficient sequential output device and the output from the code selector. output And a multiplier.
[0052]
More preferably, the tap coefficient sequential output unit includes a selector that sequentially selects and outputs the absolute values of the tap coefficients. Alternatively, the tap coefficient sequential output unit includes a shift register that loads the absolute values of the tap coefficients and outputs them while sequentially shifting them.
[0053]
By using inverted input data obtained by inverting the input data in accordance with the above configuration, the number of data shift registers is approximately two times Nfos with respect to the oversampling number Nfos, and the number of inputs of the adder is about one Nfos The circuit scale can be reduced.
[0054]
Furthermore, the number of multipliers is approximately 1 / Nfos of the oversampling number Nfos, and the circuit scale can be reduced.
[0055]
In addition, the upsampler 102 inserted in the previous stage of the waveform shaping filter is not necessary in the related art, and the circuit scale can be reduced.
[0056]
A waveform shaping digital filter circuit according to a further aspect of the present invention is a waveform shaping digital filter circuit that shapes a waveform of a signal, a register that shifts input data, output data from the register based on output data from the register, and With any number of tap coefficients prepared in advance Product A variable tap coefficient multiplier for output and an adder for adding all the results multiplied by the variable tap coefficient multiplier are provided.
[0057]
Preferably, the variable tap coefficient multiplier calculates a product of a tap coefficient selector that selects and outputs one of an arbitrary number of tap coefficients, and an output from the tap coefficient selector and input data. And a multiplier.
[0058]
More preferably, the tap coefficient selector includes a selector that selects and outputs one of an arbitrary number of tap coefficients. In particular, the selector is 2 ^T One is selected from the tap coefficients (where T is an arbitrary number).
[0059]
According to the above configuration, the upsampler 102 inserted in the previous stage of the waveform shaping filter is not necessary in the related art, and the circuit scale can be reduced.
[0060]
Even if the oversampling number Nfos is not an integer, a filter can be realized with a small circuit configuration without adding a special signal processing circuit.
[0061]
A waveform shaping digital filter circuit according to a further aspect of the present invention is a waveform shaping digital filter circuit that shapes a waveform of a signal, a register that shifts input data, output data from the register based on output data from the register, and The value obtained by interpolating two consecutive tap coefficients out of an arbitrary number of tap coefficients prepared in advance Product A variable tap coefficient multiplier for output and an adder for adding all the results multiplied by the variable tap coefficient multiplier are provided.
[0062]
Preferably, the variable tap coefficient multiplier includes a tap coefficient output unit that outputs a value obtained by interpolating two consecutive tap coefficients among an arbitrary number of tap coefficients, an output from the tap coefficient output unit, and input data; And a multiplier for calculating the product of.
[0063]
More preferably, the tap coefficient output unit selects a selector that outputs two consecutive tap coefficients from an arbitrary number of tap coefficients, and an interpolation that interpolates two consecutive tap coefficients output from the selector. Including
[0064]
In particular, the interpolator has Vcoe = W (j) where two consecutive tap coefficients are W (j) and W (j + 1), the value after interpolation is Vcoe, and the interpolation coefficient input from the outside is k. A value Vcoe obtained by x (1-k) + W (j + 1) * k is output. Selector is prepared in advance 2 ^T Two consecutive tap coefficients are selected from +1 (where T is the arbitrary number) tap coefficients.
[0065]
More preferably, the variable tap coefficient output unit selects and outputs one of the two consecutive tap coefficients of an arbitrary number of tap coefficients and a difference value of the two consecutive tap coefficients. And an interpolator that calculates an interpolation value using the tap coefficient and the difference value output from the selector.
[0066]
In particular, the interpolator sets two consecutive tap coefficients to W (j), W (j + 1), sets the difference value to Wd (j) = W (j + 1) −W (j), and sets the value after interpolation to Vcoe. When the interpolation coefficient inputted from the outside is k, a value Vcoe obtained by Vcoe = W (j) + W (j) d × k is output. Selector is prepared in advance 2 ^T (Where T is an arbitrary number) tap coefficients and 2 ^T One set is selected from the set of the difference values.
[0067]
According to the above configuration, the upsampler 102 inserted in the previous stage of the waveform shaping filter is not necessary in the related art, and the circuit scale can be reduced.
[0068]
Even if the oversampling number Nfos is not an integer, a filter can be realized with a small circuit configuration without adding a special signal processing circuit. In particular, since the tap coefficients are interpolated, the circuit configuration for realizing the same performance becomes smaller.
[0069]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is omitted.
[0070]
A waveform shaping filter according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a state in which a waveform shaping filter according to an embodiment of the present invention described below is employed in a transmission unit of a wireless communication system.
[0071]
The system configuration shown in FIG. 1 includes a baseband signal generator 101, a waveform shaping filter 203, an intermediate frequency generator 106, an orthogonal transformer 107, a digital / analog converter (D / A) 108, and a bandpass filter (BPF). 109. The waveform shaping filter 203 is provided corresponding to each of the I channel and the Q channel.
[0072]
Digital signal processing is performed from the baseband signal generator 101 to the orthogonal transformer 107, and the output of the orthogonal transformer 107 is supplied to the bandpass filter 109 via the D / A converter 108. The band-pass filter 109 and subsequent processes perform analog signal processing.
[0073]
It can be seen that the upsampler 102 is unnecessary as compared with the conventional configuration. Further, according to the present invention, a waveform shaping filter having a large oversampling number Nfos can be easily realized, so that the sampling rate Fsa of the filter and the sampling rate Fifos of the orthogonal transformer 107 can be easily made the same. Therefore, the upsampler 104 and the low-pass filter 105 are not necessary.
[0074]
Therefore, instead of the above-described conventional filter use example, it is possible to adopt a simplified system configuration shown in FIG. Hereinafter, specific circuit configurations in the first to tenth embodiments will be described.
[0075]
[First Embodiment]
A waveform shaping filter 203A according to the first embodiment is shown in FIG. As shown in FIG. 2, the waveform shaping filter 203A according to the first embodiment includes a shift register unit 1110, a variable tap coefficient multiplication unit 1120A, and an adder 1130. In the figure, the shift register unit 1110 includes three registers D, and the variable tap coefficient multiplier 1120A includes variable tap coefficient multipliers 1121A, 1122A, and 1123A.
[0076]
The shift register unit 1110 latches and shifts chip data as input data Data using the chip timing CT as an enable signal. The chip data shifted in this way is input to the variable tap coefficient multiplier.
[0077]
The variable tap coefficient multiplication unit 1120A multiplies the output of the shift register unit 1110 and the tap coefficient and outputs the result. All the outputs of the variable tap coefficient multipliers 1121A to 1123A are added by the adder 1130 and output.
[0078]
The waveform shaping filter 203A according to the first embodiment realizes the same function as a conventional waveform shaping filter with a tap number Ntap of 11 and an oversampling number Nfos of 4. The number of inputs to the data shift register and the adder is 11 in the conventional waveform shaping filter, but is 3 in the waveform shaping filter 203A shown in FIG. .
[0079]
That is, according to the configuration of the present invention, these numbers are generally reduced to about 1 / Nfos, and the reduction rate increases as the oversampling number Nfos increases. Note that the fact that the number of inputs of the adder is reduced to 1 / Nfos means that the circuit scale of the adder is also reduced to approximately 1 / Nfos.
[0080]
The waveform shaping filter 203A is mounted on the wireless communication system 9000 shown in FIG. A wireless communication system 9000 shown in FIG. 3 includes a clock generator 9001, a chip timing generator 9002, and a counter 9003 in addition to the system configuration shown in FIG. A waveform shaping filter 1000 in the figure corresponds to the waveform shaping filter according to the first to seventh embodiments.
[0081]
The clock generator 9001 generates a clock CLK that oscillates at a constant period. The chip timing generator 9002 generates chip timing CT that is activated at regular intervals based on the clock CLK. The counter 9003 is a counter that receives the clock CLK at the clock input terminal and the chip timing CT at the synchronous reset input terminal. The counter 9003 counts the clock CLK and outputs a counter value C, and resets the counter value C according to the chip timing CT.
[0082]
The clock CLK has the same frequency as the sampling rate Fsa of the filter, and the chip timing CT has the same cycle as the chip cycle Tcp.
[0083]
The operation of the waveform shaping filter according to the first embodiment will be described. When the waveform shaping filter 203 is employed in the wireless communication system 9000 shown in FIG. 3, the operation shown in FIG. 4 is realized. In FIG. 4, IN represents the input of the variable tap coefficient multiplier 1121A, and OUT represents the output of the variable tap coefficient multiplier 1121A.
[0084]
Referring to FIG. 4, input signal IN of variable tap coefficient multiplier 1121A is input every chip cycle Tcp in synchronization with chip timing CT. In this example, the variable tap coefficient multiplier 1121A outputs the product of the input signal IN and the tap coefficient W1 from the timing of the next clock CLK when the chip timing CT becomes H level. Thereafter, the products of tap coefficients W2, W3, and W4 are sequentially output in synchronization with the clock CLK at every sampling period Tsa (output signal OUT).
[0085]
An example of the internal configuration of such a variable tap coefficient multiplier 1121A is shown in FIG. As shown in FIG. 5, variable tap coefficient multiplier 1121A includes multipliers 1311 to 1314 for multiplying tap coefficients, and a multiplication result sequential output unit 1300A for sequentially outputting the results of multipliers 1311 to 1314. . Multipliers 1311, 1312, 1313, and 1314 multiply tap coefficients W1, W2, W3, and W4.
[0086]
In the first embodiment, the multiplication result sequential output unit 1300A includes a selector 1301. The selector 1301 selectively outputs a signal output from the corresponding multiplier based on the counter value C generated by the counter 9003. Specifically, if the counter value C is 1, 2, 3, 4, the outputs of the multipliers 1311, 1312, 1313, 1314 are selectively output, respectively.
[0087]
Note that the counter 9003 described above starts counting from the timing of the next clock CLK when the chip timing CT becomes H level, and generates a counter value C.
[0088]
Other variable tap coefficient multipliers 1122A and 1123A have the same configuration and operation as variable tap coefficient multiplier 1121A. However, instead of [W1, W2, W3, W4], [W5, W6, W7, W8] and {W9, W10, W11, W12} are used as tap coefficients, respectively.
[0089]
[Second Embodiment]
In the second embodiment, a variable tap coefficient multiplier 1121B is arranged instead of the variable tap coefficient multiplier 1121A (1122A, 1123A) according to the first embodiment. The variable tap coefficient multiplier including variable tap coefficient multiplier 1121B performs the same operation as variable tap coefficient multiplier 1120A, but the internal configuration is different.
[0090]
An example of the internal configuration of the variable tap coefficient multiplier 1121B is shown in FIG. 6, and the operation is shown in FIG. As shown in FIG. 6, variable tap coefficient multiplier 1121B includes multipliers 1311 to 1314 for multiplying tap coefficients and a multiplication result sequential output unit 1300B for sequentially outputting the results of multipliers 1311 to 1314. . In the second embodiment, the multiplication result sequential output unit 1300B includes a shift register 1401.
[0091]
The operation of the waveform shaping filter according to the second embodiment will be described with reference to FIG. In FIG. 7, IN represents the input of the variable tap coefficient multiplier 1121B, and OUT represents the output of the variable tap coefficient multiplier 1121B.
[0092]
The shift register 1401 sets the outputs of the multipliers 1311 to 1314 (results obtained by multiplying the tap coefficients) at the timing of the next clock CLK at which the chip timing CT becomes H level, and then the sampling period in synchronization with the clock CLK. The tap calculation multiplication result is shifted and output for each Tsa. As a result, the output signal OUT shown in FIG. 7 is output from the cyst register 1401 of the variable tap coefficient multiplier 1121B.
[0093]
As described above, according to the waveform shaping filter according to the second embodiment, the number of inputs to the adder can be generally reduced to about 1 / Nfos of the oversampling number as compared with the conventional waveform shaping filter. It becomes.
[0094]
[Third Embodiment]
In the third embodiment, a variable tap coefficient multiplier 1121C shown in FIG. 8 is used instead of the variable tap coefficient multiplier 1121A (1122A, 1123A) according to the first embodiment. The variable tap coefficient multiplier 1121C includes a tap coefficient sequential output unit 1600A and a multiplier 1610, as shown in FIG.
[0095]
Tap coefficient sequential output unit 1600A includes a memory MR and a selector 1601 that receives tap coefficients W1 to W4 read from memory MR. The tap coefficient (coefficient signal S0) output from the tap coefficient sequential output unit 1600A and the input signal IN are supplied to the multiplier 1610. A product of the coefficient signal S0 and the input signal IN is generated as the output signal OUT.
[0096]
The operation of the waveform shaping filter according to the third embodiment will be described with reference to FIG. In FIG. 9, IN represents the input of the variable tap coefficient multiplier 1121C, and OUT represents the output of the variable tap coefficient multiplier 1121C.
[0097]
The tap coefficient sequential output unit 1600A includes a memory MR that holds tap coefficients therein. The selector 1601 selectively outputs the tap coefficient Wi read from the memory MR (coefficient signal S0) according to the counter value C (1 to 4) generated by the counter 9003. Specifically, when the counter value C reaches 1, 2, 3, and 4, tap coefficients W1, W2, W3, and W4 are selected, respectively. As a result, as shown in FIG. 9, a product (output signal OUT) of the input signal IN and the tap coefficients W1, W2, W3, and W4 is sequentially generated for each sampling period Tsa in synchronization with the clock CLK. The
[0098]
As described above, according to the waveform shaping filter according to the third embodiment, the number of inputs of the data shift register, the multiplier, and the adder is generally reduced to approximately 1 / Nfos of the oversampling number. It is possible to reduce the circuit scale.
[0099]
Instead of the tap coefficient sequential output unit 1600A, a tap coefficient sequential output unit 1600B configured by a memory (for example, ROM) 1602 as shown in FIG. 10 may be used. In this case, the memory 1602 receives the counter value C at the address terminal, and outputs the tap coefficient in the storage area indicated by the counter value C from the data output terminal.
[0100]
[Fourth Embodiment]
In the fourth embodiment, a variable tap coefficient multiplier 1121D shown in FIG. 11 is used instead of the variable tap coefficient multiplier 1121A (1122A, 1123A) in the first embodiment. Variable tap coefficient multiplier 1121D includes a tap coefficient sequential output unit 1600C and a multiplier 1610.
[0101]
Tap coefficient sequential output unit 1600C includes a memory MR and a shift register 1801 that receives tap coefficients W1 to W4 read from memory MR. The operation of the variable tap coefficient multiplier 1121D is the same as that of the timing chart in the third embodiment.
[0102]
The shift register 1801 sets the tap coefficient at the timing of the next clock CLK when the chip timing CT becomes H level. After that, in synchronization with the clock CLK, the tap coefficients are shifted every sampling period Tsa and output in order (coefficient signal S0).
[0103]
As described above, according to the waveform shaping filter according to the fourth embodiment, the number of inputs of the multiplier and the adder is generally approximately over that of the conventional one while having the same function as the conventional waveform shaping filter. Since the sampling number is reduced to 1 / Nfos, the circuit scale can be reduced.
[0104]
In the waveform shaping filter 203A, the above-described variable tap coefficient multipliers 1121A to 1121D may be arranged in combination.
[0105]
[Fifth Embodiment]
A waveform shaping filter 203B according to the fifth embodiment will be described with reference to FIG. As shown in FIG. 12, the waveform shaping file 203B includes a shift register unit 1910, an inverted data shift register unit 1980, a variable tap coefficient multiplication unit 1920, a sign inverter 1970, and an adder 1930. In the figure, each of shift register units 1910 and 1980 includes three registers D, and variable tap coefficient multiplier 1920 includes variable tap coefficient multipliers 1921A, 1922A, and 1923A, respectively.
[0106]
Compared with the configuration according to the first embodiment, in the fifth embodiment, a sign inverter 1970 and an inverted data shift register unit 1980 are newly provided, and the variable tap coefficient multiplier unit 1920 includes a shift register. An input from the unit 1910 and an inverting input from the shift register unit 1980 are newly supplied.
[0107]
In the figure, IN represents an input from the shift register unit 1910 to the variable tap coefficient multiplier 1921A, and RIN represents an inverting input from the shift register unit 1980 to the variable tap coefficient multiplier 1921A.
[0108]
The sign inverter 1970 multiplies the input data Data by “−1”. The variable tap coefficient multipliers 1921A to 1923A perform the same operation as the variable tap coefficient multiplier according to the first embodiment, but can be realized with a smaller circuit scale because an inverting input is added.
[0109]
As an example, FIG. 13 shows an internal configuration of the variable tap coefficient multiplier 1921A, and FIG. 14 shows a timing chart. As shown in FIG. 13, the variable tap coefficient multiplier 1921A includes tap coefficient multipliers 2121 to 2124 corresponding to the tap coefficients W1 to W4 and a multiplication result sequential output unit 2110. The multiplication result sequential output unit 2110 includes a selector 2111.
[0110]
Tap coefficient multipliers 2123 and 2124 receive input IN from shift register unit 1910, and tap coefficient multipliers 2121, 2122 and 2124 receive inverted input RIN from shift register unit 1980.
[0111]
The selector 2111 selectively outputs (OUT) one of the outputs of the tap coefficient multipliers 2121 to 2124 according to the counter value C.
[0112]
Here, the tap coefficient is [W1, W2, W3, W4] = [− 2, −5, 4, 15]. The tap coefficient multiplier 2121 multiplies the input IN by a negative tap coefficient W1 and outputs the result. However, in practice, the following processing is executed without multiplying the input IN by the tap coefficient W1.
[0113]
That is, since the tap coefficient W1 is a negative value, the inverting input RIN (a value obtained by multiplying the input by “−1”) is input to the tap coefficient multiplier 2121. Then, “2” which is an absolute value of the tap coefficient W1 is multiplied. Thereby, multiplication of “−2” is realized. When “−2” and “2” are expressed in 12-bit binary numbers, they are “1111 1111 1110” and “10”, respectively, and “2” has fewer bits than “−2”. Therefore, the circuit scale of the tap coefficient multiplier is reduced by a smaller number of bits compared to a circuit that multiplies the input IN by a negative tap coefficient as it is.
[0114]
The tap coefficient multiplier 2122 also gives an inverting input RIN because the tap coefficient W2 is a negative value, and multiplies the absolute value of the tap coefficient W2 by the inverting input RIN. On the other hand, tap coefficient multiplier 2123 multiplies input IN and tap coefficient W3 because tap coefficient W3 is a positive value.
[0115]
The tap coefficient multiplier 2124 has a tap coefficient W4 = 15 = 16-1. Therefore, multiplication of “15” is realized by adding the input IN multiplied by “16” and the inverting input RIN. Since multiplication of “16” only shifts the bits and can be realized only by wiring, only one adder is required. Therefore, the circuit scale of the tap coefficient multiplier 2124 can be reduced as compared with a tap coefficient multiplier that multiplies the input by the tap coefficient “15” as it is.
[0116]
Multiplication result sequential output unit 2110 performs the same operation as multiplication result sequential output unit 1300A described above.
[0117]
Thus, according to the waveform shaping digital filter circuit in the fifth embodiment, the same function as that of the conventional waveform shaping digital filter circuit can be obtained, and the circuit scale can be reduced.
[0118]
[Sixth Embodiment]
Similar to the waveform shaping filter 203B according to the fifth embodiment, the waveform shaping filter according to the sixth embodiment includes a shift register unit 1910, an inverted data shift register unit 1980, an adder 1930, and a sign inverter 1970. Instead of the variable tap coefficient multiplier 1921A (1921A, 1923A), a variable tap coefficient multiplier 1921B shown in FIG. 15 is provided.
[0119]
A variable tap coefficient multiplier 1921B according to the sixth embodiment includes a tap coefficient sequential output unit 2210A, a code selector 2220, and a multiplier 2240.
[0120]
The tap coefficient sequential output unit 2210A sequentially outputs the absolute value of the tap coefficient. Multiplier 2240 multiplies coefficient signal S1 output from tap coefficient sequential output unit 2210A and code selected signal S2 output from code selector 2220.
[0121]
The sign multiplication of the tap coefficient is performed by switching the input IN and the inverted input RIN in the sign selector 2220.
[0122]
Tap coefficient sequential output unit 2210A includes a memory MR that stores absolute values W1a to W4a of tap coefficients W1 to W4, and a selector 2211 that selectively outputs one of values W1a to W4a read from memory MR. Including.
[0123]
The selector 2211 selectively outputs the corresponding tap coefficient Wia according to the counter value C (C = 1 to 4) output from the counter 9003.
[0124]
The tap coefficients W1a to W4a are absolute values of the tap coefficients W1 to W4. If {W1, W2, W3, W4} = {− 2, −5, 4, 15}, {W1a, W2a, W3a, W4a } = {2, 5, 4, 15}.
[0125]
The code selector 2220 includes a selector 2221. The selector 2221 selects and outputs the signal of the corresponding input terminal Wis according to the counter value C (C = 1 to 4) generated by the counter 9003. The input terminals W1s to W4s correspond to the tap coefficients W1 to W4, and receive the input IN when the corresponding tap coefficient is positive, and receive the inverted input RIN when the tap coefficient is negative. Here, {W1, W2, W3, W4} = {− 2, −5,4,15} = {negative value, negative value, positive value, positive value}. W2s receives the inverted input RIN, and the input terminals W3s and W4s receive the input IN.
[0126]
The operation of the waveform shaping filter according to the sixth embodiment will be described with reference to FIG. In the figure, IN is an input from the shift register unit 1910 to the variable tap coefficient multiplier 1921B, RIN is an inverted input from the inverted data shift register unit 1980 to the variable tap coefficient multiplier 1921B, and OUT is a variable tap. The outputs of the coefficient multipliers 1921B are respectively shown.
[0127]
As shown in FIG. 16, when the chip timing CT becomes H level, the product of the input IN or the inverting input RIN and the tap coefficient is calculated sequentially from the timing of the next clock CLK and output (OUT).
[0128]
By configuring in this way, the multiplier 2240 only has to be configured to multiply a signed integer and a positive integer. Therefore, the circuit scale is larger than a multiplier that multiplies a signed integer and a signed integer. Is reduced.
[0129]
As shown in FIG. 17, instead of the tap coefficient sequential output unit 2210A, a tap coefficient sequential output unit 2210B including a shift register 2212 that loads and sequentially shifts tap coefficients Wia may be used.
[0130]
[Seventh Embodiment]
The variable tap coefficient multipliers according to the fifth and sixth embodiments described above are supplied with the input IN from the shift register unit 1910 and the inverted input RIN from the inverted data shift register unit 1980. . On the other hand, if all the tap coefficients have the same sign, only one of the input IN and the inverting input RIN may be supplied to the variable tap coefficient multiplier.
[0131]
For example, if {W1, W2, W3, W4} are all positive, signal input from the inverted data shift register unit 1980 to the variable tap coefficient multiplier is unnecessary.
[0132]
In such a case, the waveform shaping filter 203C includes a shift register unit 1910, an inverted data shift register unit 1980, and a variable tap coefficient multiplication unit 2420, as shown in FIG. The variable tap coefficient multiplication unit 2420 includes a variable tap coefficient multiplier 2421 that receives an input from the shift register unit 1910, a variable tap coefficient multiplier 2422 that receives data from the shift register unit 1910 and the inverted data shift register unit 1980, and an inversion. And a variable tap coefficient multiplier 2423 that receives a signal from the data shift register unit 1980.
[0133]
As described above, the variable tap coefficient multiplier 2421 does not need an input from the inverted data shift register unit 1980, and the variable tap coefficient multiplier 2423 does not need an input from the shift register unit 1910. Register is omitted, and as a result, the circuit scale is reduced.
[0134]
In this case, each of the shift register unit 1910 and the inverted data shift register unit 1980 includes two registers D. Further, the sign inverter is also arranged at a location different from the waveform shaping filter 203B shown in FIG.
[0135]
[Eighth Embodiment]
In the first to seventh embodiments described above, the oversampling number Nfos is 4 (integer). Therefore, in the eighth embodiment, it is assumed that Fcp = 3 MHz and Fsa = 6.9 MHz. At this time, the oversampling number Nfos = 2.3.
[0136]
The waveform shaping filter according to the eighth embodiment is mounted on the wireless communication system 9500 shown in FIG. The wireless communication system 9500 includes a clock generator 9001 and an NCO (Numerical Controlled Oscillator) circuit 9005 in addition to the system configuration shown in FIG.
[0137]
The clock CLK is 6.9 MHz. A 3 MHz chip timing CT is generated from the clock CLK using the NCO circuit 9005. The NCO circuit 9005 includes an increment value register 9010 and a counter 9011 that can represent 10 bits, that is, a value of 0 to 1023.
[0138]
The counter 9011 includes an adder 9012 and a D flip-flop 9013. The value of the increment value register 9010 is added to the adder 9012 for each clock CLK. The value of the increment value register 9010 is (2) when the bit number B (= 10) of the counter 9011, the clock frequency Fclk (= 6.9 MHz), and the output frequency F0 (= 3 MHz). ^B XF0) / Fclk = 445.
[0139]
When the added result is “1024” or more, an overflow occurs. If an overflow occurs, all but the lower 10 bits are ignored. That is, when “5” is added to “1023”, the counter 9011 returns to “4”. The adder 9012 generates a chip timing CT when an overflow occurs.
[0140]
The D flip-flop 9013 takes the output of the adder 9012 in synchronization with the clock CLK and outputs the NCO counter value NC.
[0141]
The waveform shaping filter 2000 in the figure corresponds to the waveform shaping filter according to the eighth to tenth embodiments.
[0142]
The waveform shaping filter according to the eighth embodiment has the configuration shown in FIG. 2 as in the third embodiment. However, the waveform shaping filter according to the eighth embodiment includes a variable tap coefficient multiplier 1121E shown in FIG. 20 instead of the variable tap coefficient multiplier 1121C according to the third embodiment. Variable tap coefficient multiplier 1121E includes a tap coefficient selector 2500 and a multiplier 1610.
[0143]
In the third embodiment, since the oversampling number Nfos = 4, four types of tap coefficients are provided. On the other hand, in the eighth embodiment, tap coefficients W0 to W63 (64 types here) are provided.
[0144]
Tap coefficient selector 2500 includes a selector 2501 that selects tap coefficients W0 to W63 received from an internal memory (not shown). The selector 2501 receives an integer value j obtained by dividing the NCO counter value NC by 16 (a value corresponding to the upper 6 bits of 10 bits of the NCO counter value NC), selects a corresponding tap coefficient Wj, and selects a coefficient signal. Output as S3.
[0145]
The tap coefficient (coefficient signal S3) generated by the tap coefficient selector 2500 and the input signal IN are supplied to the multiplier 1610. A product of the coefficient signal S3 and the input signal IN is generated as the output signal OUT.
[0146]
The operation of the waveform shaping filter according to the eighth embodiment will be described with reference to the timing chart of FIG. In the figure, IN represents an input to the variable tap coefficient multiplier 1121E, and OUT represents a signal output from the variable tap coefficient multiplier 1121E.
[0147]
The value 445 of the increment value register 9010 is added to the NCO counter value NC every time the clock CLK is input. As a result of the addition, if it is “1024” or more, an overflow occurs, and other than the lower 10 bits are ignored. At the same time, chip timing CT is output.
[0148]
The shift register unit 1110 latches and shifts chip data as input data Data using the chip timing CT as an enable signal. The chip data shifted in this way is input to the variable tap coefficient multiplier.
[0149]
The tap coefficient selector 2500 selects the corresponding tap coefficient Wj (j = 0 to 63) and outputs it as the coefficient signal S3 when the high-order 6-bit value j of the NCO counter value NC is 0 to 63.
[0150]
For example, when the NCO counter value NC is “925”, the above 6 bits are <925/16> = 57 (where “<number>” indicates truncation), and therefore the tap coefficient W57 is output. The output signal OUT is generated by multiplying the input signal IN and the coefficient signal S3.
[0151]
Variable tap coefficient multipliers 1122E and 1123E instead of variable tap coefficient multipliers 1122C and 1123C have the same configuration as variable tap coefficient multiplier 1121E and perform the same operation. However, instead of {W0, W1,..., W63}, {W64, W65,... W127}, {W128, W129,..., W191} are used as tap coefficients, respectively, and the upper 6 bits of the NCO counter value NC are used. When the value is 0 to 63, “W64 to W127” and “W128 to W191” are selected, respectively.
[0152]
With this configuration, even when the oversampling number Nfos is not an integer, filtering can be performed with a small circuit scale.
[0153]
[Ninth Embodiment]
Also in the ninth embodiment, as in the eighth embodiment, it is assumed that Fcp = 3 MHz and Fsa = 6.9 MHz. Therefore, the oversampling number Nfos = 2.3. Similarly, the NCO circuit 9005 is used to generate a 3 MHz chip timing CT from the 6.9 MHz clock CLK. The NCO circuit 9005 uses a counter 9011 that can represent 10 bits, that is, a value from “0” to “1023”.
[0154]
The waveform shaping filter according to the ninth embodiment includes a variable tap coefficient multiplier 1121F shown in FIG. 22 instead of the variable tap coefficient multiplier 1121C according to the third embodiment. Variable tap coefficient multiplier 1121F includes a tap coefficient output unit 2700A and a multiplier 1610.
[0155]
The tap coefficient output unit 2700A can select a sufficiently large number of consecutive tap coefficient sets. That is, a set of tap coefficients consisting of {W (j), W (j + 1)} can be selected for j = 0, 1,. Such a selection operation is realized by the selectors 2721 and 2722 of the tap coefficient output unit 2700A. Further, tap coefficient output unit 2700A includes an interpolator 2730 that interpolates between two selected sets of tap coefficients.
[0156]
The tap coefficient selection process and the interpolation process are performed according to the following procedure. First, the NCO counter value NC is divided by 16. Let the integer part of this result be j and the decimal part be k. j takes the values 0, 1,. According to this value, a set of tap coefficients {W (j), W (j + 1)} is selected.
[0157]
Assuming that the output of the interpolator 2730 is Vcoe, the interpolator 2730 performs an operation (interpolation) expressed by Expression (6).
[0158]
Vcoe = W (j) × (1−k) + W (j + 1) × k (6)
In the eighth embodiment, the tap coefficient is selected using the upper 6 bits (j) of the 10 bits of the NCO counter value NC, but in the ninth embodiment, the lower 4 bits (k) are further reduced. Is used for interpolation. If the accuracy is sufficient, for example, interpolation may be performed using only the upper 3 bits of the lower 4 bits. The output (coefficient signal) Vcoe of the interpolator 2730 thus obtained is multiplied by the input signal IN by the multiplier 1610. An output signal OUT is output from the multiplier 1610.
[0159]
Variable tap coefficient multipliers 1122F and 1123F instead of variable tap coefficient multipliers 1122C and 1123C perform the same configuration and operation as variable tap coefficient multiplier 1121F. However, as tap coefficients, instead of 64 tap coefficient sets {W (j), W (j + 1)} consisting of j = 0, 1,... 63, 64 tap coefficient sets {W ( j + 64), W (j + 65)}, {W (j + 128), W (j + 129)}, and when the value of the upper 6 bits of the NOC counter value NC is j, {W (j + 64), W (j + 65)} , {W (j + 128), W {j + 129)} are selected.
[0160]
With this configuration, it is possible to perform filling with a small circuit scale even when the oversampling number Nfos is not an integer, as in the eighth embodiment. Further, since the tap coefficients are interpolated, the circuit scale for realizing the same performance can be smaller than that in the eighth embodiment.
[0161]
[Tenth embodiment]
In the tenth embodiment, a variable tap coefficient multiplier 1121G is used instead of the variable tap coefficient multiplier 1121F. As shown in FIG. 23, variable tap coefficient multiplier 1121G includes tap coefficient output unit 2700B instead of tap coefficient output unit 2700A. Tap coefficient output unit 2700B includes a selector 2820, a multiplier 2832, and an adder 2833.
[0162]
As in the ninth embodiment, the integer part of the value obtained by dividing the NCO counter value NC by 16 is j, and the decimal part is k. In the tenth embodiment, the selector 2820 selects a tap coefficient set {W (j), W (j) d}. Here, W (j) d is a value that satisfies Expression (7), and is calculated in advance and stored therein.
[0163]
W (j) d = W (j + 1) -W (j) (7)
When the output value of the tap coefficient output unit 2700B is Vcoe, the multiplier 2832 and the adder 2833 perform an operation (interpolation) expressed by Expression (8).
[0164]
Vcoe = W (j) + W (j) d × k (8)
Using equations (7) and (8), Vcoe = W (j) × (1−k) + W (j + 1) × k, which matches the interpolation equation (6) described in the ninth embodiment. . Therefore, tap coefficient output unit 2700B outputs the same value as tap coefficient output unit 2700A.
[0165]
When the number of tap coefficients is sufficiently large, the difference W (j) d between adjacent tap coefficient values is small, and the number of bits for expressing the difference W (j) d between tap coefficients is also small. Therefore, rather than holding and selecting a set of tap coefficients {W (j), W (j + 1)}, hold {W (j), W (j) d} as shown in the tenth embodiment. However, the circuit scale becomes smaller when the selection is made.
[0166]
Further, as is apparent from the interpolation formula, in the ninth embodiment, two multipliers, one adder and one subtractor are required, whereas in the tenth embodiment, a multiplier is used. Only one adder and one adder are required. As described above, when the configuration according to the tenth embodiment is used, the circuit scale for realizing the same performance as the ninth embodiment can be reduced.
[0167]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a waveform shaping digital filter circuit having a large oversampling number Nfos with a smaller circuit scale. The effect of reducing the circuit scale in comparison with the conventional filter increases as the filter oversampling number Nfos increases.
[0168]
Furthermore, the upsampler inserted in the previous stage of the waveform shaping filter is not necessary, and the circuit scale is reduced. Further, as a secondary effect, it is possible to reduce the up-sampler and the low-pass filter inserted in the subsequent stage of the waveform shaping filter, and a further reduction in circuit scale can be realized.
[0169]
The waveform shaping digital filter of the present invention eliminates the need for the upsampler 102 inserted before the waveform shaping filter, thereby reducing the circuit scale.
[0170]
Furthermore, the waveform shaping digital filter of the present invention reduces the number of data shift registers 410 and the number of inputs of the adder 430 to about 1 / Nfos of the oversampling number Nfos, thereby reducing the circuit scale. In addition, the number of multipliers in the multiplication unit 420 is approximately 1 / Nfos of the oversampling number Nfos, and the circuit scale can be reduced.
[0171]
Further, by using the inverted input data obtained by inverting the input data by the waveform shaping digital filter according to the present invention, the number of the data shift registers 410 is approximately two times Nfos with respect to the oversampling number Nfos. Can be reduced to about 1 / Nfos, and the circuit scale can be reduced.
[0172]
Furthermore, in the waveform shaping digital filter according to the present invention, the circuit scale can be further reduced as compared with the tap coefficient multipliers 1311 to 1314 by using the tap coefficient multipliers 2121 to 2124.
[0173]
Furthermore, in the waveform shaping digital filter of the present invention, the multiplier 2240 can further reduce the circuit scale than the multiplier 1610.
[0174]
Further, the waveform shaping digital filter of the present invention realizes a filter with a small circuit scale without adding a special signal processing circuit such as a sampling rate non-integer multiple converter even when the oversampling number Nfos is not an integer. be able to.
[0175]
Furthermore, in the waveform shaping digital filter of the present invention, since the tap coefficients are interpolated, the circuit scale for realizing the same performance becomes smaller.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a system configuration using a waveform shaping filter according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a waveform shaping filter according to the first embodiment.
3 is a block diagram showing a configuration of a wireless communication system 9000 including a waveform shaping filter 1000. FIG.
FIG. 4 is a timing chart for explaining the operation of the waveform shaping filter according to the first embodiment;
FIG. 5 is a block diagram showing an example of an internal configuration of a variable tap coefficient multiplier 1121A.
FIG. 6 is a block diagram showing an example of an internal configuration of a variable tap coefficient multiplier 1121B according to the second embodiment.
FIG. 7 is a timing chart for explaining the operation of the waveform shaping filter according to the second embodiment.
FIG. 8 is a block diagram illustrating an example of an internal configuration of a variable tap coefficient multiplier 1121C according to a third embodiment.
FIG. 9 is a timing chart for explaining the operation of the waveform shaping filter according to the third embodiment;
FIG. 10 is a diagram showing a tap coefficient sequential output unit 1600B according to a third embodiment.
FIG. 11 is a block diagram showing an example of an internal configuration of a variable tap coefficient multiplier 1121D according to the fourth embodiment.
FIG. 12 is a block diagram showing a configuration of a waveform shaping filter according to a fifth embodiment.
FIG. 13 is a block diagram illustrating an example of an internal configuration of a variable tap coefficient multiplier 1921A according to a fifth embodiment.
FIG. 14 is a timing chart for explaining the operation of the waveform shaping filter according to the fifth embodiment;
FIG. 15 is a block diagram illustrating an example of an internal configuration of a variable tap coefficient multiplier 1921B according to a sixth embodiment.
FIG. 16 is a timing chart for explaining the operation of the waveform shaping filter according to the sixth embodiment;
FIG. 17 is a block diagram showing an example of another configuration of the tap coefficient sequential output device according to the sixth embodiment.
FIG. 18 is a block diagram showing a configuration of a waveform shaping filter 203C according to a seventh embodiment.
FIG. 19 is a block diagram showing a configuration of a wireless communication system 9500 including a waveform shaping filter 2000.
FIG. 20 is a block diagram showing an example of an internal configuration of a variable tap coefficient multiplier 1121E according to the eighth embodiment.
FIG. 21 is a timing chart for explaining the operation of the waveform shaping filter according to the eighth embodiment;
FIG. 22 is a block diagram showing an example of an internal configuration of a variable tap coefficient multiplier 1121F according to the ninth embodiment.
FIG. 23 is a block diagram illustrating an example of an internal configuration of a variable tap coefficient multiplier 1121G according to the tenth embodiment.
FIG. 24 is a block diagram showing a system configuration using a conventional waveform shaping filter.
FIG. 25 is a timing chart showing a relationship between an input signal to the upsampler and an output signal.
26 is a block diagram showing a configuration of a conventional waveform shaping filter 103. FIG.
27 is a diagram illustrating an example of a spectrum of an output signal of a conventional waveform shaping filter 103. FIG.
28 is a diagram illustrating an example of an impulse response of a conventional waveform shaping filter 103. FIG.
FIG. 29 is a diagram illustrating an example of a spectrum of an output signal of the upsampler 104. FIG.
30 is a diagram illustrating an example of a spectrum of an output signal of the low-pass filter 105. FIG.
FIG. 31 is a diagram illustrating an example of a spectrum of an output signal of the orthogonal transformer 107;
32 is a conceptual diagram showing in detail the contents of the output of the shift register unit 410 and the output of the multiplication unit 420. FIG.
33 is a diagram showing another example of the spectrum of the output signal of the conventional waveform shaping filter 103. FIG.
34 is a diagram showing another example of the spectrum of the output signal of the upsampler 104. FIG.
35 is a diagram showing another example of the spectrum of the output signal of the low-pass filter 105. FIG.
36 is a diagram showing another example of the spectrum of the output signal of the orthogonal transformer 107. FIG.
FIG. 37 is a diagram showing another example of the spectrum of the output signal of the conventional waveform shaping filter 103.
38 is a diagram showing another example of the spectrum of the output signal of the upsampler 104. FIG.
39 is a diagram showing another example of the spectrum of the output signal of the low-pass filter 105. FIG.
40 is a diagram showing another example of the spectrum of the output signal of the orthogonal transformer 107. FIG.
[Explanation of symbols]
203, 203A to 203C, 1000, 2000 Waveform shaping filter, 101 baseband signal generator, 106 intermediate frequency generator, 107 orthogonal transformer, 108 analog converter, 109 bandpass filter, 1110 shift register unit, 1120, 1920, 2420 Variable Tap Coefficient Multiplier, 1121A to 1121G, 1921A, 1922A, 1923A, 1921B, 2421 to 2423 Variable Tap Coefficient Multiplier, 1130, 1930, 2833, 9012 Adder, 1300A, 1300B, 2110 Multiplication result sequential output device, 1301 1601, 2111, 221, 251, 2721, 820 selector, 1401, 1801, 1910, 1980 cyst register, 1600A to 1600C, 2210A, 2210B Sequential output unit, 1610, 2240, 2832 multiplier, 1970 sign inverter, 2121 to 2124 tap coefficient multiplier, 2220 code selector, 2500 tap coefficient selector, 2700A, 2700B tap coefficient output unit, 2730 interpolator, 9001 clock Generator, 9002 Chip timing generator, 9003, 9011 counter, 9005 NCO circuit, 9010 Increment value register, 9013 flip-flop, 9000, 9500 Wireless communication system.

Claims (7)

A waveform shaping digital filter circuit for shaping a signal waveform,
A register to shift input data;
A sign inverter that multiplies the input data by "-1";
An inverted data register for shifting the output of the sign inverter;
Of the output data from the output data and the inversion data register from the register, by multiplying the absolute value of the output data and the tap coefficients corresponding to the code of the tap coefficients, and output data from the register A plurality of variable tap coefficient multipliers that sequentially output products of tap coefficients of the same number as the number of oversamplings;
A waveform shaping digital filter circuit comprising: an adder that adds products simultaneously received from the plurality of variable tap coefficient multipliers. The variable tap coefficient multiplier is
Of the output data from the output data and the inversion data register from the register, a plurality of tap coefficient multipliers for multiplying the absolute value of the output data and the tap coefficients corresponding to the code of the tap coefficients,
The waveform shaping digital filter circuit according to claim 1, further comprising: a multiplication result sequential output device that sequentially outputs output data from the plurality of tap coefficient multipliers. The multiplication result sequential output device comprises:
The waveform shaping digital filter circuit according to claim 2, further comprising: a selector that sequentially selects and outputs output data from the plurality of tap coefficient multipliers. The multiplication result sequential output device comprises:
The waveform shaping digital filter circuit according to claim 2, further comprising: a shift register that loads output data from the plurality of tap coefficient multipliers and outputs the data while sequentially shifting the output data. The variable tap coefficient multiplier is
A tap coefficient sequential output device that sequentially outputs the absolute value of the tap coefficient;
A sign selector for selecting and outputting the output data from the register when the sign of the tap coefficient is positive, and the output data of the register for inverted data when the sign of the tap coefficient is negative;
The waveform shaping digital filter circuit according to claim 1, further comprising a multiplier that outputs a product of an output from the tap coefficient sequential output device and an output from the code selector. The tap coefficient sequential output device,
The waveform shaping digital filter circuit according to claim 5, further comprising: a selector that sequentially selects and outputs the absolute value of the tap coefficient. The tap coefficient sequential output device,
6. The waveform shaping digital filter circuit according to claim 5, further comprising a shift register that loads the absolute value of the tap coefficient and outputs the tap coefficient while sequentially shifting it.

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