JPH08265218A - Spreading code detection circuit, inverse spread demodulation circuit and receiver - Google Patents

Abstract

PURPOSE: To demonstrate sufficient performance even when a signal-to-noise ratio is low by performing the inverse rotation of a phase to quadrature phase components so as to cancel phase rotation generated at the time of minimum frequency shift keying modulating spreading codes on a transmission side. CONSTITUTION: An inverse spreading circuit 34 for performing the inverse rotation of the phase to the quadrature phase components so as to cancel the phase rotation generated at the time of minimum frequency shift keying modulating the spreading codes on the transmission side and detecting a correlation value for the spreading codes is provided. The inverse spreading circuit 34 performs the inverse rotation to the quadrature phase components I and Q outputted from an orthogonal detection circuit 21 so as to cancel the phase rotation generated at the time of MSK modulating PN codes on the transmission side and detects the correlation value of the PN codes. Then, the inverse spreading circuit 34 outputs the correlation value as a correlation result S22. A judgement device 35 judges that the PN codes are detected when the correlation result S22 exceeds a prescribed threshold value, outputs a judged result S23 to a control circuit 36 and reports that the PN codes are detected.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 22 and 23) Problem to be Solved by the Invention Means for Solving the Problem Action Example (1) First Example (1-1) Principle of the Invention (1) -2) Overall configuration of receiver (Fig. 1) (1-3) Configuration of PN detection unit (Fig. 2) (1-3-1) Configuration of despreading circuit (Figs. 3 to 8) (1-4) Configuration of despreading / demodulation unit (FIGS. 9 and 10) (1-4-1) Configuration of despreading circuit (FIG. 11) (1-5) Operation and effect of embodiment (2) Second embodiment (2) -1) Configuration of PN detection section (Fig. 12) (2-1-1) Configuration of despreading circuit (Figs. 13 and 14) (2-2) Operation and effect of embodiment (3) Third embodiment (3) 3-1) Configuration of Despreading / Demodulation Unit (FIG. 15) (3-1-1) Configuration of Despreading Circuit (FIGS. 16 and 17) (3-2) Operation and Effect of Embodiment (4) Other Example (4-1) Part 1 (FIG. 18) (4-2) Part 2 (FIG. 19) (4-3) Part 3 (FIG. 20) (4-4) Part 4 (FIG. 21) (4-5 ) Part 5 Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread code detection circuit, a despread demodulation circuit, and a receiver, which are MSK modulation (Mini
mum Shift Keying: It is suitable for application to, for example, a digital cordless telephone device that communicates by a communication system that combines a so-called narrow band frequency shift keying) system and a spread spectrum system.

[0003]

2. Description of the Related Art Conventionally, spread spectrum systems have been mainly used in the field of satellite communication. However, recently, it is also beginning to be used in digital cellular telephone devices that are being put to practical use in the United States, digital cordless telephone devices using the ISM (Industrial Scientific Medical) band, and the like.

On the other hand, in the frequency shift keying system, a highly efficient nonlinear amplifier can be used for the transmitter, and a simple limiter can be used for the receiver instead of the AGC circuit (so-called automatic gain adjustment circuit). It has advantages such as realization of an inexpensive demodulator by frequency detection and the like, and is widely used in cordless telephone devices.

22 and 23, a digital cordless telephone device in which the MSK modulation system, which is a kind of frequency shift keying system, and the spread spectrum system are combined will be described. As shown in FIG. 22, in the transmitter 1 of this digital cordless telephone device, the information data S1 is input to the multiplier 2.
The multiplier 2 generates P as a spreading code generated by the PN generator 3.
The N code (Pseudo Noise code) S2 is multiplied by the input information data S1, and the spread data S3 obtained as a result is M
Output to the SK modulator 4. The MSK modulator 4 performs MSK modulation on a predetermined carrier using the input spread data S3, and outputs the resulting modulated signal to the frequency converter 5. The frequency conversion unit 5 converts the modulated signal into a high frequency signal in a predetermined band and outputs it as a transmission signal to the RF amplification unit 6. R
The F amplifier 6 amplifies the input transmission signal. This RF
The transmission signal amplified by the amplification unit 6 is transmitted via the antenna 7.

On the other hand, as shown in FIG. 23, in the receiver 8 of the digital cordless telephone apparatus, the transmission signal transmitted from the transmitter 1 is received by the antenna 9, and the reception signal obtained as a result is supplied to the RF amplification section 10. It is designed to be entered into. The RF amplification unit 10 amplifies the input reception signal and outputs it to the frequency conversion unit 11. The frequency converter 11 converts the received signal into a low-frequency signal by performing a process reverse to that of the frequency converter 5 on the transmission side, and outputs the low-frequency signal to the demodulator 12. The demodulator 12 demodulates the MSK-modulated reception signal to obtain spread data S4 corresponding to the spread data S3 on the transmission side, and outputs the spread data S4 to the despreading unit 13 and the PN detection unit 14.

The PN detector 14 detects the PN from the spread data S4.
The code timing is detected, and the detection result is output to the PN generator 15 as an initialization signal S5. PN generator 15
Are initialized by the initialization signal S5 and generate the same PN code S6 synchronized with the PN code S2 on the transmitting side. The despreading unit 13 despreads the spread data S4 using the PN code S6 generated by the PN generator 15 to obtain information data S7. In this way, in this digital cordless telephone device, the transmitter 1 and the receiver 8 communicate with each other by a communication system combining the MSK modulation system and the spread spectrum system.

[0008]

In the receiver 8 described above, the demodulator 12 and the despreading unit 13 are separated from each other, so that the existing inexpensive frequency detection circuit is used as the demodulator 12. Therefore, the cost can be reduced as a whole, and the configuration can be simplified. However, when the demodulator 12 and the despreading unit 13 are separated, the performance remarkably deteriorates when the signal-to-noise ratio C / N is low (specifically, the error rate for the signal-to-noise ratio C / N is very large. A problem occurs.

The present invention has been made in consideration of the above points, and provides a spreading code detecting circuit, a despreading demodulating circuit and a receiving device which can exhibit sufficient performance even when the signal-to-noise ratio C / N is low. It is a proposal.

[0010]

In order to solve such a problem, according to the present invention, a spread code is detected from a transmission signal transmitted by a communication system in which a narrow band frequency shift keying system and a spread spectrum system are combined. In the spreading code detection circuit, the phase is inversely rotated for the quadrature phase component so as to cancel the phase rotation that occurs when the spreading code is narrow-band frequency shift keyed on the transmission side, and the correlation value for the spreading code is detected. The despreading circuit is provided, and the detection of the spreading code is determined by comparing the correlation value output from the despreading circuit with a predetermined threshold value.

Further, according to the present invention, in the spreading code detecting circuit for detecting the spreading code from the transmission signal transmitted by the communication system in which the narrow band frequency shift keying system and the spread spectrum system are combined, the spreading code is spread on the transmitting side. A despreading circuit is provided to detect the correlation value of the spreading code by performing the reverse rotation of the phase in parallel to the quadrature phase component so as to cancel the phase rotation that occurs when the code is narrow-band frequency shift keyed. The detection of the spread code is determined by comparing the correlation value output from the despreading circuit with a predetermined threshold value.

Further, according to the present invention, the despreading demodulation circuit for demodulating the information data from the transmission signal transmitted by the communication system in which the narrow band frequency shift keying system and the spread spectrum system are combined has three stages. And first and second shift registers for delaying each signal component of the quadrature phase component and outputting first to third quadrature phase components, and a narrowband frequency shift modulation of the spreading code on the transmission side. To reverse the phase rotation that occurs when the first to the third quadrature phase components are canceled,
First to third despreading circuits for detecting correlation values for two types of spreading codes corresponding to information data are provided, and second
Information data is determined by comparing the magnitudes of the correlation values of the two types of spreading codes output from the first despreading circuit, and the correlation of the two types of spreading codes output from the first despreading circuit. The difference between the value and the correlation value for the two kinds of spreading codes output from the third despreading circuit is obtained, and the processing timings of the first and second shift registers and the first to third despreading circuits are adjusted. I decided to do it.

Further, according to the present invention, in the despreading demodulation circuit for demodulating information data from the transmission signal transmitted by the communication system in which the narrow band frequency shift keying system and the spread spectrum system are combined, the despreading demodulation circuit spreads on the transmission side. Despreading, in which the phase is inversely rotated for the quadrature phase component so as to cancel the phase rotation that occurs when the code is subjected to narrowband frequency shift keying, and the correlation value for two types of spreading codes corresponding to information data is detected. Circuit, and a first delaying the correlation value for each of the two types of spreading codes output from the despreading circuit.
And a second register, and third and fourth registers for respectively delaying the correlation values for the two types of spread codes output from the first and second registers, respectively. Information data is determined by comparing the magnitudes of the correlation values of the two types of spreading codes output, and the correlation values of the two types of spreading codes output from the despreading circuit and the third and fourth The processing timings of the first to fourth registers and the despreading circuit are adjusted by obtaining the difference between the correlation values of the two types of spreading codes output from the register.

[0014]

[Function] The quadrature phase component is inversely rotated so as to cancel the phase rotation that occurs when the spreading code is narrow-band frequency shift keyed at the transmitting side, and the correlation value for the spreading code is detected. Therefore, the signal-to-noise ratio C / N
Even when is low, the signal components can be strengthened by adding the quadrature phase components that cancel the phase rotation.

The inverse rotation of the phase is performed in parallel on the quadrature phase component so as to cancel the phase rotation that occurs when the spreading code is narrow-band frequency shift keyed on the transmitting side, and the correlation value for the spreading code is detected. By doing so, even when the signal-to-noise ratio C / N is low, the quadrature phase components that cancel the phase rotation can be added to strengthen the signal component, and the phase rotation can be performed in parallel to spread. The code can be detected quickly.

The difference between the correlation values of the two kinds of spreading codes output from the first despreading circuit and the correlation values of the two kinds of spreading codes output from the third despreading circuit is calculated to obtain the first value. By adjusting the processing timings of the second shift register and the first to third despreading circuits, the information data can be demodulated at the optimum timing.

The difference between the correlation value for the two types of spreading codes output from the despreading circuit and the correlation value for the two types of spreading codes output from the third and fourth registers is calculated to obtain the first to the first values. By adjusting the processing timings of the register 4 and the despreading circuit, the information data can be demodulated at the optimum timing.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment (1-1) Principle of the Present Invention Here, the principle of the present invention, that is, how to despread and demodulate a signal spectrum-spread using the MSK modulation method in a receiver This will be described using each mathematical expression. First, the carrier frequency is f _C , the PN code used as a spreading code is pn (i), the initial phase is φ, and the information data is d.
Then, if the MSK modulation method and the spread spectrum method are combined, the transmission signal for one information data output from the transmitter is

[Equation 1] Given in.

The receiver first performs quadrature detection on the reception signal obtained by receiving this transmission signal. That is, for the received signal represented by the above equation (1), the following equation

[Equation 2] The signal component x (i) represented by is multiplied. As a result,

(Equation 3) A quadrature detection signal b (i) represented by

Next, the receiver despreads the quadrature detection signal b (i). That is, the following equation is added to the quadrature detection signal b (i) represented by the above equation (3).

[Equation 4] The signal component y (i) represented by is multiplied. As a result,

(Equation 5) A despread signal r (i) represented by

When the information data d is "1", the despread signal r (i) is given by

(Equation 6) Given in. As can be seen from the expression (6), the despread signal r (i) has a fixed value of exp {j · φ} at each time i. From this, the following equation

(Equation 7) As shown in, it can be seen that the noise-to-noise ratio can be improved by adding the despread signals r (i) at each time.

On the other hand, when the information data d is "-1", the despread signal r (i) becomes

(Equation 8) Is given by

[Equation 9] Given in. Also in this case, as can be seen from the equations (8) and (9), the despread signals r (i) at each time are added for even numbers, and the despread signal r (i) for each time is odd. It can be seen that the noise-to-noise ratio can be improved by inverting the sign of and adding them.

(1-2) Overall Configuration of Receiver Here, the overall configuration of the receiver will be described. However, the configuration and operation of the transmitter are the same as those of the conventional transmitter 1 (see FIG. 22), and thus the description thereof will be omitted. In FIG. 1, in which parts corresponding to those in FIG.
Shows a receiver in the case of combining the MSK modulation system and the spread spectrum system as a whole, and is adapted to receive a spread spectrum and MSK modulated transmission signal and perform despreading and MSK modulation demodulation in the baseband. There is.

In the receiver 20, the transmission signal transmitted from the transmitter is received by the antenna 9, and the reception signal obtained as a result is input to the RF amplifier 10. RF amplifier 10
Amplifies the received signal that has been input and outputs it to the frequency conversion unit 11. The frequency conversion unit 11 converts the received signal into a low-frequency signal by performing processing opposite to that on the transmission side, and outputs the resulting received signal S10 to the quadrature detection circuit 21. The quadrature detection circuit 21 quadrature-detects the received signal S10 to obtain a quadrature-phase component, which is used as the baseband signal S11.
Is output to the despreading / demodulation unit 22 and the PN detection unit 23.

The PN detection section 23 uses the baseband signal S11.
The MSK-modulated PN code is detected, and the detection result is output to the PN generator 24 as an initialization signal S12.
The PN generator 24 is initialized based on the initialization signal S12 and generates the PN code S13 for despreading at an appropriate timing. The despreading / demodulation unit 22 despreads the baseband signal S11 using the PN code S13 generated by the PN generator 24 and demodulates the MSK modulation to obtain the information data S7. In this way, the receiver 20
Then, after the received signal is quadrature-detected as described in the above principle, despreading and MSK modulation demodulation are performed.

(1-3) Configuration of PN Detection Unit Here, the above-mentioned PN detection unit 23 will be described with reference to FIG. As shown in FIG. 2, the quadrature detection circuit 21 outputs the oscillator 30 and the oscillation signal S20 generated by the oscillator 30 to π / 2.
The reception signal S10 is configured by a delay device 31 and multipliers 32 and 33 that generate a oscillated signal S21 by phase delay, and the received signal S10 is multiplied by oscillated signals S20 and S21 that are quadrature phase waves (that is, cosine wave and sine wave), respectively. By doing so, two types of baseband signals (here, quadrature phase components I and Q) composed of quadrature phase components are output.

By the way, MSK modulation is a kind of frequency shift keying modulation. When the frequencies used for modulation are f _L and f _H , quadrature detection is performed with a quadrature clock having a frequency of (f _L + f _H ) / 2. The phases of the quadrature-phase components I and Q converted to the baseband are rotated by -π / 2 when the frequency is f _L and rotated by π / 2 when the frequency is f _H.
That is, the quadrature phase components I and Q output from the quadrature detection circuit 21 are phase-rotated by the MSK modulation.

On the other hand, the PN detector 23 includes a despreading circuit 34,
The judging device 35, the control circuit 36, and the memory circuit 37 are included. The despreading circuit 34 has a sliding correlator structure and detects a PN code from the quadrature phase components I and Q output from the quadrature detection circuit 21. Specifically, the despreading circuit 34 performs a reverse rotation on the quadrature phase components I and Q output from the quadrature detection circuit 21 so as to cancel the phase rotation generated when the PN code is MSK-modulated on the transmission side, The correlation value of the PN code is detected. And despreading circuit 3
4 outputs the correlation value as the correlation result S22.

The determiner 35 checks the correlation result S22 output from the despreading circuit 34. In this case, the despreading circuit 34
Detects the PN code in the received signal, the despreading circuit 3 concerned
The correlation result S22 output from No. 4 becomes large. Therefore, the determiner 35 determines that the PN code is detected when the correlation result S22 exceeds the predetermined threshold value, and outputs the determination result S23 to the control circuit 36 to inform that the PN code is detected.

The control circuit 36 outputs a recording signal S24 to the storage circuit 37 based on the determination result S23, and the correlation result S output from the despreading circuit 34 to the storage circuit 37.
The PN code generation timing S25 of the PN generator incorporated in the despreading circuit 34 managed by the control circuit 22 and the control circuit 36 is stored. Further, the control circuit 36 outputs the initialization signal S26 and the timing adjustment signal S27 to the despreading circuit 34 to adjust the PN code generation timing of the PN generator built in the despreading circuit 34, thereby receiving at any timing. The despreading circuit 34 is caused to detect the PN code in the signal.

The memory circuit 37 generates a PN code detection result (that is, the above-mentioned initialization signal S12) based on the stored correlation result S22 and PN code generation timing S25,
Output to the PN generator 24 (see FIG. 1). In this way, in the PN detection unit 23, the determination unit 35 determines the detection of the PN code based on the correlation result S22 obtained by the despreading circuit 34,
If the PN code is not detected, the control circuit 36 outputs the initialization signal S26 and the timing adjustment signal S27 to the despreading circuit 34 and adjusts the PN code generation timing in the despreading circuit 34, thereby changing the PN code. To detect.

(1-3-1) Configuration of the despreading circuit Here, the despreading circuit 3 provided in the PN detection section 23 described above.
The configuration of No. 4 is shown in FIG. As shown in FIG. 3, in the despreading circuit 34, the timing adjustment signal S27 output from the control circuit 36 is input to the PN generator 40. The PN generator 40 uses the same PN code S3 as the transmitting side.
0 is generated, and this timing adjustment signal S2
The generation timing of the PN code S30 can be adjusted based on 7. The PN code S30 generated by the PN generator 40 is input to the phase generator 41. The phase generator 41 calculates the amount of phase rotation that occurs when the PN code is MSK-modulated on the transmitting side based on the input PN code S30, and outputs the phase signal S31 indicating the amount of phase rotation to the phase rotator 42. To do.

On the other hand, the quadrature phase components I and Q output from the quadrature detection circuit 21 are input to the phase rotator 42, respectively. The phase rotator 42 reversely rotates the phases of the quadrature phase components I and Q according to the phase signal S31 supplied from the phase generator 41. Then, the phase rotator 42 adds the quadrature-phase components I ′ and Q ′ whose phases are reversed to the integrators 43 and 44, respectively.
Output to. In this case, if the generation timings of the PN code generated on the transmission side included in the received signal and the PN code S30 generated by the PN generator 40 match, the quadrature phase component I output from the phase rotator 42 ', Q'becomes signals in phase with no phase rotation in time. Ie PN
If the generation timing of the code S30 matches the transmission side, the phase rotation amount at the time of MSK modulation on the transmission side is canceled by the phase rotator 42.

The integrators 43 and 44 add the input quadrature phase components I'and Q'by a predetermined number of chips (here, one chip means one PN code), and Accumulated output is integrated output S32, S33
Is output to the squaring circuits 45 and 46. In this case, if the generation timing of the PN code S30 coincides with that on the transmission side and the quadrature phase components I ′ and Q ′ are in-phase signals as described above, the signals are added by the integrators 43 and 44. The ingredients are strengthened.

The squaring circuits 45 and 46 square the input integrated outputs S32 and S33, respectively, and output the squared outputs to the adder 47 as squared outputs S34 and S35.
Thus, by adding the squared outputs S34 and S35 by the adder 47, the energy value of the PN code component at the same timing as the PN generator 40 included in the received signal can be obtained. In this case, the PN code generated in the transmission side and the PN code S generated in the PN generator 40 included in the received signal
If 30 and the same timing, the energy value becomes the highest. The energy value thus obtained is output as the correlation result S22 to the determiner 35 and the storage circuit 37 (see FIG. 2).

In the despreading circuit 34 having such a configuration, P
By sequentially shifting the generation timing of the N generator 40, energy values at all timings are obtained.
Then, the obtained energy value is output as the correlation result S22 to the deciding unit 35 in the subsequent stage, and if the deciding unit 35 decides the energy value of the correlation result S22, the PN code included in the received signal can be detected. Because, as described above, the PN code generated at the transmission side and the P generated at the PN generator 40
This is because the energy value becomes the highest if the N code S30 has the same timing.

Incidentally, in the despreading circuit 34, since the generation timing of the PN generator 40 is sequentially shifted in this way, the PN generator 40 generates the PN code S30 based on the timing adjustment signal S27 as described above. The timing can be adjusted. In addition, the integrator 43,
44 is adapted to be initialized by an initialization signal S26, which allows PN at one timing.
When the detection of the code is ended and the detection is performed at another timing, the integrated values in the integrators 43 and 44 can be cleared.

The PN generator 40 will be described here.
The PN generator 40 is configured by a 15th-order M-sequence code generator, as shown in FIG. 4, for example. As is apparent from FIG. 4, the PN generator 40 is composed of 15 registers (REG1 to REG15) and five exclusive OR gates (EXOR1 to EXOR5), and outputs the M sequence code output from the register REG15. It is output as a PN code S30.

This PN generator 40 has an operation clock CK.
In addition to 1, the initialization signal S36 and the enable signal EN are input, and the PN generator 40 generates by controlling the initialization signal S36 and the enable signal EN based on the timing adjustment signal S27. The timing of the PN code S30 is adjusted.
At this time, the initialization signal S36 is used when the PN generator 40 is operated at a predetermined timing or when the timing of the PN code is found from the received signal and the PN code S30 is generated in accordance with the timing. To be done.

On the other hand, the enable signal EN is the PN generator 4
0 is operated, and is generated at the timing shown in FIG. In this case, motion clock C
Since a clock that is 8 times the normal operating speed of the PN generator 40 is used as K1, the PN generator 40 is activated by setting the enable signal EN once every 8 clocks (level "L"). It is designed to operate at normal operating speed.

By the way, in the despreading circuit 34, when the detection of the PN code ends at a certain timing, the PN code must be detected at another timing. Therefore, the PN code generation timing of the PN generator 40 must be adjusted. At this time, it is a general method to shift the PN code generation timing of the PN generator 40 by 1/2 chip. Therefore, also in the case shown in FIG. 5, the PN code generation timing is halved by adjusting the enable interval to 4 clocks, which is a half of the normal interval, based on this method.
It is adjusted so that it can be advanced. By the way, this PN
When the generator 40 delays the PN code generation timing by 1/2 chip, the enable interval may be 12 clocks.

The relationship between the enable signal EN and the initialization signal S26 supplied to the integrators 43 and 44 at this time is shown in FIG. In the case of this embodiment, as shown in FIG. 6, after adjusting the enable interval of the enable signal EN, the initialization signal S26 is set to the level "L" to initialize the integrators 43 and 44 ( Clear). Incidentally, here, the integrators 43 and 44 are initialized after the enable interval of the enable signal EN is adjusted, but in terms of timing, the adjustment of the PN code generation timing and the integrators 43 and 44 may be simultaneously performed. ,
Alternatively, the PN code generation timing may be adjusted after the integrators 43 and 44 are initialized.

The phase generator 41 provided in the despreading circuit 34 will be described. As shown in FIG. 7, in practice, the phase generator 41 is constituted by a 2-bit binary up-down counter 48, and each time the PN code S30 is supplied, the phase generator 41 depends on the value of the PN code S30. By counting up or counting down, the phase rotation amount when the PN code is MSK modulated is output as a 2-bit signal of π / 2 unit.

Specifically, the up-down counter 48
Is a clock C equal to the chip plate of PN code S30.
It operates based on K2, and counts up or counts down according to the value of the input PN code S30. In this case, when the PN code is “0” on the transmitting side, the frequency f _H is
If the frequency f _L is transmitted when the PN code is "1", the up-down counter 48 counts up when the PN code S30 is "0", and the PN code S30 is "1".
In case of, it counts down. The up-down counter 48 uses the resulting 2-bit count value as the phase signal S31 indicating the phase rotation amount (see FIG. 3).
Output).

The phase rotator 42 provided in the despreading circuit 34 will be described. As shown in FIG. 8, in practice, the phase rotator 42 comprises two inverting circuits 49, 50 and 2
It is constituted by one selector 51, 52. The I component supplied from the quadrature detection circuit 21 is input to the selectors 51 and 52 and the inverting circuit 49. The inverting circuit 49 inverts the sign of the input I component and outputs the -I component obtained as a result to the selectors 51 and 52. On the other hand, the Q component supplied from the quadrature detection circuit 21 is input to the selectors 51 and 52 and the inverting circuit 50. The inversion circuit 50 inverts the sign of the input Q component and outputs the -Q component obtained as a result to the selectors 51 and 52.

The selector 51 uses the 2-bit phase signal S31.
Signal components I, Q, -I, and -Q input as selection values based on the value of, and the selected component is an I component (that is, I'component) after phase rotation 43.
(See FIG. 3). Similarly, the selector 52 selects, based on the value of the 2-bit phase signal S31, the signal components Q, -I, -Q, I inputted as the selected values, and the selected ones after phase rotation are selected. The Q component (that is, the Q ′ component) is output to the integrator 44 (see FIG. 3).

At this time, "00", "0" of the phase signal S31
1 ”,“ 10 ”and“ 11 ”are the phase rotation amounts“ 0 ”,
Assuming that “π / 2”, “π”, and “3π / 2” are represented, “00”, “01”, “10”, and “11” of the phase signal S31.
On the other hand, the selector 51 selects and outputs I, Q, -I, and -Q, and the selector 52 selects Q, -I, and-, respectively.
Q and I are selected and output. As a result, the phase rotator 42
Then, for the I component and the Q component, “0”, “−π /
This means that the phase rotation of 2 ”,“ −π ”, and“ −3π / 2 ”has been performed, and the amount of phase rotation generated by the MSK modulation can be canceled.

(1-4) Configuration of Despreading / Demodulating Unit The despreading / demodulating unit 22 provided in the receiver 20 described above will be described. However, here, when two different PN codes are allocated to the information data and transmitted on the transmitting side (for example, when the information data S1 is “0”, the first
The despreading / demodulation unit for the case where the PN code is generated, and the second PN code is generated and transmitted when the information data S1 is "1").

As shown in FIG. 9, in the despreading / demodulation unit 22, the quadrature phase component I output from the quadrature detection circuit 21,
Q is input to the three-stage shift registers 55 and 56, respectively. In the shift register 55,
The register 55A delays the input I component and outputs the delayed I component to the despreading circuit 57 and the register 55B. The register 55B further delays the input I component, and outputs the delayed I component to the despreading circuit 59 and the register 55C. The register 55C further delays the input I component, and the delayed I component is despread circuit 61.
Output to.

On the other hand, in the shift register 56, the register 56A delays the input Q component and outputs the delayed Q component to the despreading circuit 57 and the register 56B. The register 56B further delays the input Q component, and outputs the delayed Q component to the despreading circuit 59 and the register 56C. The register 56C further delays the input Q component, and the delayed Q component is despread circuit 61.
Output to. In this case, the registers 55A, 55B, 55
The delay amounts of C and 56A, 56B, 56C are based on the outputs of the registers 55B, 56B
The delay amounts are set so that the outputs of 5A and 56A and the outputs of registers 55C and 56C are shifted by exactly 1/2 chip of the PN code.

The despreading circuits 57, 59 and 61 are for performing despreading on the I and Q components at three different timings obtained by the shift registers 55 and 56. Specifically, the despreading circuits 57, 59, and 61 internally generate two different types of PN codes corresponding to the transmission side, and detect the correlation value between the two types of PN codes and the I component and Q component. To do. Then, the despreading circuits 57, 59 and 60 calculate the correlation values for the two types of PN codes by despreading data R.
Output as _PN1 and R _PN2 respectively.

The despread data R _PN1 and R _PN2 output from the despreading circuit 59 are input to the comparator 64. Comparator 6
4 compares the sizes of the despread data R _PN1 and R _PN2 . For example, between the despread data R _PN1 and R _PN2

[Equation 10] If the relationship of

[Equation 11] Information data S obtained by demodulating "1" when the relationship of
Output as 7.

On the other hand, the despreading data R _PN1 and R _PN2 output from the despreading circuits 57 and 61 are selected by the selector 65, respectively.
66 is input. The selectors 65 and 66 respectively select one of the despread data R _PN1 and R _PN2 input based on the information data S7 output from the comparator 64. For example, the despread data R _PN1 is selected when the information data S7 is “0”, and the despread data R _PN2 is selected when the information data S7 is “1”. And selector 6
Reference numerals 5 and 66 output the selected outputs S40 and S41 to the subtractor 67, respectively.

The subtractor 67 selects the selected output S40 and the selected output S
41 is obtained (for example, selected output S41-selected output S40), and difference data S42 obtained as a result is output.
In this case, the difference data S42 output from the subtractor 67
Means that if the sign is positive, the demodulation timing is delayed, and if the sign is negative, the demodulation timing is advanced.

Here, this point will be described with reference to FIG. In FIG. 10, the signal waveforms in the figure show the temporal changes of the despread data. By the way, it is generally desirable to demodulate at the peak timing of the despread data in order to reduce the data error rate. That is, it is desirable that the demodulation timing in the figure be located at the peak of the despread data.

As described above, in order to detect whether the demodulation timing is at the optimum position, despreading is performed at timings before and after the demodulation timing, and the despread data obtained as a result is detected. Compare the size. This is because when the demodulation timing is deviated from the optimum position, the despread data that is closer to the peak becomes larger among the despread data obtained by the timing before and after, and there is a difference in the size of the despread data. is there.

For example, as shown in FIG. 10, when the demodulation timing is advanced, the despread data obtained at the preceding timing (that is, the selected output S40) is despread data obtained at the following timing (ie, the despread data). It becomes smaller than the selection output S41), and the sign of the difference data S42 becomes negative.
Therefore, when the sign of the difference data S42 is negative, it means that the demodulation timing is advanced. Similarly,
When the demodulation timing is delayed, the despread data (that is, the selected output S40) obtained at the preceding timing becomes larger than the despread data (that is, the selected output S41) obtained at the subsequent timing, and the difference data S42 is obtained. Has a positive sign. Therefore, if the sign of the difference data S42 is positive, it means that the demodulation timing is delayed.

In this way, the difference data S42 indicating the advance or the delay of the demodulation timing is the low-pass filter (L
PF) 68. The low-pass filter 68 smoothes the input difference data S42 and outputs the resulting smoothed difference data S43 to the timing control circuit 69. Normally, when the signal-to-noise ratio C / N is low, the output of the despreading circuits 57 and 61 (that is, despread data R _PN1 ,
R _PN2 ) contains a lot of noise components. Therefore, the despreading / demodulation unit 22 removes this noise component by smoothing the difference data S42 by the low-pass filter 68. In this case, since the signal component indicating the advance or delay of the demodulation timing included in the difference data S42 has a frequency sufficiently lower than the noise component, the noise component can be removed by using the low pass filter 68 in this way. it can.

The timing control circuit 69 includes a PN detector 2
A PN code used for despreading based on the initialization signal S12 supplied from S.3 (specifically, despreading circuits 57, 59, 6
The PN code generated in 1) is specified, and the advance or delay of the demodulation timing is determined based on the difference data S43 supplied from the low-pass filter 68, and the timing control signal is determined based on these determination results. S
44 is output to the despreading circuits 57, 59, 61 and each register to adjust the processing timing of each unit.

In this way, in the despreading / demodulation section 22,
The information data S7 is demodulated by generating a despreading PN code based on the PN code detection result (specifically, the initialization signal S12) obtained by the PN detection unit 23 and performing despreading. In the despreading / demodulation unit 22, the timing before and after the demodulation timing of the information data S7 (specifically, PN
Despreading is also performed at timings shifted by a code 1/2 chip), despread data at timings before and after the despreading are compared to determine whether the demodulation timing is advanced or delayed, and the demodulation timing is determined according to the result of the advance or delay determination. Fine-tune. As a result, the despreading / demodulation unit 22 can perform despreading at the optimum demodulation timing, and can reduce the data error rate even when the signal-to-noise ratio C / N is low.

(1-4-1) Configuration of Despreading Circuit Here, the despreading circuits 57, 59 and 61 provided in the above despreading / demodulation unit 22 will be described. However, since the despreading circuits 57, 59, 61 have the same configuration, only the despreading circuit 59 will be described here.

As shown in FIG. 11, the despreading circuit 59 is composed of first and second despreading circuits 70 and 71 having the same circuit configuration. The first and second despreading circuits 7
The difference between 0 and 71 is only that the PN codes S45 and S46 generated by the two PN generators 72 and 73 are different. That is, the despreading circuit 59 has a structure corresponding to the case where two different PN codes are allocated to information data on the transmitting side and transmitted as described in the despreading / demodulation unit 22 described above. The generators 72 and 73 generate the same PN codes S45 and S46 as those generated on the transmission side, and despread the PN codes S45 and S46, respectively. Incidentally, the PN generators 72 and 73 provided in the despreading circuit 59 are the PN generators described in FIG.
It corresponds to the generator 24.

First, in the first despreading circuit 70, the PN code S45 generated by the PN generator 72 is input to the phase generator 74. The phase generator 74 calculates the amount of phase rotation that occurs when the PN code is MSK-modulated on the transmitting side based on the input PN code S45, and outputs the phase signal S47 indicating the amount of phase rotation to the phase rotator 75. To do.

The phase rotator 75 has a register 55.
The quadrature phase components I and Q output from B and 56B (see FIG. 9) are input. The phase rotator 75 reversely rotates the phases of the quadrature phase components I and Q according to the phase signal S47 supplied from the phase generator 74. Then, the phase rotator 75 outputs the quadrature phase components I ₁ ′ and Q ₁ ′ whose phases are inversely rotated to the integrators 76 and 77, respectively. In this case, if the generation timings of the PN code generated on the transmission side included in the received signal and the PN code S45 generated by the PN generator 72 match, the quadrature phase component I output from the phase rotator 75 ₁ ', Q _1' is a signal in phase without a time-phase rotation. That is, if the generation timing of the PN code S45 matches the transmission side, the phase rotation amount when the MSK modulation is performed on the transmission side is canceled by the phase rotator 75.

The integrators 76 and 77 add the input quadrature phase components I ₁ ′ and Q ₁ ′ by a predetermined number of chips, and add up the integrated output S48,
The signal is output to the squaring circuits 78 and 79 as S49. In this case, if the generation timing of the PN code S45 coincides with that on the transmission side and the quadrature phase components I ₁ 'and Q ₁ ' become in-phase signals as described above, the integrators 76 and 77 add them together. Thereby strengthening the signal component.

The squaring circuits 78 and 79 square the input integrated outputs S48 and S49, respectively, and output the squared outputs to the adder 80 as squared outputs S50 and S51.
Thus, by adding the squared outputs S50 and S51 by the adder 80, the energy value of the PN code component at the same timing as the PN generator 72 included in the received signal can be obtained. The energy value (that is, the correlation) thus obtained is output to the comparator 64 (see FIG. 9) as despread data R _PN1 .

Incidentally, the PN generator 72 receives the timing adjustment signal S52 which is a part of the timing control signal S44, and the PN generator 72 determines the generation timing of the PN code S45 in accordance with the timing adjustment signal S52. It is designed to be adjustable. As a result, in the despreading circuit 59, the generation timing of the PN code S45 can be adjusted according to the detection result of the PN detection unit 23 as described above, and the PN code S45 of the demodulation timing can be adjusted according to the determination result of advance or delay of the demodulation timing. The generation timing can be finely adjusted.

An initialization signal S53, which is a part of the timing control signal S44, is input to the integrators 76 and 77, and the integrators 76 and 77 can be initialized according to the initialization signal S53. ing. As a result, in the despreading circuit 59, one despreading is completed, and the integrated values in the integrators 76 and 77 can be cleared before the next despreading is started.

The configuration and operation of the other second despreading circuit 71 are basically the same as those of the first despreading circuit 70. That is, another P generated by the PN generator 73
The N code S46 is input to the phase generator 81, where P
The phase rotation amount is calculated based on the N code S46 to generate the phase signal S54. The phase rotator 82 performs reverse rotation on the input quadrature phase components I and Q based on the phase signal S54, and performs the reverse rotation on the quadrature phase component I ₂ ′,
Q ₂ 'is output to the integrators 83 and 84, respectively.

The integrators 83 and 84 add the input quadrature phase components I ₂ ′ and Q ₂ ′ for a predetermined number of chips, and add up the integrated outputs as a square circuit 85, as integrated outputs S55 and S56. Output to 86. Square circuit 85, 8
6 squares the respective integrated outputs S55 and S56, and outputs the squared outputs to the adder 87 as squared outputs S57 and S58. Thus, by the adder 87, 2
By adding the power outputs S57 and S58, the energy value of the PN code component at the same timing as the PN generator 73 included in the received signal can be obtained. The energy value (that is, the correlation) thus obtained is the despread data R
It is output to the comparator 64 (see FIG. 9) as _PN2 .

Incidentally, also in the second despreading circuit 71, the generation timing of the PN code S46 can be adjusted by inputting the timing adjustment signal S52 which is a part of the timing control signal S44 to the PN generator 73. In addition, by inputting the initialization signal S53, which is a part of the timing control signal S44, to the integrators 83 and 84, the integrated value can be cleared after the end of despreading once. There is.

As the phase generators 74 and 81, circuits having the same structure as the phase generator 41 shown in FIG. 7 are used. As the phase rotators 75 and 82, circuits having the same configuration as the phase rotator 42 shown in FIG. 8 are used.

(1-5) Operation and effects of the embodiment With the above configuration, when receiving a transmission signal transmitted by a method combining MSK modulation and spread spectrum, the receiver 20 first receives the antenna 9 and RF amplification. Part 10
And quadrature detection is performed on the reception signal S10 obtained via the frequency conversion unit 11 to obtain quadrature phase components I and Q.
Detect the sign.

In this case, the PN detector 23 generates the same PN code S30 as that on the transmitting side, as shown in FIGS. 2 and 3, and MSK modulates the PN code on the transmitting side based on the generated PN code S30. The amount of phase rotation that occurs when is calculated. Then, in the PN detection unit 23, the quadrature phase components I and Q are inversely rotated according to the phase rotation amount (specifically, the phase signal S31) to cancel the phase rotation, and the quadrature phase component I ′ obtained as a result is obtained. Q'is added to each of the predetermined chips to strengthen the signal component, and the PN code and PN contained in the received signal are added.
The correlation with the PN code S30 generated by the generator 40 is obtained. Then, the PN detection section 23 detects the PN code included in the received signal by comparing the obtained correlation result S22 with a predetermined threshold value.

At this time, in the PN detector 23, M is transmitted on the transmitting side.
By canceling the amount of phase rotation that occurs when SK modulation is performed, the quadrature phase components I ′ and Q ′ that cancel the amount of phase rotation can be added together to strengthen the signal component. As a result, the PN detection unit 23 can reliably detect the PN code transmitted on the transmission side even when the signal-to-noise ratio C / N is low.

Next, in the receiver 20, the PN code is generated at the timing detected by the PN detecting section 23, and the despreading / demodulating section 22 uses the PN code to obtain the quadrature phase component I,
Despread Q and demodulate information data. in this case,
In the despreading / demodulation unit 22, as shown in FIGS. 9 and 10, the same PN codes S45 and S46 as those on the transmitting side are generated, and based on the generated PN codes S45 and S46, PN is generated on the transmitting side.
The amount of phase rotation that occurs when the code is MSK modulated is calculated. Then, in the despreading / demodulation unit 22, the quadrature phase components I and Q are inversely rotated according to the phase rotation amount (specifically, the phase signals S47 and S54) to cancel the phase rotation, and the obtained quadrature phase is obtained. Ingredients I ₁ ', Q ₁ ', I ₂ ',
Q ₂ 'is added to each predetermined chip to strengthen the signal component, and the energy value (correlation) of the PN code contained in the received signal is obtained to obtain despread data R _PN1 and R _PN2 . Then, the despreading / demodulation unit 22 compares the sizes of the obtained despread data R _PN1 and R _PN2 and demodulates the information data S7.

At this time, the despreading / demodulation unit 22 cancels the phase rotation amount generated when the MSK modulation is performed on the transmitting side, so that the quadrature phase components I ₁ ′ and Q ₁ ′ that cancel the phase rotation amount. , I ₂ ', Q ₂ ' can be added together to enhance the signal component. As a result, the despreading / demodulation unit 22 can reliably demodulate the information data S7 even when the signal-to-noise ratio C / N is low.

In the despreading / demodulation section 22, when demodulating the information data S7, the quadrature phase components I and Q are also despread at the timing before and after the demodulation. Then, the advance or delay of the demodulation timing is detected based on the despread data R _PN1 and R _PN2 obtained at the timing before and after that, and the PN code S is detected based on the detection result (specifically, the difference data S43).
The generation timings of S45 and S46 are finely adjusted, and the demodulation timing is finely adjusted. As a result, the despreading / demodulation unit 22 can perform despreading at the optimum demodulation timing,
Even if the signal-to-noise ratio C / N is low, the data error rate can be reduced.

According to the above configuration, the PN detector 23 cancels the amount of phase rotation that occurs when MSK modulation is performed on the transmitting side, so that the quadrature phase components I'and Q'which cancel the amount of phase rotation are cancelled. Can be added together to enhance the signal component, which results in a signal-to-noise ratio C
Even if / N is low, the PN code transmitted on the transmission side can be detected reliably.

Further, the despreading / demodulation unit 22 cancels the phase rotation amount generated when the MSK modulation is performed on the transmitting side, so that the quadrature phase components I ₁ ′, Q ₁ ′, I that cancel the phase rotation amount are canceled. ₂ ', Q _2' can be made enhance signal components are summed, respectively, thereby the signal to noise ratio C / N for demodulating reliably information data S7 or low. Further, in the despreading / demodulation unit 22, despreading is performed even before and after the demodulation timing,
By finely adjusting the demodulation timing based on the despread data R _PN1 and R _PN2 , the despreading can be performed at the optimum demodulation timing, and thus data can be obtained even when the signal-to-noise ratio C / N is low. The error rate of can be reduced.

In this way, it is possible to realize the PN detection section 23, the despreading / demodulation section 22 and the receiver 20 which can exhibit sufficient performance even when the signal-to-noise ratio C / N is low.

(2) Second Embodiment Another configuration of the PN detector will be described as a second embodiment.

(2-1) Configuration of PN Detecting Section In FIG. 12 in which parts corresponding to those in FIG. 2 are assigned the same reference numerals, 90 denotes a PN detecting section as a whole, which is a quadrature output from the quadrature detection circuit 21. The phase components I and Q are despreading circuit 9
It is designed to input 1. The despreading circuit 91 has a matching filter structure, and detects the PN code used on the transmitting side from the quadrature phase components I and Q output from the quadrature detection circuit 21. Specifically, the despreading circuit 91 parallelizes the reverse rotation so as to cancel the phase rotation generated when the PN code is MSK-modulated on the transmitting side with respect to the quadrature phase components I and Q output from the quadrature detection circuit 21. Then, the correlation value of the PN code is detected. Then, the despreading circuit 91 outputs the correlation value as the correlation result S22.

The determiner 35 checks the correlation result S22 output from the despreading circuit 91. In this case, the despreading circuit 91
Detects the PN code in the received signal, the despreading circuit 9 concerned
The correlation result S22 output from 1 increases. Therefore, the determiner 35 determines that the PN code is detected when the correlation result S22 exceeds the predetermined threshold value, and outputs the determination result S23 to the control circuit 36 to inform that the PN code is detected.

The control circuit 36 outputs the recording signal S24 to the storage circuit 37 based on the determination result S23, and the correlation result S output from the despreading circuit 91 to the storage circuit 37.
The PN code generation timing S25 managed by the control circuit 22 and the control circuit 36 is stored. The storage circuit 37 uses the stored correlation result S22 and PN code generation timing S25 to store the PN
Code detection result (that is, the initialization signal S12 described above)
Is generated and output.

(2-1-1) Configuration of the despreading circuit Here, the despreading circuit 9 provided in the above-mentioned PN detection unit 90.
The configuration of No. 1 is shown in FIG. As shown in FIG. 13, the despreading circuit 91 is a parallel output type having a number of stages of (2 × M−1), where M is the length of the PN code for calculating the correlation (that is, the number of chips). Two shift registers 92, 93
, M phase rotators PR _{1 to} PR _M , two adders 95 and 96 having M input terminals, two squaring circuits 97 and 98, and an adder 99 having two input terminals. It is composed by.

In this case, the shift register 92 has a 1/2
1-stage register R ₁₁ for delaying by a chip and 1 /
It is composed of two-stage registers R _{12 to} R _1M for delaying one chip in units of two chips, so that the outputs of the first to Mth registers of the delay time interval of one chip can be taken out. There is. Similarly, the shift register 93 has 1
A one-stage register R ₂₁ that delays by 1/2 chip,
It is composed of two-stage registers R _{22 to} R _2M for delaying one chip in a unit of ½ chip so that the first to Mth register outputs having a delay time interval of one chip can be taken out. Has been done.

First, the I component output from the quadrature detection circuit 21 is input to the shift register 92. The shift register 92 delays the I component by 1/2 chip units, and outputs the resulting I-component of the first to M a (I ₁ ~I _M) to the phase rotator PR ₁ to PR _M respectively. On the other hand, the Q component output from the quadrature detection circuit 21 is input to the shift register 93. The shift register 93 This delays the Q component by 1/2 chip units, and outputs the results obtained first register output of the M a (Q ₁ to Q _M) to the phase rotator PR ₁ to PR _M respectively.

The phase rotator PR ₁ reversely rotates the phase of the pair of quadrature phase components I ₁ and Q ₁ so as to cancel the phase rotation when the PN code is MSK-modulated, and performs the reverse rotation. The applied quadrature phase components I ₁ 'and Q ₁ ' are output. Similarly, the phase rotator PR ₂ to PR _M is to cancel the phase rotation when the PN code to MSK modulation, quadrature-phase component I ₂ ~I _M serving as input pairs to Q ₂ to Q _M Respectively, the phases are inversely rotated, and the quadrature-phase components I ₂ ′ to I _M ′ and Q ₂ ′ to Q _M ′ that have been inversely rotated are output.

Of the quadrature phase components output from the phase rotators PR _{1 to} PR _{M, the} I components (I ₁ 'to I _M ') are input to the adder 95, respectively. The adder 95 adds the input I components (I ₁ ′ to I _M ′) and outputs the addition result to the squaring circuit 97 as an addition output S60. On the other hand, Q components of the quadrature phase component output from the phase rotator _{PR 1 ~PR M (Q 1 '} ~Q M') is input to the adders 96. The adder 96 receives the input Q
The components (Q ₁ 'to Q _M ') are added up, and the addition result is output to the squaring circuit 98 as an addition output S61.

The squaring circuits 97 and 98 square the input addition outputs S62 and S63, respectively, and output the squared outputs to the adder 99 as squared outputs S62 and S63. Thus, the square output S62, S6 is generated by the adder 99.
By adding 3, the energy values for M chips of the quadrature phase components I and Q can be obtained. The obtained energy value is used as the correlation result S22 in the determiner 35 and the storage circuit 3.
7 (see FIG. 12).

[0093] Here, the phase rotator PR ₁ to PR _M described above, the circuit (100 of FIG. 14 (A) ~ FIG 14 (D)
Any one of 103) is used. First, FIG.
The circuit 100 shown in (A) shows a circuit when the amount of phase rotation is “0”, and the quadrature phase component I ′ that has been inversely rotated,
As Q ′, the input quadrature phase components I and Q are output as they are. Next, a circuit 101 shown in FIG. 14B shows a circuit in the case where the phase rotation amount is “π / 2”, and the Q component and the I component are the reversely rotated quadrature phase components I ′ and Q ′. The -I components obtained by inversion are output respectively.

Next, a circuit 102 shown in FIG. 14C shows a circuit when the phase rotation amount is "π", and the Q component is inverted as the inversely rotated quadrature phase components I'and Q '. The -I component obtained by inverting the obtained -Q component and I component is output. Next, a circuit 103 shown in FIG. 14D shows a circuit in the case where the phase rotation amount is “3π / 2”. The Q component is inverted as the inversely rotated quadrature phase components I ′ and Q ′. The obtained -Q component and I component are output respectively.

[0095] Is this way which one to adopt one of the circuit 100 to 103, such, the phase rotator (PR ₁ to PR _M) performs the phase rotation of the ordinal number of the output of the shift register (92 or 93), or It is determined by what kind of PN code is used. When the type of the PN code is determined, how the phase is rotated when the MSK modulation is performed is determined. Therefore, for example, the phase rotation of the second to Mth outputs with respect to the first output of the shift register is performed. It is decided as a fixed value. Therefore, which circuit (100 to 103) should be adopted is determined according to the determined fixed value. That is, when the amount of phase rotation is “0”, the circuit 100 shown in FIG. 14A is adopted, and when the amount of phase rotation is “π / 2”, the circuit 101 shown in FIG. 14B.
Is adopted and the phase rotation amount is “π”, FIG.
The circuit 102 shown in is adopted, and the phase rotation amount is "3π / 2".
In that case, the circuit 103 shown in FIG. 14D may be employed.

(2-2) Operation and Effect of the Embodiment In the above-mentioned configuration, in the PN detecting section 90, as shown in FIGS. 12 and 13, the despreading circuit 91 receives the received signal (quadrature phase component I, Detect the correlation between Q) and the PN code,
The PN code is detected based on the correlation result. Specifically, in the despreading circuit 91, the PN code is transmitted to the MS on the transmitting side.
To cancel the amount of phase rotation that occurs when K modulation is performed,
The quadrature phase components I and Q are inversely rotated in parallel, and the inversely rotated quadrature phase components I and Q are added for the number of chips of the PN code (that is, the quadrature phase component I ₁ ′-
I _M 'and Q ₁ ' to Q _M 'are added together). Then, the sum of them (specifically, the addition output S6
0, S61) to calculate the energy value to detect the correlation between the quadrature phase components I and Q and the PN code.

In this case, the quadrature phase components I and Q are inversely rotated so as to cancel out the phase rotation amount generated when the PN code is MSK modulated on the transmitting side. , Q can be added to strengthen the signal component. As a result, in the PN detection unit 90, even if the signal-to-noise ratio C / N is low, the P transmitted from the transmission side is transmitted.
It is possible to reliably detect the N code. Further, the despreading circuit 91 has a so-called match filter structure in which the PN code is detected in parallel by sequentially shifting the quadrature phase components I and Q, so that the PN code can be detected quickly. .

According to the above configuration, the amount of phase rotation generated when MSK modulation is performed on the transmission side is canceled, so that the quadrature phase components I and Q that cancel the amount of phase rotation are added together to strengthen the signal component. Therefore, even if the signal-to-noise ratio C / N is low, the P
It is possible to reliably detect the N code.

(3) Third Embodiment Here, another configuration of the despreading / demodulation section will be described as a third embodiment. However, also in the case of this embodiment, when two different types of PN codes are assigned to the information data on the transmission side and transmitted (for example, when the information data S1 is "0", the first PN code is generated). , The case where the second PN code is generated and transmitted when the information data S1 is “1”) will be described.

(3-1) Configuration of Despreading / Demodulation Section In FIG. 15 in which parts corresponding to those in FIG. 9 are assigned the same reference numerals, 110 indicates a despreading / demodulation section as a whole, from the quadrature detection circuit 21. The output quadrature phase components I and Q are input to the despreading circuit 111.

The despreading circuit 111 has a structure of a Matto filter, performs reverse rotation in parallel so as to cancel the phase rotation generated when MSK modulating the PN code, and obtains the correlation value for the PN code obtained as a result. This is a circuit that outputs as despread data. The despreading circuit 111 internally generates two different types of PN codes corresponding to the transmitting side, inversely rotates the quadrature phase components I and Q using the two types of PN codes, respectively, and obtains the resulting two types. The correlation value for the PN code is output as despread data R _PN1 and R _PN2 . Of the two types of despread data R _PN1 and R _PN2 , the despread data R _PN1 is input to the register 112 and the selector 116, and the despread data R _PN2 is input to the register 114 and the selector 116.

The register 112 delays the input despread data R _PN1 by 1/2 chip, and outputs the delayed despread data R _PN1 to the register 113 and the comparator 117. The register 113 receives the input despread data R
_PN1 is further delayed by ½ chip, and the delayed despread data R _PN1 is output to the selector 118. On the other hand, the register 114 _{halves the} input despread data R _PN2 .
The chip is delayed by a chip, and the delayed despread data R _PN2 is output to the register 115 and the comparator 117. Register 1
15 further _halves the input despread data R _PN2
The chip is delayed by a chip, and the delayed despread data R _PN2 is output to the selector 118.

The comparator 117 compares the values of the input despread data R _PN1 and R _PN2 , and outputs the one with the higher level as demodulated information data S7. For example, if the transmitting side generates a first PN code when the information data S1 is "0" and generates a second PN code when the information data S1 is "1", the comparator 117 Despread data R
_{If PN1} is larger than the despread data R _PN2 , set “0”,
If the despread data R _PN1 is smaller than the despread data R _PN2 , “1” is output as the information data S7. The information data S7 thus obtained is used for selecting the selectors 116 and 118.
Is output as a selection control signal.

The selector 116 receives the input despread data R
_PN1 and R _PN2 are selected. When the information data S7 is "0", the despread data R _PN1 is selected, and when the information data S7 is "1", the despread data R _PN2 is selected. , The selected one as the selected output S70
It outputs to 19. Similarly, the selector 118 also selects the input despread data R _PN1 and R _PN2 . When the information data S7 is "0", the despread data R _PN1 is selected and the information data S7 is " In the case of "1", the despread data R _PN2 is selected, and the selected one is output to the subtractor 119 as a selection output S71.

The subtracter 119 selects the selected output 70 and the selected output S
The difference with S. 71 is obtained (for example, selection output S71-selection output S70), and the resulting difference data S72 is output to the low pass filter (LPF) 120. In this case, the difference data S72 output from the subtractor 119 means that the demodulation timing is delayed if the sign is positive, and that the demodulation timing is advanced if the sign is negative. . This is because, as described in the first embodiment, when the demodulation timing is delayed, the earlier one in terms of timing (that is, the output of the register 113 or the register 115) becomes larger, and when the demodulation timing is advanced. Is because the first one becomes smaller in timing.

The low-pass filter 120 smoothes the input difference data S72, and outputs the resulting smoothed difference data S73 to the timing control circuit 121.
Normally, when the signal-to-noise ratio C / N is low, the despreading circuit 11
The output of 1 (that is, despread data R _PN1 and R _PN2 ) contains a lot of noise components. Therefore, the despreading / demodulation unit 110 removes this noise component by smoothing the difference data S72 with the low-pass filter 120. In this case, since the signal component indicating the advance or delay of the demodulation timing included in the difference data S72 has a frequency sufficiently lower than the noise component, the noise component is removed by using the low-pass filter 120 in this way. You can

The timing control circuit 121 determines whether the demodulation timing is advanced or delayed on the basis of the difference data S73 supplied from the low-pass filter 120, and based on the result of this determination, outputs the timing control signal S74 to the despreading circuit 111 and the register 112-. Output to 115 to adjust the processing timing of each unit.

As described above, in the despreading / demodulation unit 110, the despreading data R output from the registers 112 and 114 is used.
_The information data S7 is demodulated by comparing _PN1 and R _PN2 with the comparator 117. In addition, the despreading / demodulation unit 11
At 0, the despread data R _PN1 and R _PN2 are registered in the register 112.
By the 115 connexion delay despread data before and after the timing of the demodulation timing by R _PN1, give R _PN2, despread data R _PN1 of the front and rear timing, R
The advance or delay of the demodulation timing is detected by checking the difference in _PN2 , and the demodulation timing is adjusted according to the detection result. As a result, the despreading / demodulation unit 110 can perform despreading at the optimum timing, and the signal-to-noise ratio C
Even if / N is low, the data error rate can be reduced.

(3-1-1) Configuration of Despreading Circuit Here, the configuration of the above despreading circuit 111 will be described. As shown in FIG. 16, the despreading circuit 111 is actually composed of two correlators 130 and 131. In this case, the correlators 130 and 131 each have a structure of a matching filter, and two different types of PN codes (2
A correlation value between a PN code of one kind and a code obtained by inverting the PN code is included) and a received signal (that is, quadrature phase components I and Q) is calculated.

For example, the correlator 130 receives the received signals (I, Q)
To detect the correlation value of the first PN code, and output the correlation value as despread data R _PN1 . The correlator 131 detects the correlation value of the second PN code from the received signals (I, Q) and outputs the correlation value as despread data R _PN2 .
Incidentally, the correlators 130 and 131 are the timing control circuit 1
The processing timing can be adjusted according to the timing control signal S74 supplied from the control unit 21.

Here, the specific configuration of the correlators 130 and 131 will be described. However, since the correlators 130 and 131 have the same circuit configuration, only the correlator 130 will be described here. As shown in FIG. 17, the correlator 130
Where M is the length of the PN code for calculating the correlation (that is, the number of chips), two parallel output type shift registers 132 and 133 having (2 × M−1) stages and M
Phase rotators PR _{1 to} PR _M , two adders 135 and 136 having M input terminals, and two squaring circuits 1
37 and 138, and an adder 139 having two input terminals
It is composed by.

In this case, the shift register 132 is 1 /
1-stage register R ₁₁ that delays by 2 chips and 1
It is constituted by two-stage registers R _{12 to} R _1M for delaying one chip in a unit of / 2 chips, and is adapted to take out the outputs of the first to Mth registers of the delay time interval of one chip. ing. Similarly, the shift register 133
Is a one-stage register R that delays by 1/2 chip
₂₁ and two-stage registers R _{22 to} R _2M for delaying one chip in 1/2 chip unit, and outputs the first to Mth register outputs having a delay time interval of one chip. It is designed to be taken out.

[0113] Further the register R ₁₁ to R _1M, are input timing control signals S74 output from the timing control circuit 121 to the R ₂₁ to R _2M, each register R ₁₁ to R
_1M, R ₂₁ to R _2M is to allow the demodulation process at the optimum timing, by connexion operation timing to the timing control signal S74 is adapted to be adjusted.

First, the I component output from the quadrature detection circuit 21 is input to the shift register 132. The shift register 132 delays this I component in 1/2 chip units, and outputs the resulting 1st to Mth register outputs (I ₁ ...
I _M ) to the phase rotators PR ₁ -PR _M , respectively. On the other hand, the Q component output from the quadrature detection circuit 21 is
It is input to the shift register 133. Shift register 1
33 delays the Q component by 1/2 chip units, and outputs the result from the first obtained of the M register output (Q ₁ to Q _M) into phase rotator PR ₁ to PR _M respectively.

The phase rotator PR ₁ reversely rotates the phase of the pair of quadrature phase components I ₁ and Q ₁ so as to cancel the phase rotation when the PN code is MSK-modulated, and performs the reverse rotation. The applied quadrature phase components I ₁ 'and Q ₁ ' are output. Similarly, the phase rotator PR ₂ to PR _M is to cancel the phase rotation when the PN code to MSK modulation, quadrature-phase component I ₂ ~I _M serving as input pairs to Q ₂ to Q _M Respectively, the phases are inversely rotated, and the quadrature-phase components I ₂ ′ to I _M ′ and Q ₂ ′ to Q _M ′ that have been inversely rotated are output.

The I components (I ₁ ′ to I _M ′) of the quadrature phase components output from the phase rotators PR _{1 to} PR _M are input to the adder 135, respectively. The adder 135 adds the input I components (I ₁ ′ to I _M ′) and outputs the addition result to the squaring circuit 137 as an addition output S80. On the other hand, Q components of the quadrature phase component output from the phase rotator _{PR 1 ~PR M (Q 1 '} ~Q M') is
Each is input to the adder 136. The adder 136 adds the input Q components (Q ₁ 'to Q _M '), and adds the added Q components as an addition output S81 to the squaring circuit 13
Output to 8.

The squaring circuits 137 and 138 square the input addition outputs S80 and S81, respectively, and output the squared outputs to the adder 139 as squared outputs S82 and S83. Thus, the square output S8 is output by the adder 139.
2 and S83 are added to obtain the quadrature phase components I and Q.
The energy value for M chips is obtained. The obtained energy value is output as despread data R _PN1 representing the correlation result.

By the way, the phase rotators PR _{1 to} PR _M include
The circuits (100 to 1) shown in FIGS.
Any one of 03) is used. Which circuit is used, or a phase rotator (PR ₁ to PR _M) is what performs the phase rotation of the ordinal number of the output of the shift register (132 or 133), or to use any kinds of things as the PN code It is decided by.

(3-2) Operation and effect of the embodiment With the above-mentioned configuration, the despreading / demodulation section 110 is configured as shown in FIG.
As shown in FIGS. 5 to 17, the despreading circuit 111 detects the correlation between the received signal (quadrature phase components I and Q) and the PN code, and demodulates the information data S7 based on the correlation result. Specifically, in the despreading circuit 111, the quadrature phase components I and Q are inversely rotated so as to cancel the amount of phase rotation that occurs when the PN code is MSK modulated on the transmitting side, and the inversely rotated quadrature is performed. The phase components I and Q are added up by the number of chips of the PN code (that is, the quadrature phase component I ₁ '...
I _M 'and Q ₁ ' to Q _M 'are added together). Then, the sum thereof (specifically, the addition output S8
0, S81), the energy value is calculated based on (0, S81) to detect the correlation between the quadrature phase components I and Q and the PN code.

In this case, the quadrature phase components I and Q are inversely rotated so as to cancel the amount of phase rotation that occurs when the PN code is MSK-modulated on the transmitting side. , Q can be added to strengthen the signal component. As a result, the despreading / demodulation unit 110 can reliably detect the PN code transmitted from the transmission side and demodulate the information data S7 even when the signal-to-noise ratio C / N is low. In addition, the despreading circuit 111
Since the PN code is detected in parallel by sequentially shifting the quadrature-phase components I and Q, the so-called matching filter structure is adopted, so that the PN code can be detected quickly.

Further, in the despreading / demodulating section 110, the despreading data R _PN1 and R _PN2 output as the correlation result from the despreading circuit 111 are delayed by the registers 112 to 115, thereby making it possible to obtain the timing before and after the demodulation timing. _Despread data R _PN1 and R _PN2 are obtained, and the advance or delay of the demodulation timing is detected by examining the difference between the despread data R _PN1 and R _PN2 before and after the timing, and the demodulation timing is set according to the detection result. adjust. As a result, the despreading / demodulation unit 110 can perform despreading at the optimum timing, and can reduce the data error rate even when the signal-to-noise ratio C / N is low.

According to the above configuration, the phase rotation amount generated when the MSK modulation is performed on the transmission side is canceled, so that the quadrature phase components I and Q that cancel the phase rotation amount are added to strengthen the signal component. Therefore, even if the signal-to-noise ratio C / N is low, the information data S can be reliably
7 can be demodulated.

(4) Other Embodiments (4-1) Part 1 In the above-mentioned first embodiment, the despreading / demodulation unit 22 is used.
11 has been described as the despreading circuit 59 of FIG. 11, but the present invention is not limited to this, and one PN code and its inverted code are used as two kinds of PN codes on the transmission side. In this case, the despreading circuit 1 as shown in FIG.
40 may be used. Specifically,
As shown in FIG. 18 in which parts corresponding to those in FIG. 11 are assigned the same reference numerals, the first PN code S45 generated by the PN generator 72 is provided by providing an inverting circuit 141 instead of the PN generator 73. It is inverted to generate the second PN code S90. By doing so, the number of PN generators can be reduced by one, and the configuration can be further simplified.

(4-2) Part 2 Further, in the above-described first embodiment, the despreading / demodulation unit 22 is used.
11 has been described as the despreading circuit 59 of FIG. 11, but the present invention is not limited to this, and one PN code and its inverted code are used as two kinds of PN codes on the transmission side. In this case, the despreading circuit 1 as shown in FIG.
45 may be used.

More specifically, as shown in FIG. 19 in which parts corresponding to those in FIG.
The first PN code S45 generated in 2 is input to the phase generator 74. The phase generator 74 calculates the amount of phase rotation generated when MSK modulation is performed on the transmitting side based on the input first PN code S45, and the phase signal S4 indicating the amount of phase rotation is calculated.
7 is output to the phase rotator 75.

The phase rotator 75 has a quadrature phase component I,
Q is input. The phase rotator 75 receives the quadrature phase components I and Q according to the phase signal S47 supplied from the phase generator 74.
The phase is rotated in the opposite direction (that is, the phase rotation is canceled to make the quadrature phase components I and Q into signals of the same phase). Of the quadrature-phase components I ′ and Q ′ whose phases are inversely rotated, the I ′ component is input to the integrators 76 and 83 via the switch 146, and the Q ′ component is input to the integrators 77 and 8 via the switch 147.
4 is input. In this case, the switch 146 is switched for each chip, and the I ′ component is alternately input to the integrator 76 and the integrator 83. Similarly, the switch 147 is switched every chip, and the Q ′ component is alternately input to the integrator 77 and the integrator 84.

The integrators 76, 77, 83, 84 add the input I'components or Q'components by a predetermined number of chips. The integration results output from the integrators 76 and 83 are the adder 148 and the subtractor 14 respectively.
9 is input. Similarly, the integration results output from the integrators 77 and 84 are the adder 150 and the subtractor 151, respectively.
Is input to

The adder 148 adds the integration result of the integrator 76 and the integration result of the integrator 83, and the subtractor 149 subtracts the integration result of the integrator 76 and the integration result of the integrator 83.
Similarly, the adder 150 adds the integrated result of the integrator 77 and the integrated result of the integrator 84, and the subtracter 151 adds the integrator 77.
And the result of integration by the integrator 84 is subtracted. In this case, the output of the adder 148 is the integration result of the I ′ component for the first PN code, and the output of the subtractor 149 is the first
The result is the integration result of the I ′ component with respect to the inversion code of the PN code. Further, the output of the adder 150 becomes the integration result of the Q ′ component for the first PN code, and the output of the subtractor 151 is the first
The result is the integration result of the Q ′ component with respect to the inversion code of the PN code.

The output of the adder 148 is input to the squaring circuit 78, where it is squared and then input to the adder 80 as a squared output S50. The output of the subtractor 149 is input to the squaring circuit 85, where it is squared and then the squared output S5.
7 is input to the adder 87. Similarly, the adder 15
The output of 0 is input to the squaring circuit 79, where it is squared and then input to the adder 80 as a squared output S51. Further, the output of the subtractor 51 is input to the squaring circuit 86, where it is squared and then input to the adder 87 as a squared output S58.

Thus, the adder 80 outputs the squared output S5.
By adding 0 and S51, the energy value (that is, the correlation) of the PN code component at the same timing as the first PN code generated by the PN generator 72 included in the received signal (quadrature phase components I and Q) is obtained. can get. Similarly, the adder 8
7 by adding the squared outputs S57 and S58, the first signal included in the received signal (quadrature phase components I and Q) is added.
The energy value (that is, the correlation) of the PN code component at the same timing as the inversion code of the PN code is obtained. The energy values thus obtained are the despread data R respectively.
It is output as _PN1 and R _PN2 . Two kinds of P like this
When one PN code and its inverted code are used as the N code, it is possible to further simplify the configuration of the despreading circuit 145 by utilizing the property.

(4-3) Part 3 Further, in the above-mentioned second and third embodiments, the case where the circuit as shown in FIG. 14 is used as the phase rotator has been described, but the present invention is not limited to this. Alternatively, a phase rotator 160 as shown in FIG. 20 may be used. However, also in this case, how much phase is rotated by the phase rotator 160 depends on what kind of PN code is used,
Alternatively, it is determined by the number of the output of the shift register that is phase-rotated.

Here, the phase rotator 160 shown in FIG. 20 will be specifically described. Phase rotator 160 shown here
Indicates that the phase rotation amount (“0”, “π / 2”, “π”, “3π / 2”) can be designated so as to correspond to a plurality of PN codes. The phase rotator 160 has 2
One inversion circuit 161, 162, two selectors 163, 164 having a structure of four inputs and one output, and a register 165.
It is composed by.

Phase signal S1 input to register 165
The setting value of 00 differs depending on the type of PN code and the output of the shift register for which the phase is rotated.
It is set by a predetermined control means such as (Central Processing Unit). For example, the amount of phase rotation “0”, “π /
2 "," π ", and" 3π / 2 "are each" 0 ".
0 ”,“ 01 ”,“ 10 ”, and“ 11 ”are phase signals S10.
Written as 0. This written phase signal S1
00 is supplied from the register 165 to the selectors 163 and 164.

The I component is input to the selectors 163 and 164 and also to the inverting circuit 161. Inversion circuit 16
1 reverses the sign of the input I component and obtains -I
The components are output to the selectors 163 and 164, respectively. On the other hand, the Q component is input to the selectors 163 and 164, and also to the inverting circuit 162. The inversion circuit 162 inverts the sign of the input Q component, and outputs the -Q component obtained as a result to the selectors 163 and 164, respectively.

The selector 163 selects the signal components I, Q, -I, -Q input as selection values based on the value of the 2-bit phase signal S100 supplied from the register 165, and selects the selected signal component. It is output as the I component (that is, the I ′ component) after the phase rotation. Similarly, the selector 164
Selects the signal components Q, -I, -Q, I input as selection values based on the value of the 2-bit phase signal S100 supplied from the register 165, and selects the selected components after phase rotation. Output as Q component (that is, Q'component).

In this case, "00" of the phase signal S100,
Selectors 163 for “01”, “10”, and “11”
Select and output the signal components I, Q, -I, -Q, respectively, and the selector 164 outputs the signal components Q, -I, -Q, respectively.
Select I and output. Thereby, in the phase rotator 160, "0", "-π / 2", "-π", "-3π / 2".
Phase rotation can be performed, and the phase rotation caused by the MSK modulation can be canceled.

(4-4) Part 4 In the third embodiment described above, the despreading / demodulation section 11
16 and 17 are used as the despreading circuit 111 of 0, the present invention is not limited to this, and one PN code is used as two types of PN codes on the transmission side.
When a code and its inverted code are used, a despreading circuit 170 as shown in FIG. 21 may be used.

More specifically, as shown in FIG. 21, in which parts corresponding to those in FIG.
70 denotes two parallel output type shift registers 132 and 133 having (2 × M−1) stages, where M is the length of the PN code for calculating the correlation (that is, the number of chips).
The M phase rotator PR ₁ and to PR _M, M / 2 pieces (however,
When M is an odd number, four adders 171 to 174 having M / 2 or (M-1) / 2 input terminals and four adders 175, 177, 18 having two input terminals
3, 184 and two subtractors 1 with two input terminals
76, 178 and four squaring circuits 179-182.

First, the I component is input to the shift register 132. The shift register 132 delays this I component in 1/2 chip units, and outputs the resulting first to Mth register outputs (I _{1 to} I _M ) respectively to the phase rotators PR ₁ to PR.
Output to PR _M. On the other hand, the Q component is the shift register 13
Input to 3. Shift register 133 This delays the Q component by 1/2 chip units, and outputs the results obtained first register output of the M a (Q ₁ to Q _M) to the phase rotator PR ₁ to PR _M respectively.

The phase rotators PR _{1 to} P _M correspond to the input quadrature phase components I _{1 to} I _M and Q _{1 to} Q _M so as to cancel the phase rotation when the PN code is MSK modulated. And inversely rotate the phases respectively, and output the inversely rotated quadrature phase components I ₁ ′ to I _M ′ and Q ₁ ′ to Q _M ′ to the adders 171 to 174 for each quadrature phase component and every other chip. To do. That of the phase rotator PR ₁ to PR _M,
The I component output from the odd number is input to the adder 171, and the I component output from the even number is input to the adder 172. Similarly, of the phase rotator PR ₁ to PR _M,
The Q component output from the odd number is input to the adder 173, and the Q component output from the even number is input to the adder 174.

The adders 171 and 172 add the input I components and output the added components to the adder 175 and the subtractor 176, respectively. Similarly, adders 173, 1
74 adds the input Q components and outputs the added components to the adder 177 and the subtractor 178, respectively. Adders 175 and 177 add the input I component or Q component, and subtractors 176 and 178 add the input I component or Q component.
Subtract the components. In this case, the adder 175 calculates the I component of the correlation value of the PN code, and the subtractor 176 calculates P component.
The I component of the correlation value of the code obtained by inverting the N code is calculated. Similarly, the adder 177 calculates the Q component of the correlation value of the PN code, and the subtractor 178 calculates the Q component of the correlation value of the code obtained by inverting the PN code.

The output of the adder 175 is input to the squaring circuit 179, where it is squared and then input to the adder 183 as a squared output S110. The output of the subtractor 176 is input to the squaring circuit 180, where it is squared and then input to the adder 184 as a squared output S111. Similarly, the output of the adder 177 is input to the squaring circuit 181.
After being squared here, the adder 1 is output as a square output S112.
83 is input. The output of the subtractor 178 is input to the squaring circuit 182, where it is squared and then the squared output S1.
13 is input to the adder 184.

Thus, the adder 183 outputs the squared output S
By adding 110 and S112, the correlation (that is, energy value) between the received signal (quadrature phase components I and Q) and the PN code can be obtained. Similarly, by adding the squared outputs S111 and S113 with the adder 184, the correlation (that is, energy value) between the received signal (quadrature phase components I and Q) and the code obtained by inverting the PN code is obtained. . The correlations thus obtained are the despread data R respectively.
It is output as _PN1 and R _PN2 . Two kinds of P like this
When one PN code and its inverted code are used as the N code, the property of the despreading circuit 170 can be further simplified.

(4-5) Part 5 Further, in the above-described embodiment, the case where the present invention is applied to the receiver 20 of the system in which the MSK modulation system and the spread spectrum system are combined has been described. Not only the GMSK modulation (Gaussian filtered Minimum
Shift Keying: It can be widely applied to a receiver of a system in which a so-called band-limited narrow band frequency shift keying) system and a spread spectrum system are combined.

[0145]

As described above, according to the present invention, the quadrature phase component is inversely rotated so as to cancel the phase rotation generated when the spread code is narrow-band frequency shift keyed at the transmitting side, By detecting the correlation value for the spread code, even if the signal-to-noise ratio C / N is low, it is possible to add the quadrature-phase components that cancel the phase rotation to strengthen the signal component. Can be reliably detected. Signal-to-noise ratio C /
It is possible to realize a spread code detection circuit that can exhibit sufficient performance even when N is low.

Further, reverse phase rotation is performed in parallel on the quadrature phase component so as to cancel the phase rotation that occurs when the spread code is subjected to narrowband frequency shift keying modulation on the transmission side, and the correlation value for the spread code is detected. By doing so, even when the signal-to-noise ratio C / N is low, the quadrature-phase component that cancels the phase rotation can be added to strengthen the signal component, and the spread code can be detected reliably. Spreading codes can be detected quickly by applying phase rotation in parallel. Signal-to-noise ratio C / N
It is possible to realize a spread code detection circuit that can exhibit sufficient performance even when the value is low.

Further, 2 output from the first despreading circuit
The difference between the correlation value for the two kinds of spread codes and the correlation value for the two kinds of spread codes output from the third despreading circuit is calculated to obtain the first and second shift registers and the first to third inverse codes. By adjusting the processing timing of the spreading circuit, it is possible to demodulate the information data at the optimum timing, thereby reducing the data error rate even when the signal-to-noise ratio C / N is low. . As a result, it is possible to realize a despread demodulation circuit that can exhibit sufficient performance even when the signal-to-noise ratio C / N is low.

The difference between the correlation value for the two types of spreading codes output from the despreading circuit and the correlation value for the two types of spreading codes output from the third and fourth registers is calculated to determine the difference from the first to the first. By adjusting the processing timings of the register 4 and the despreading circuit, it is possible to demodulate the information data at the optimum timing, and thus the error rate of the data can be reduced even when the signal-to-noise ratio C / N is low. Can be made smaller. Signal-to-noise ratio C / N
It is possible to realize a despread demodulation circuit capable of exhibiting sufficient performance even when the value is low.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a receiver when an MSK modulation system and a spread spectrum system are combined according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a PN detection unit.

FIG. 3 is a block diagram showing a configuration of a despreading circuit of a PN detection unit.

FIG. 4 is a block diagram showing an example of a PN generator.

FIG. 5 is a schematic diagram showing the timing of an enable signal EN used in a PN generator.

FIG. 6 is a schematic diagram showing a relationship between an enable signal EN used for a PN generator and an initialization signal S26 used for an integrator.

FIG. 7 is a block diagram showing a configuration of a phase generator.

FIG. 8 is a block diagram showing a configuration of a phase rotator.

FIG. 9 is a block diagram showing a configuration of a despreading / demodulating unit.

FIG. 10 is a schematic diagram showing the relationship between demodulation timing and despread data.

FIG. 11 is a block diagram showing the configuration of the despreading circuit of the despreading / demodulation unit.

FIG. 12 is a block diagram showing a configuration of a PN detection unit of the second embodiment.

FIG. 13 is a block diagram showing the configuration of the despreading circuit of the PN detection unit.

FIG. 14 is a block diagram showing the configuration of a phase rotator.

FIG. 15 is a block diagram showing the configuration of a despreading / demodulating unit according to the third embodiment.

FIG. 16 is a block diagram showing the configuration of the despreading circuit of the despreading / demodulation unit.

FIG. 17 is a block diagram showing a configuration of a correlator of a despreading circuit.

FIG. 18 is a block diagram showing a configuration of a despreading circuit of a despreading / demodulating unit according to another embodiment.

FIG. 19 is a block diagram showing a configuration of a despreading circuit of a despreading / demodulating unit according to another embodiment.

FIG. 20 is a block diagram showing the configuration of a phase rotator according to another embodiment.

FIG. 21 is a block diagram showing the configuration of the despreading circuit of the despreading / demodulating unit according to another embodiment.

FIG. 22 is a block diagram showing a configuration of a transmitter when a conventional MSK modulation system and a spread spectrum system are combined.

FIG. 23 is a block diagram showing a configuration of a receiver with respect to a conventional transmitter.

[Explanation of symbols]

1 ... Transmitter, 3, 15, 24, 40, 72, 73 ...
PN generator, 8, 20 ... Receiver, 14, 23, 90 ...
... PN detection unit, 22, 110 ... despreading / demodulation unit, 21
... Quadrature detection circuit, 34, 57, 59, 61, 91, 1
11, 140, 145, 170 ... Despreading circuit, 41,
74, 81 ... Phase generator, 42, 75, 82, PR ₁
To PR _M, 160 ...... phase rotator, 130, 131 ......
Correlator.

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[Procedure amendment]

[Submission date] June 2, 1995

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[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread code detection circuit, a despread demodulation circuit, and a receiver, and MSK modulation (Mi
It is suitable for application to, for example, a digital cordless telephone device or the like that communicates by a communication system that combines a number shift keying (so-called minimum frequency shift keying) system and a spread spectrum system.

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[0010]

In order to solve such a problem, in the present invention, a spread code is detected from a transmission signal transmitted by a communication system combining a minimum frequency shift keying modulation system and a spread spectrum system. In the spreading code detection circuit, reverse phase rotation is applied to the quadrature phase component so as to cancel the phase rotation that occurs when the spreading code is minimum frequency shift keyed at the transmitting side, and the correlation value for the spreading code is detected A spreading circuit is provided, and the detection of the spreading code is determined by comparing the correlation value output from the despreading circuit with a predetermined threshold value.

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Further, according to the present invention, in the spreading code detecting circuit for detecting the spreading code from the transmission signal transmitted by the communication system in which the minimum frequency shift keying system and the spread spectrum system are combined, the spreading code is transmitted on the transmitting side. Is applied to the quadrature phase components in parallel so as to cancel the phase rotation that occurs when the minimum frequency shift modulation is performed,
A despreading circuit for detecting the correlation value for the spreading code is provided, and the detection of the spreading code is determined by comparing the correlation value output from the despreading circuit with a predetermined threshold value.

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Further, according to the present invention, the despreading demodulation circuit for demodulating information data from a transmission signal transmitted by a communication system in which the minimum frequency shift keying system and the spread spectrum system are combined has a three-stage configuration. And delays each signal component of the quadrature phase component to delay the first to third
And the first and second shift registers for outputting the quadrature phase components of and the first to the third quadrature phase components so as to cancel the phase rotation generated when the spread code is minimum frequency shift-modulated on the transmission side. On the other hand, the first to third despreading circuits that perform the inverse rotation of the phase and detect the correlation values of the two kinds of spreading codes corresponding to the information data are provided, and the 2 output from the second despreading circuit is provided. The information data is determined by comparing the magnitudes of the correlation values for the two types of spreading codes, and the correlation values for the two types of spreading codes output from the first despreading circuit and the third despreading circuit are output. The processing timings of the first and second shift registers and the first to third despreading circuits are adjusted by obtaining the difference between the correlation values of the two types of output spreading codes.

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[Correction method] Change

[Correction content]

Further, in the present invention, in the despreading demodulation circuit for demodulating the information data from the transmission signal transmitted by the communication system in which the minimum frequency shift keying system and the spread spectrum system are combined, the spreading code is provided on the transmitting side. And a despreading circuit that detects the correlation value of two types of spreading codes corresponding to information data by performing the reverse rotation of the phase on the quadrature phase component so as to cancel the phase rotation that occurs when the minimum frequency shift modulation is performed. , First and second registers for respectively delaying the correlation values for the two types of spreading codes output from the despreading circuit, and correlation values for the two types of spreading codes output from the first and second registers And third and fourth registers for delaying respectively, and comparing the magnitudes of the correlation values for the two types of spreading codes output from the first and second registers. By determining the information data, the difference between the correlation values for the two types of spreading codes output from the despreading circuit and the correlation values for the two types of spreading codes output from the third and fourth registers. Then, the processing timings of the first to fourth registers and the despreading circuit are adjusted.

[Procedure correction 22]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

[Function] The phase is inversely rotated for the quadrature phase component so as to cancel the phase rotation generated when the spread code is subjected to the minimum frequency shift keying modulation on the transmission side, and the correlation value for the spread code is detected. As a result, even if the signal-to-noise ratio C / N is low, the quadrature-phase components that cancel the phase rotation can be added to strengthen the signal component.

[Procedure amendment 23]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

In order to cancel the phase rotation that occurs when the spread code is subjected to the minimum frequency shift keying modulation on the transmission side, the reverse rotation of the phase is performed in parallel for the quadrature phase component so that the correlation value for the spread code is detected. As a result, even if the signal-to-noise ratio C / N is low, the quadrature phase components that cancel the phase rotation can be added to strengthen the signal component, and by performing the phase rotation in parallel, the spread code Can be detected quickly.

[Procedure correction 24]

[Document name to be amended] Statement

[Correction target item name] 0144

[Correction method] Change

[Correction content]

(4-5) Part 5 Further, in the above-described embodiment, the case where the present invention is applied to the receiver 20 of the system in which the MSK modulation system and the spread spectrum system are combined has been described. Not limited to, GMSK modulation (Gaussian filter)
ered Minimum Shift Keyin
g: It can be widely applied to a receiver of a system in which a so-called band-limited minimum frequency shift keying) system and a spread spectrum system are combined.

[Procedure correction 25]

[Document name to be amended] Statement

[Name of item to be corrected] 0145

[Correction method] Change

[Correction content]

[0145]

As described above, according to the present invention, the quadrature phase component is inversely rotated and spread so as to cancel the phase rotation that occurs when the spread code is subjected to the minimum frequency shift keying modulation on the transmitting side. By detecting the correlation value for the code, even if the signal-to-noise ratio C / N is low, it is possible to add the quadrature-phase components that cancel the phase rotation to strengthen the signal component. It can be reliably detected. Signal-to-noise ratio C / N
It is possible to realize a spread code detection circuit that can exhibit sufficient performance even when the value is low.

[Procedure Amendment 26]

[Document name to be amended] Statement

[Name of item to be corrected] 0146

[Correction method] Change

[Correction content]

Further, reverse phase rotation is performed in parallel on the quadrature phase component so as to cancel the phase rotation that occurs when the spreading code is subjected to the minimum frequency shift keying modulation on the transmission side, and the correlation value for the spreading code is detected. By doing so, even when the signal-to-noise ratio C / N is low, the quadrature-phase component that cancels the phase rotation can be added to strengthen the signal component, and the spread code can be reliably detected and the phase Spreading codes can be quickly detected by applying rotation in parallel. Signal-to-noise ratio C / N
It is possible to realize a spread code detection circuit that can exhibit sufficient performance even when the value is low.

Claims (34)

[Claims] 1. A spreading code detection circuit for detecting a spreading code from a transmission signal transmitted by a communication system combining a narrow band frequency shift keying system and a spread spectrum system, and receiving the transmission signal to obtain a spread code. The quadrature detection circuit that extracts the quadrature phase component by multiplying the received signal by the quadrature phase wave, and the quadrature phase component that cancels the phase rotation that occurs when the spread code is narrow-band frequency shift keyed at the transmission side. Despreading circuit for performing a reverse rotation of the phase to detect the correlation value for the spreading code, and comparing the correlation value output from the despreading circuit with a predetermined threshold value An expansion circuit characterized by comprising a judgment circuit for judging detection and a control circuit for adjusting the timing of the spreading code in the despreading circuit according to the judgment result of the judgment circuit. Scatter code detection circuit. 2. The despreading circuit, based on the spreading code generating circuit for generating the spreading code and the spreading code output from the spreading code generating circuit, transmits the spreading code to a narrow band frequency bias on the transmitting side. A phase generating circuit that calculates the amount of phase rotation that occurs when the signal is transmodulated; and a phase rotating circuit that performs reverse rotation of the phase on the quadrature phase component in accordance with the amount of phase rotation calculated by the phase generating circuit. , A correlation value output circuit for obtaining and outputting a correlation value for the spread code based on the quadrature phase component returned to the in-phase signal component by the phase rotation circuit. The spread code detection circuit according to Item 1. 3. The correlation value output circuit includes first and second integrating circuits for adding the I component and the Q component of the quadrature phase component returned to the in-phase signal component, respectively, and the first and second integrating circuits. I added by the integrating circuit of 2
A first and a second squaring circuit for squaring a component and a Q component respectively; and an adding circuit for summing the I and Q components squared by the first and second squaring circuits. 3. The signal component added by the adder circuit is output as a correlation value for the spread code.
The spread code detection circuit described in 1. 4. The phase generating circuit is composed of a 2-bit binary up-down counter, and counts up or counts down according to the value of the spreading code each time the spreading code is supplied, 3. The spread code detecting circuit according to claim 2, wherein the phase rotation amount is output as a 2-bit signal of π / 2 unit. 5. The phase rotation circuit inputs first and second inverting circuits for respectively inverting the I and Q components of the input quadrature phase component, and inputs the I and Q components as selection values. At the same time, the -I and -Q components whose signs are inverted by the first and second inversion circuits are input, and the 2-bit phase signal representing the amount of phase rotation output from the phase generation circuit is input. By selecting the selection value according to the above, a first selection circuit that outputs the I component that has been inversely rotated in units of π / 2, and the I component and the Q component as selection values are input. The -I component and the -Q component whose signs are inverted by the first and second inversion circuits are input, and the above-mentioned two-bit phase signal representing the amount of phase rotation output from the phase generation circuit is output in accordance with the above-mentioned phase signal. By selecting the selected value, π The spread code detection circuit according to claim 2, further comprising a second selection circuit that outputs a Q component that is inversely rotated by a unit of / 2. 6. A spread code detection circuit for detecting a spread code from a transmission signal transmitted by a communication system which is a combination of a narrow band frequency shift keying system and a spread spectrum system. The quadrature detection circuit that extracts the quadrature phase component by multiplying the received signal by the quadrature phase wave, and the quadrature phase component that cancels the phase rotation that occurs when the spread code is narrow-band frequency shift keyed at the transmission side. The phase is inversely rotated in parallel with respect to the despreading circuit for detecting the correlation value for the spreading code, and the correlation value output from the despreading circuit is compared with a predetermined threshold value. A spread code detection circuit, comprising: a determination circuit for determining the detection of the spread code. 7. The despreading circuit has (2.times.M-1) stages when the number of chips of the spreading code is M, and the I component of the quadrature phase component is 1/2 chip. A first shift register which outputs the first to Mth I components in a delay time interval of one chip after delaying by a unit; and (2 × M-1) stages, From the first and second shift registers, which outputs the first to Mth Q components of the delay time interval of 1 chip by delaying the Q component of each chip by 1/2 chip unit. The first to Mth phase rotations are performed on the paired I component and Q component to reverse the phase so as to cancel the phase rotation that occurs when the spread code is narrow-band frequency shift keyed on the transmission side. Circuit and the I-phase counter-rotated by the first to Mth phase rotation circuits. Based on the amount and Q components, spreading code detection circuit according to claim 6, characterized in that it comprises a correlation value output circuit for outputting the correlation value for the spread code. 8. The correlation value output circuit includes a first adder circuit for adding back-rotated I components, and a second adder circuit for adding back-rotated Q components. The I component added by the first adder circuit is added to 2
The first square circuit for multiplication and the Q component added by the second adder circuit
A third squaring circuit for squaring, an I component squared by the first squaring circuit, and a Q component squared by the second squaring circuit are added together. 8. The spread code detection circuit according to claim 7, further comprising an adder circuit, wherein the signal component added by the third adder circuit is output as a correlation value for the spread code. 9. The first to Mth phase rotation circuits are provided with respect to the input I component and Q component,
A circuit that outputs the Q component as it is, or a circuit that outputs -Q component and I component for the input I component and Q component respectively, or a circuit that outputs the input I component and Q component, The spread code is configured by either a circuit that outputs the -I component or the -Q component, or a circuit that outputs the Q component or the -I component with respect to the input I component or Q component, respectively. The spread code detection circuit according to claim 7, wherein a circuit to be adopted is determined according to the above. 10. The first to Mth phase rotation circuits are values corresponding to the amount of phase rotation that occurs when the spread code is narrow-band frequency shift keyed on the transmitting side or the amount of phase rotation that cancels it. A two-bit register into which is written, first and second inverting circuits that sign-invert the input I and Q components, the I and Q components as selection values, and the first And the -I component and the -Q component whose sign is inverted by the second inverting circuit are input, and the selected value is selected according to the value written in the register to reverse the value in π / 2 units. A first selection circuit that outputs a rotated I component, the I component and the Q component as selection values are input, and the signs are inverted by the first and second inversion circuits. I component and -Q component are input , A second selection circuit for outputting the Q component which is inversely rotated by π / 2 unit by selecting the selection value according to the value written in the register. The spread code detection circuit according to claim 7. 11. A despreading demodulation circuit for demodulating information data from a transmission signal transmitted by a communication system which is a combination of a narrow band frequency shift keying system and a spread spectrum system, and receives and obtains the transmission signal. And a quadrature detection circuit for extracting a quadrature phase component by multiplying the received signal by a quadrature phase wave, and a three-stage configuration. And the first and second shift registers for outputting the quadrature-phase component of the quadrature-phase component and the quadrature-phase components The signals are output from the first to third despreading circuits that perform the inverse rotation of the phase for each and detect the correlation values for the two types of spreading codes corresponding to the information data, and the second despreading circuit. A comparison circuit that determines and outputs information data by comparing the magnitudes of the correlation values of the two types of spread codes, and the first despreading circuit according to the information data output from the comparison circuit. A first selection circuit that selects and outputs one of the correlation values for the two types of spreading codes output from the circuit, and the third despreading circuit according to the information data output from the comparison circuit. The difference between the second selection circuit, which selects and outputs one of the correlation values for the two types of spread codes output from the circuit, and the difference between the correlation values output from the first and second selection circuits. A subtraction circuit, a low-pass filter for smoothing the difference between the correlation values obtained by the subtraction circuit, and the first and second shift registers according to the difference between the correlation values smoothed by the low-pass filter. as well as Serial despreading demodulation circuit, characterized in that it comprises a timing control circuit from the first to adjust the processing timing of the third despreading circuit. 12. The first, second or third despreading circuit comprises a first spreading code generating circuit for generating a first spreading code of the two types of spreading codes, and the first spreading code generating circuit. A first phase generation circuit for calculating the amount of phase rotation generated when the transmission side performs narrowband frequency shift keying on the first spread code based on the first spread code output from the spread code generator. A first phase rotation circuit that performs reverse rotation of the phase on the input quadrature phase component according to the phase rotation amount calculated by the first phase generation circuit; and the first phase rotation circuit. A first correlation value output circuit that obtains and outputs a correlation value for the first spreading code based on the quadrature phase component returned to the in-phase signal component by the circuit, and the two types of spreading codes. A second spreading code generating circuit for generating the second spreading code Secondly, a phase rotation amount generated when the transmission side performs narrowband frequency shift keying of the second spreading code based on the second spreading code output from the second spreading code generation circuit is calculated. And a second phase rotation circuit that performs reverse rotation of the phase of the input quadrature phase component according to the amount of phase rotation calculated by the second phase generation circuit, A second correlation value output circuit for obtaining and outputting a correlation value for the second spreading code based on the quadrature phase component returned to the in-phase signal component by the second phase rotation circuit. The despreading demodulation circuit according to claim 11, wherein: 13. The first or second correlation value output circuit, wherein the I component of the quadrature phase component returned to the in-phase signal component,
First and second integrating circuits for adding Q components respectively, and I added by the first and second integrating circuits.
A first and a second squaring circuit for squaring a component and a Q component respectively; and an adding circuit for summing the I and Q components squared by the first and second squaring circuits. , The signal component added by the adding circuit is output as a correlation value for the spreading code.
2. The despread demodulation circuit according to item 2. 14. The first or second phase generation circuit is constituted by a 2-bit binary up-down counter, and the spread code of the first or second spread code is supplied every time the spread code is supplied. 13. The phase rotation amount is output as a 2-bit signal of .pi. / 2 unit by counting up or counting down according to the value.
The despreading demodulation circuit according to 1. 15. The first or second phase rotation circuit includes first and second inverting circuits for inverting the sign of the I component and the Q component of the input quadrature phase component, and the I value as the selection value. The component and the Q component are input, the -I component and the -Q component whose sign is inverted by the first and second inversion circuits are input, and the phase rotation amount output from the phase generation circuit is calculated. A first selection circuit that outputs an I component that has been inversely rotated in units of π / 2 by selecting the selection value in accordance with the 2-bit phase signal that is expressed, and the I component and the Q component as selection values. Is input, the -I component and the -Q component whose signs are inverted by the first and second inversion circuits are input, and a 2-bit signal indicating the amount of phase rotation output from the phase generation circuit is input. Select the above selection value according to the phase signal The Rukoto, despreading demodulation circuit according to claim 12, characterized in that it comprises a second selection circuit for outputting a Q component reverse rotation is performed at [pi / 2 units. 16. The first, second or third despreading circuit includes a first spreading code generating circuit for generating a first spreading code of the two types of spreading codes, and the first spreading code generating circuit. A first phase generation circuit for calculating the amount of phase rotation that occurs when the transmission side performs narrowband frequency shift keying on the first spread code based on the first spread code output from the spread code generator. A first phase rotation circuit that performs reverse rotation of the phase on the input quadrature phase component according to the phase rotation amount calculated by the first phase generation circuit; and the first phase rotation circuit. A first correlation value output circuit for obtaining and outputting a correlation value for the first spreading code based on the quadrature phase component returned to the in-phase signal component by the circuit, and the first spreading code By inverting it, the second spread code of the above two kinds of spread codes is An inversion circuit that generates a code and the second spread code output from the inversion circuit are used to calculate the amount of phase rotation that occurs when the second spread code is narrow-band frequency shift-modulated on the transmission side. A second phase generating circuit, and a second phase rotating circuit that reversely rotates the phase of the input quadrature phase component in accordance with the amount of phase rotation calculated by the second phase generating circuit. A second correlation value output circuit for obtaining and outputting a correlation value for the second spread code based on the quadrature phase component returned to the in-phase signal component by the second phase rotation circuit. The despreading demodulation circuit according to claim 11, further comprising: 17. The first or second correlation value output circuit comprises an I component of a quadrature phase component returned to the in-phase signal component,
First and second integrating circuits for adding Q components respectively, and I added by the first and second integrating circuits.
A first and a second squaring circuit for squaring a component and a Q component respectively; and an adding circuit for summing the I and Q components squared by the first and second squaring circuits. , The signal component added by the adding circuit is output as a correlation value for the spreading code.
6. The despread demodulation circuit according to item 6. 18. The first or second phase generating circuit is constituted by a 2-bit binary up-down counter, and the spread code of the first or second spread code is supplied every time the spread code is supplied. 17. The phase rotation amount is output as a 2-bit signal of .pi. / 2 unit by counting up or counting down according to the value.
The despreading demodulation circuit according to 1. 19. The first or second phase rotation circuit includes first and second inverting circuits for inverting the signs of the I component and Q component of the input quadrature phase component, and the I value as a selection value. The component and the Q component are input, the -I component and the -Q component whose sign is inverted by the first and second inversion circuits are input, and the phase rotation amount output from the phase generation circuit is calculated. A first selection circuit that outputs an I component that has been inversely rotated in units of π / 2 by selecting the selection value in accordance with the 2-bit phase signal that is expressed, and the I component and the Q component as selection values. Is input, the -I component and the -Q component whose signs are inverted by the first and second inversion circuits are input, and a 2-bit signal indicating the amount of phase rotation output from the phase generation circuit is input. Select the above selection value according to the phase signal The Rukoto, despreading demodulation circuit according to claim 16, characterized in that it comprises a second selection circuit for outputting a Q component reverse rotation is performed at [pi / 2 units. 20. The first, second or third despreading circuit is a spreading code generating circuit for generating a first spreading code of the two types of spreading codes, and outputs from the spreading code generating circuit. Based on the first spread code that is performed, a phase generation circuit that calculates a phase rotation amount that occurs when performing narrowband frequency shift keying, and a phase rotation amount that is calculated by the phase generation circuit, Of the quadrature phase component that reverses the phase of the input quadrature component and the quadrature component returned to the in-phase signal component by the phase rotator circuit, the I component is alternated for each chip. Of the first and second integrating circuits for integrating and the quadrature phase components returned to the in-phase signal components by the phase rotating circuit, the Q component is alternately integrated for each chip. The integrating circuit and the first and second integrating circuits A first adder circuit for adding the I components integrated together, a first subtraction circuit for obtaining the difference between the I components integrated by the first and second integrating circuits, and the third and fourth A second adding circuit for adding the Q components integrated by the integrating circuit, and a second subtracting circuit for obtaining the difference between the Q components integrated by the third and fourth integrating circuits, The difference between the first squaring circuit for squaring the I component added by the first adding circuit and the I component obtained by the first subtracting circuit is 2
A second squaring circuit for multiplying, a third squaring circuit for squaring the Q component added by the second adding circuit, and a Q component obtained by the second subtracting circuit The difference of 2
By adding the fourth squaring circuit for multiplication, the I component squared by the first squaring circuit, and the Q component squared by the third squaring circuit, A third adder circuit for obtaining and outputting a correlation value for the first spread code, a difference between the I components squared by the second square circuit, and the fourth square circuit. Then, by adding the difference of the I component squared, the correlation value for the second spreading code, which is the sign of the first spreading code, is obtained and output.
12. The despreading demodulation circuit according to claim 11, further comprising: 21. The phase generating circuit is constituted by a 2-bit binary up-down counter, and counts up or counts down according to the value of the spread code each time the first spread code is supplied. 21. The despreading demodulation circuit according to claim 20, wherein the phase rotation amount is output as a 2-bit signal of π / 2 unit. 22. The phase rotation circuit inputs first and second inversion circuits for respectively inverting the I and Q components of the input quadrature phase component, and inputs the I and Q components as selection values. At the same time, the -I and -Q components whose signs are inverted by the first and second inversion circuits are input, and the 2-bit phase signal representing the amount of phase rotation output from the phase generation circuit is input. By selecting the selection value according to the above, a first selection circuit that outputs the I component that has been inversely rotated in units of π / 2, and the I component and the Q component as selection values are input. The -I component and the -Q component whose signs are inverted by the first and second inversion circuits are input, and the above-mentioned two-bit phase signal representing the amount of phase rotation output from the phase generation circuit is output in accordance with the above-mentioned phase signal. By selecting a selection value Despreading demodulation circuit according to claim 20, characterized in that it comprises a second selection circuit for outputting a Q component reverse rotation is performed at [pi / 2 units. 23. A despreading demodulation circuit for demodulating information data from a transmission signal transmitted by a communication system which is a combination of a narrow band frequency shift keying system and a spread spectrum system. The quadrature detection circuit that extracts the quadrature phase component by multiplying the received signal by the quadrature phase wave, and the quadrature phase component that cancels the phase rotation that occurs when the spread code is narrow-band frequency shift keyed at the transmission side. And a despreading circuit that detects the correlation values of the two types of spreading codes corresponding to the information data, and the correlation values of the two types of spreading codes output from the despreading circuit. First and second registers which are respectively delayed, and third and third which delay the correlation values for the two kinds of spread codes output from the first and second registers, respectively. And a fourth register, a comparison circuit that determines and outputs information data by comparing the magnitudes of the correlation values for the two types of spread codes output from the first and second registers, and a selection value. As a first selection, the correlation values for the two types of spreading codes output from the despreading circuit are input as, and one of the selection values is selected and output according to the information data output from the comparison circuit. The circuit and the correlation values for the two kinds of spread codes output from the third and fourth registers as selection values are input, and one of the selection values is selected according to the information data output from the comparison circuit. A second selection circuit for selecting and outputting, a subtraction circuit for obtaining the difference between the correlation values output from the first and second selection circuits, and a smoothing for the difference between the correlation values obtained by the subtraction circuit. Do A pass filter and a timing control circuit for adjusting the processing timing of the first to fourth registers and the despreading circuit according to the difference in the correlation value smoothed by the low pass filter. Despreading demodulator circuit. 24. The despreading circuit includes a first correlator that determines one of the correlation values for the two types of spreading codes and a second correlator that determines the other of the correlation values for the two types of spreading codes. 3. The correlator of claim 2
3. A despreading demodulation circuit according to item 3. 25. The first or second correlator has (2.times.M-1) number of stages, where M is the number of chips of the spreading code for obtaining the correlation value. Of the first to Mth I-components of the delay time interval of 1 chip by delaying the I-component of the above by 1/2 chip unit, and (2 × M−1) stages. A second shift register for delaying the Q component of the quadrature phase component in units of ½ chip and outputting the first to Mth Q components in the delay time interval of one chip; The pair of I component and Q component output from the second shift register is subjected to reverse phase rotation so as to cancel the phase rotation that occurs when the spread code is subjected to narrow band frequency shift keying modulation on the transmitting side. The first to Mth phase rotation circuits and the first to Mth phase rotation circuits are provided. 25. The despread demodulation according to claim 24, further comprising: a correlation value output circuit that obtains and outputs a correlation value for the spread code based on the I component and the Q component that are inversely rotated. circuit. 26. The correlation value output circuit includes a first adder circuit for adding I components that have been inversely rotated and a second adder circuit for adding Q components that have been inversely rotated. The I component added by the first adder circuit is added to 2
The first square circuit for multiplication and the Q component added by the second adder circuit
A third squaring circuit for squaring, an I component squared by the first squaring circuit, and a Q component squared by the second squaring circuit are added together. 26. The despreading demodulation circuit according to claim 25, further comprising an adding circuit, wherein the signal component added by the third adding circuit is output as a correlation value for the spreading code. 27. The first to Mth phase rotation circuits are provided with respect to the input I component and Q component,
A circuit that outputs the Q component as it is, or a circuit that outputs -Q component and I component for the input I component and Q component respectively, or a circuit that outputs the input I component and Q component, The spread code is configured by either a circuit that outputs the -I component or the -Q component, or a circuit that outputs the Q component or the -I component with respect to the input I component or Q component, respectively. 26. The despreading demodulation circuit according to claim 25, wherein the circuit to be adopted is determined according to 28. The first to Mth phase rotation circuits each have a phase rotation amount generated when the spread code is narrow-band frequency shift keyed on the transmitting side or a value corresponding to the phase rotation amount canceling the phase rotation amount. A two-bit register into which is written, first and second inverting circuits that sign-invert the input I and Q components, the I and Q components as selection values, and the first And the -I component and the -Q component whose sign is inverted by the second inverting circuit are input, and the selected value is selected according to the value written in the register to reverse the value in π / 2 units. A first selection circuit that outputs a rotated I component, the I component and the Q component as selection values are input, and the signs are inverted by the first and second inversion circuits. I component and -Q component are input , A second selection circuit for outputting the Q component which is inversely rotated by π / 2 unit by selecting the selection value according to the value written in the register. Claim 25
The despreading demodulation circuit according to 1. 29. The despreading circuit has (2.times.M-1) number of stages, where M is the number of chips of the spreading code for obtaining the correlation value, and the I component of the quadrature phase components is 1 A first shift register for delaying by 1/2 chip unit and outputting the 1st to Mth I components in a delay time interval of 1 chip; and (2 × M−1) stages, and the quadrature phase A second shift register for delaying the Q component of the components by 1/2 chip unit and outputting the first to Mth Q components at a delay time interval of 1 chip; and the first and second shift registers described above. The pair of the I component and the Q component output from the first to Mth components are inversely rotated so as to cancel the phase rotation generated when the spread code is narrow-band frequency shift keyed at the transmission side. Reverse rotation by the phase rotation circuit of No. 1 and the first to Mth phase rotation circuits. 24. A despread demodulation circuit according to claim 23, further comprising: a correlation value output circuit for obtaining and outputting a correlation value for the two types of spreading codes based on the applied I component and Q component. . 30. A first adder circuit for adding an odd-numbered I component among the I components inversely rotated by the first to Mth phase rotation circuits, respectively. And a second adder circuit that adds even-numbered I components among the I components that have been inversely rotated by the first to Mth phase rotation circuits, and the first to Mth phases. A third adder circuit for adding the odd-numbered Q components among the Q components reversely rotated by the rotation circuit, and reverse rotation by the first to Mth phase rotation circuits. A fourth addition circuit for adding even-numbered Q components among the Q components, an I component added by the first addition circuit, and an I component added by the second addition circuit. A fifth adding circuit for adding the component and the first adding circuit First subtraction circuit for subtracting the I component added by the second addition circuit and the I component added by the second addition circuit, the Q component added by the third addition circuit, and the fourth addition circuit A sixth adder circuit for adding the Q component added by the circuit, a Q component added by the third adder circuit, and a Q component added by the fourth adder circuit. A second subtraction circuit for subtracting, a first squaring circuit for squaring the I component added by the fifth addition circuit, and an I component subtracted by the first subtraction circuit A second squaring circuit for squaring, a third squaring circuit for squaring the Q component added by the sixth adding circuit, and a second subtracting circuit for subtracting The fourth squaring circuit squaring the Q component, the I component squared by the first squaring circuit, and the third squaring circuit. And a squared Q component, and outputs the sum as a correlation value of one of the correlation values for the two types of spreading codes; and the second squaring circuit. And the Q component squared by the fourth squaring circuit are added, and the sum is added to the other of the correlation values for the two types of spreading codes. 30. The despreading demodulation circuit according to claim 29, further comprising: an eighth adder circuit for outputting as a correlation value. 31. The first to Mth phase rotation circuits are provided with respect to the input I component and Q component,
A circuit that outputs the Q component as it is, or a circuit that outputs -Q component and I component for the input I component and Q component respectively, or a circuit that outputs the input I component and Q component, The spread code is configured by either a circuit that outputs the -I component or the -Q component, or a circuit that outputs the Q component or the -I component with respect to the input I component or Q component, respectively. 30. The despreading demodulation circuit according to claim 29, wherein the circuit to be adopted is determined according to 32. The first to M-th phase rotation circuits are values corresponding to the amount of phase rotation generated when the spreading code is narrow-band frequency shift keyed on the transmitting side or the amount of phase rotation canceling the phase rotation. A two-bit register into which is written, first and second inverting circuits that sign-invert the input I and Q components, the I and Q components as selection values, and the first And the -I component and the -Q component whose sign is inverted by the second inverting circuit are input, and the selected value is selected according to the value written in the register to reverse the value in π / 2 units. A first selection circuit that outputs a rotated I component, the I component and the Q component as selection values are input, and the signs are inverted by the first and second inversion circuits. I component and -Q component are input , A second selection circuit for outputting the Q component which is inversely rotated by π / 2 unit by selecting the selection value according to the value written in the register. Claim 29
The despreading demodulation circuit according to 1. 33. A spread code according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, claim 9 or claim 10. A receiving apparatus, comprising a detection circuit, for detecting a spread code from a transmission signal transmitted by a communication method combining a narrow band frequency shift keying method and a spread spectrum method. 34. The above-mentioned claim 11, claim 12, claim 1
3, claim 14, claim 15, claim 16, claim 1
7, claim 18, claim 19, claim 20, claim 2
1, claim 22, claim 23, claim 24, claim 2
5, claim 26, claim 27, claim 28, claim 2
9. A transmission signal transmitted by a communication system comprising a despread demodulation circuit according to claim 30, claim 31, claim 32 or claim 32, which is a combination of a narrow band frequency shift keying system and a spread spectrum system. A receiving apparatus which demodulates transmitted information data by performing despreading and narrow band frequency shift keying modulation.