JP2964196B2 - Digital quadrature detection demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital quadrature detection demodulator for demodulating a modulated wave signal for transmitting information by phase, amplitude, or both, and more particularly to a digital quadrature detection demodulator comprising an n-phase phase modulated wave or an amplitude modulated wave. The present invention relates to a digital quadrature detection demodulator that obtains a quadrature amplitude output or a phase output by correcting data obtained by directly sampling an intermediate frequency signal.

2. Description of the Related Art When data is transmitted by an electric signal or an optical signal, a method of transmitting a signal whose phase and / or amplitude is modulated by information, and detecting and demodulating the signal at a receiving side to reproduce the original information. , Is commonly used.

In such a demodulation demodulator for demodulating a modulated wave signal transmitting information by phase, amplitude or both, a necessary correction is made to data obtained by directly sampling the modulated wave signal. In addition, it is desired that orthogonal amplitude or phase outputs be obtained.

[0004]

2. Description of the Related Art FIG. 24 shows an example of a conventional detection demodulator. Reference numerals 11 and 12 denote mixers, reference numeral 13 denotes a local oscillator, reference numeral 14 denotes a 90 ° hybrid, reference numerals 15 and 16 denote low-pass filters (LPF), and reference numeral 17. , 18 are analog-to-digital converters (A / D), 19 is a detector, 20 is a bit timing recovery circuit (BTR), 21 is a clock generator, 2
Reference numeral 2 denotes an automatic frequency control unit (AFC). Name of each part below
The names are described using abbreviations in parentheses.

The mixers 11 and 12 receive an intermediate frequency (IF) signal (carrier frequency f _c, phase φ) at one input, and receive a local signal (frequency f _l ) of the local oscillator 13 at the other input. , 90.degree., The signals having phases shifted so as to be orthogonal to each other are added to each other, thereby generating a signal having the sum and difference frequencies of the two signals. The LPFs 15 and 16 remove the frequency components of the sum. Therefore, cos ｛2 consisting of the difference frequency components
_{π (f c -f l) +} φ}, sin {2π (f c -f l)
+ Φ} is output from LPFs 15 and 16 as a baseband signal.

[0006] The A / Ds 17 and 18 convert orthogonal baseband signal components composed of analog signals from the LPFs 15 and 16 into digital signals according to the clock from the BTR 20 and input the digital signals to the detector 19. The detection unit 19 performs required detection and demodulation processing such as synchronous detection and delay detection on both signal components, and restores the data string DATA transmitted by the IF signal.

The BTR 20 has a phase locked loop (PLL), divides the frequency of the clock from the clock generator 21, and
A clock synchronized with the data sequence from the detector 19 is generated and supplied to the A / Ds 17 and 18. The AFC 22 performs, for example, automatic frequency control of the clock generator 21 in synchronization with the data sequence from the detector 19,
9, the clock frequency of the clock generator 21 is synchronized with the data string. Note that the AFC 22 may be used for other purposes. A / D17,18 are BT
The conversion operation is performed only at the data points by the clock from R20, thereby reducing the current consumption.

[0008]

In the conventional demodulator shown in FIG. 24, the mixers 11, 12, LPF1
5, 16, 90 ° hybrid 14, local oscillator 1
3 is an analog circuit, each element is large,
Not only is it disadvantageous in reducing the circuit scale, it is difficult to adjust, and there is a problem in stability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a detector and demodulator for demodulating a modulated wave signal transmitting information by phase, amplitude or both. By directly sampling the modulated wave signal and extracting the quadrature detection component, it can be configured with a digital circuit,
Accordingly, it is an object of the present invention to provide a digital quadrature detection demodulator capable of reducing the circuit scale.

[0010]

SUMMARY OF THE INVENTION The digital quadrature of the present invention
Detector demodulator (1) a digital quadrature detection demodulator for demodulating a modulated wave to transmit any information by one or both of the carrier phase and amplitude of the frequency f _c, the modulated wave with the same period Sampling is performed by sampling clocks f _sa and f _{sb having} different phases and sample values S _a and
sampling means 2 and 3 for outputting _b, and conversion means 4 for outputting two orthogonal components I and Q of the modulated wave from the sample values S _a and S _b by the sampling means 2 and 3.
(5) and provided with, this conversion means, the sampling clock f _sa, as the deviation angle from the phase quadrature relation of f _sb theta, the conversion of _{I = S b Q = S a} / cosθ-S b tanθ And outputs two orthogonal components I and Q.

[0011] The present invention is, (2) the frequency f _c of the carrier wave
Transmits information by phase and / or amplitude
Digital quadrature detection demodulator that demodulates modulated waves
To modulate the modulated waves with the same
Sampled by sampling f _sa and f _sb
Sampling means for outputting S _a, S _b, the sump
Sample values S _a by ring means, and S _b, the sump
Deviation of the phases of the ring clocks f _sa and f _sb from the orthogonal relationship
A conversion means for performing a conversion of φ = arctan {S _a / (S _b cos θ) -tan θ} by using the angle θ to obtain a phase φ of the modulated wave.
Have.

The present invention also provides (3) two orthogonal components I and Q
Or a conversion means for obtaining the phase φ of the modulated wave
Regenerate the clock based on the output of the
Bit timing reproduction circuit for generating locks f _sa and f _sb
And, the recovered clock from the bit timing re-live circuit
The sampling means or
Is provided with correction means for correcting the output phase of the conversion means.
be able to.

The present invention also provides (4) bit timing reproduction
Integrates the advance and delay of the phase of the reproduced clock of the circuit and
It is possible to provide an integrating means for performing correction in the correct means.
it can.

The present invention also provides (5) a master clock
To generate the sampling clocks f _sa and f _sb
Both the carrier frequency f _c and frequency of the master clock
The sampling means or the variable according to the difference from the number.
Correction means for correcting the phase of the output of the conversion means may be provided.
it can.

[0015]

In the present invention, the input modulated wave signal is
Sampling at the timing, cos component of quadrature detection
And to extract what is equivalent to the sin component,
Hereinafter, the principle operation of the present invention will be described with reference to FIGS.
I will tell.

FIG . 1 shows the principle configuration of the present invention.
(A) is a structure for demodulating the amplitude S of the modulated wave.
(B) is a field for demodulating orthogonal two components I and Q of a modulated wave.
(C) is the configuration when demodulating the phase φ of the modulated wave
Are respectively shown.

As shown in FIG .
Recovers signals with modulation schemes that include information in width or both.
Of the most basic digital quadrature detection demodulator
To the modulated wave of the carrier frequency f _c, the sampling circuit
Sample at the frequency f _s to obtain the amplitude S of the modulated wave directly
So that

FIG . 2 shows the frequency conversion by the sampling method.
It is for explanation. Now, the IF signal of frequency f _c,
When the sample at a certain frequency f _s, the sampling output
, As shown in FIG. _{2, f d = | f s} -f c | becomes
Frequency components appear.

Carrier frequency f _c, carrier phase
When φ, the IF signal is expressed as follows. as the sample in the _{cos (2πf c t + φ)} ... This frequency f _s, replacement write the formula
Obtain _{the, cos (2πf c t + φ} ) = cos {2π (f s + f d) t + φ} _{However, f d = f c -f s} f c / 2 <f s <2 * f c

[0020] The sample to period is met T _s = 1 / f _s
Te, the timing of _{t = t s * k = k} / f s (k is self
Number). Substituting this into _{equation, cos {2π (f s +} f d) t s * k + φ} = cos {2π (f s + f d) k / f s + φ} = cos {2πk (1 + f d / f s) + φ} …

Since k is a natural number, in the above equation, the triangle
The first term 1 in the function cos can be eliminated.
And the equation can be expressed as: When expressed as a function of _{cos (2πkf d / f s +} φ) ... This again _{t, cos (2πf d t +} φ) ... to become.

As is apparent from the equation, the IF signal cos
Obtained when samples with (2πf _c t + φ) the frequency f _s
Frequency f _d to be is, of the original carrier frequency f _c phase
Has the information φ as it is. Conversely, the frequency component
By knowing the phase of the minute f _d , the original IF signal f _c
Can be known.

Also, as shown in FIG.
Is a modulation signal whose amplitude or both contain information.
In a digital quadrature detection demodulator that demodulates
Sample modulated waves with two clocks with the same phase but different phases
And convert it from the sample values obtained.
Thus, two orthogonal components of the modulated wave can be obtained.

As information indicating the phase, two orthogonal
An amplitude component is required. Therefore, the frequency that is the modulated wave
The IF signal f _c, the same cycle 2 different phases Tsunoku
_Sampled and obtained according to the timing of the lock f _sa, f _sb
Are sample values S _a, from S _b, two orthogonal configuration of modulated waves
Min I and Q can be obtained.

Further, a conversion means is provided, and the carrier frequency f
Sampling clock f _sa, f _sb for the modulated wave of _C
Is obtained when the phase of
From the pull values S _{a and} S _b , I = S _b , Q = S _a / cos θ−
By performing the conversion of S _b tan θ, the orthogonal
Two components can be obtained.

FIG . 3 shows the sample timing and the position of the modulated wave.
(A) is a carrier frequency.
The relationship between the modulated wave of f _C and the sampling clocks f _{sa and} f _sb
(However, the phase relationship between the modulated wave and the sampling clock
Indicates a summary and is not an exact representation)
(b) shows the sample values S _{a and} S _b in this case on the phase plane.
Is shown. Also, FIG.
This is for explaining the derivation of the amplitude and the phase.

Both sample values S _a, S _b on the phase plane
The deviation angle θ from the orthogonality, modulated wave f _c and the sampling
It can be obtained from the phase difference (time difference) between the clocks f _{sa and} f _sb.
Can be. Now, the sampling clock f _sa, to f _sb
The sampling timing is set to t _{sa and} t _sb ,
If the time difference is Δt, the sampled data is
_{Is, S a = cos (2πf c} t sa + φ) ... S b = cos (2πf c t sb + φ) = cos {2πf c (t sa + Δt) + φ} = cos (2πf c t sa + 2πf c Δt + φ) ... and Therefore, the phase difference between the sample values S _{a and} S _b is θ ′ = 2
πfc _c Δt. Therefore the sample value S _a, orthogonal functions of S _b
The deviation θ from the engagement is as follows. θ = π / 2−θ ′ = π / 2−2πf _c Δt

The sample values S _a,
And a S _b and the phase difference theta, in the sample value S _a or S _b
Two orthogonal amplitude components based on phase
Can be sought. Here, the reference sample value S _b is
When both the amplitude component becomes _{I = S b Q = S a} / cosθ-S b tanθ.

FIG . 5 shows a phase plane when the phase relationship is different.
And each symbol is the same as in FIG.
The amplitude components I and Q and the phase angle θ are obtained in the same manner.
Can be

[0030] In addition the carrier frequency f _c of the modulated wave, San
The time difference Δt between the pulling clocks f _{sb and} f _sb is Δt =
(1 / 4fc) × (1 + 4n) (n is a natural number) or Δ
t = (1 / 4fc) × (3 + 4n)
By doing, I = _Sb , Q = _Sa or I = −
Assuming that S _b and Q = S _a , the circuit configuration can be simplified.
Wear.

[0031] and the frequency f _c of the modulated wave, sampling Black
The time difference Δt between the _locks f _{sa and} f _sb is Δt = (1 / 4fc)
× (1 + 4n) (n is a natural number)
The pull values S _{a and} S _b directly represent the amplitude of the orthogonal component.

This corresponds to the phase plane shown in FIG.
Therefore, it is equal when θ = 0. That is, in this case, 2π
is a f _c Δt = π / 2. This can be expressed as
_{Substituting, S a = cos (2πf c} t sa + φ) S b = cos (2πf c t sb + φ) = cos {2πf c (t sa + Δt) + φ} = cos {2πf c t sa + (π / 2) _{+ φ} = sin (2πf c} t sa + φ} Therefore _{I = S b, Q = S} a is obtained.

Similarly, the frequency f _{c of the} modulated wave and the sampler
The time difference Δt between the _switching clocks f _{sa and} f _sb is Δt = (1 /
4fc) × (3 + 4n) (n is a natural number)
The sample values S _{a and} S _b are equal to the state of θ = π
By inverting the sign of I, the orthogonal components I and Q
Can be requested. That is, I = −S _b , Q = S _a

Also, as shown in FIG.
A modulation scheme that contains information in its amplitude or both.
Modulation in a digital quadrature detection demodulator
Two clocks with the same period but different phases for the waves
f _sa, f _sb , and sampled values S _a, S
_{From b} , by performing a conversion represented by φ = arctan {S _a / (S _b cos θ) −tan θ} , the phase φ of the modulated wave is changed.
To get.

[0035] In other words, the change relative to the sample value S _b
The phase phi harmonic f _c, with reference to FIG. 4, since it is tanφ = OQ / OI = (OP / cosθ-OItanθ) / OI = OP / (OIcosθ) -tanθ, φ = arctan {S a / (S _b cosθ) -tanθ} ... it can be calculated as.

[0036] In addition, the carrier frequency f _c of the modulated wave, the difference
Time difference Δt due to the phases of the sampling clocks f _{sa and} f _sb
Is Δt = (1 / 4fc) × (1 + 4n) (n is natural
Number) or Δt = (1 / 4fc) × of (3 + 4n) relationship
By making φ = arctan (S _a / S _b )
Or, as φ = −arctan (S _a / S _b ),
The road configuration can be simplified.

In this case, Δt = (1 / 4fc) × (1
+ 4n), θ = 0 and Δt = (1 / 4fc)
In the case of × (3 + 4n), θ = π, so the above equation
Thus, when the phase angle θ = 0, φ = arctan (S
_a / S _b) next, when the phase angle θ = π, φ = -arc
tan (S _a / S _b ).

Further , in a digital quadrature detection demodulator,
And the clock f _s for sampling the modulated wave , or
Clocks for creating sampling clocks f _{sa and} f _sb
A clock generator for the sample is provided.
It can be supplied from.

The clock f _s for sampling the modulated wave ,
_{Alternatively} , create the sampling clocks f _{sa and} f _sb
Clock from the sample clock generator
By setting the sampling clock to any frequency
Can be selected.

Also, in a digital quadrature detection demodulator,
And the clock f _s for sampling the modulated wave , or
Clocks for creating sampling clocks f _{sa and} f _sb
Clock for processing the baseband signal.
By the dividing click f _m, it can be created
You.

The clock f _s for sampling the modulated wave ,
_{Alternatively} , create the sampling clocks f _{sa and} f _sb
Clock for processing the baseband signal,
Create a clock f _m from the master clock generator by dividing
Can be achieved. This eliminates the need for one oscillator
It is possible to reduce the hardware scale
Become.

In the digital quadrature detection demodulator,
And the clock f _s for sampling the modulated wave , or
Clocks for creating sampling clocks f _{sa and} f _sb
Extract the bit timing of the transmission signal
Playback clock from BTR (bit timing playback circuit)
Use a lock.

The clock f _s for sampling the modulated wave ,
_{Alternatively} , create the sampling clocks f _{sa and} f _sb
The bit timing of the transmission signal as a clock for
You can use the recovered clock from the BTR
You. This eliminates the oscillator and reduces the hardware scale
A / D for reducing the input signal and A / D converting the input signal
The operating speed of the converter can be reduced.

In the digital detection demodulator, B
Based on the jitter of the recovered clock from TR,
The fluctuation of the sample point with respect to the
The phase change is determined by the product of the demodulation phase and the shift of the sample point.
Correction according to the minute value allows correct phase
A demodulated output can be obtained.

FIG . 6 shows the phase of the sample point due to the jitter.
(A) explains the change and the method of correcting the change.
The change in the phase of the sample point due to jitter is shown.
Shows the correct method.

Using the clock recovered by the BTR
When the sampling clocks f _{sa and} f _sb are created,
BTR takes data at the center of the eye pattern
It always works, so it always has jitter. So
_Therefore , sampling clocks f _{sa and} f _sb also have jitter.
The phase of the sampled point is the unit of jitter resolution
To change. The phase change due to jitter in this case is
Become like

Now, at the sample timing from the BTR,
Assuming that the time variation based on the jitter is ± t _j ,
S is the phase of the sample point when there is no
Therefore, if the phase of the changed sample point is S ′, Becomes Where k is the sample integrated from the initial state
The movement amount of the point is shown.

[0048] and the carrier frequency f _c of the modulated wave, sample
Since the time change of the timing ± t _j is known, the phase of S ′
By subtracting ± 2πf _c kt _j from
As a result, a demodulated output having a correct phase can be obtained.

FIG . 7 is a circuit for correcting a phase change due to jitter.
30 indicates the phase correction of the demodulated data.
This is a phase correction unit that performs. In BTR31, the clock
The advance / delay determining unit 32 determines whether the clock is advanced by jitter,
The delay is determined and the up / down (U / D) counter 33
Is counted up by the determined advance and delay
The sample timing by counting down
Integrate the time change of the data. The correction data selection unit 34
Demodulated data based on the integration result of U / D counter 33
The correction data for performing the phase correction is selected. Taimi
The tuning adjustment delay unit 35 is based on the selected correction data.
And controls the phase correction unit 30 so that the phase correction unit
At 30, the phase correction of the data was performed,
Demodulated data is output.

In the digital quadrature detection demodulator,
In particular, when delay detection is used, reproduction from the BTR
Samples a modulated wave based on clock jitter
Variation of the point changes the phase of the demodulated signal
However, the correction according to the difference from the previous sample value
Correct phase demodulation output by adding to demodulation phase
Can be obtained.

FIG . 8 illustrates a correction method in the case of differential detection.
Is what you do. With respect to the carrier frequency f _c of the modulated wave
And sample clocks f _sa, f having a phase difference of 90 °
By sample I by the _sb, detection demodulation is performed
However, the sampling clock is set based on the operation of the BTR.
Click f _sa, the f _sb, phase advance as _shown, delayed raw
This also changes the phase of the sampled data.
You.

At this time, a phase change occurs in the sampling clock.
Occurs, the phase of the sample data is correspondingly
By changing, the same phase as the previous data
Therefore, the differential detection result is always 0.

FIG . 9 is a circuit for correcting a phase change during delay detection.
Which is the same as in FIG.
The numbers are shown. At the time of differential detection, 1
It is only necessary to correct the change from the phase of the previous data
Eliminates the need for a U / D counter for performing the integration operation
Other than that, the operation is the same as that of FIG.

In the digital quadrature detection demodulator,
Te, master carrier frequency f _c and the baseband signal
Not synchronized because of the frequency difference to the clock f _m
The demodulated signal is
Signal by correcting for the frequency difference.
A new phase can be obtained.

[0055] Master for modulation wave f _c and the baseband signal
Because of the frequency difference to the clock f _m, Masutakuro'
When samples obtained clock f _s by dividing the click,
Perform sampling at the same timing for modulated waves.
Therefore, the phase of the demodulated signal gradually changes.

In this case, the phase shift is the n-th time
And ring the _{t sn = (1 / f s} ) × n (n is a natural number)
When the sample value and each _{S 1 = 2πf c t s1 +} φ = 2πf c / t s + φ S 2 = 2πf c t s2 + φ = (2πf c / t s) × 2 + φ: S n = 2πf c t sn + φ = ( the _{2πf c / t s) × n} + φ.

[0057] Since the carrier frequency f _c is known, sump
Complement subtracting Le value S _n of phases _{(2πf c / t s) ×} n
By performing the correction, a correct demodulation phase can be obtained.
This is to correct the frequency difference that occurs in the circuit configuration,
Frequency stability and Doppler shift of local oscillator for transmission and reception
It does not compensate for the frequency difference due to. The latter correction
Can be performed by the AFC shown in FIG. 24, for example.
You.

FIG . 10 shows a phase correction circuit for a frequency difference.
Which is the same as in FIG.
The numbers are shown. In this case, the counter 36
The frequency difference is counted, and the
Timing adjustment using the correction data corresponding to the
When the delay unit 35 controls the phase correction unit 30,
Performs phase correction on the demodulated data, and
Output data.

In the digital quadrature detection demodulator,
Te, master carrier frequency f _c and the baseband signal
Not synchronized because of the frequency difference to the clock f _m
Based on the frequency
If the difference is small, pull in the frequency with AFC.
And a demodulated signal with the correct phase can be obtained.
You.

[0060] for the carrier frequency f _c and a baseband signal
Small frequency difference between the master clock f _m of, particular problem
If not, the AFC is performed based on the demodulated output signal.
Thus, during the carrier frequency f _c and a baseband signal
It is drawn the frequency difference between static clock f _m
Wear.

Further , in a digital quadrature detection demodulator,
Te, master carrier frequency f _c and the baseband signal
Not synchronized because of the frequency difference to the clock f _m
Is particularly slow for phase shifts of sample values.
In the case of postponed detection, the compensation according to the difference from the previous sample value
Correct phase demodulation by adding positive to demodulation phase
You can get the output.

In the case of delay detection, the phase of the immediately preceding data
It is only necessary to correct only the difference between. Previous one due to frequency difference
The difference between the phase of the data is always a 2 [pi] f _c / f _s
Since it is constant, it can be corrected with a fixed correction value.
The integration section as shown in FIG. 7 is unnecessary.

FIG . 11 is a diagram showing the position due to the frequency difference at the time of differential detection.
FIG. 10 shows a phase correction circuit, the same as in FIG.
The same items are indicated by the same numbers. In this case, the correction data
The constant correction data in the
The delay adjustment unit 35 controls the phase correction unit 30.
Performs phase correction on demodulated data that has been delayed detected.
Thus, the corrected data is output.

Further , information on the phase and / or the amplitude is given.
Detection that demodulates the signal of the modulation method including the information
In the demodulator, the modulation wave frequency f _c, the baseband signal
A master clock f _m for issue _{is, f m = (f c /} 4)
(1 + 2n) * k (k is a natural number)
Can always obtain a demodulated output with the correct phase.
You.

[0065] and the carrier frequency f _c of the modulated wave, baseband
And a master clock f _m for command signals, f _m = (f _c /
4) When (1 + 2n) * k (k is a natural number)
Is always a modulation wave frequency f _c, the master clock f _m is
Synchronization eliminates the need for a phase correction circuit,
Configuration is easier.

[0066]

FIG . 12 shows a main part of an embodiment (1) of the present invention.
41 is an analog-to-digital converter
(A / D). As described above, the A / D 41 is
An input IF signal consisting of the modulated wave of the rear frequency f _c, A /
And sampled at the frequency f _s in D41, the modulation wave
By extracting the sample values of the amplitude demodulation output
By obtaining S, frequency conversion by analog signal
It is not needed.

FIG . 13 shows an embodiment (2) of the present invention.
42 and 43 are analog-to-digital converters
(A / D), 44 converts the sample value to a quadrature demodulated output
Converter.

The operation has been described with reference to FIG .
A, A / D42,43, the modulation wave of the carrier frequency f _c
The input IF signal composed of the sampling clock f _sa,
Generate sample values S _{a and} S _b by sampling with f _sb
And, the transducer 44 may be converted sample values S _a, the S _b
Demodulates and outputs two orthogonal components I and Q of the modulated wave.
Power.

FIG . 14 shows a modification of the embodiment (2).
45, an analog / digital converter (A /
D), 46 is an OR circuit (OR), 47, 48 are flips
The flop (FF).

In FIG . 14, A / D 45 is a carrier.
An input IF signal composed of the modulation wave frequency f _c, the OR circuit
Sampling clocks f _sa, f
_{By sb} , sample in time division and output sample value
The FFs 47 and 48 provide sampling clocks f _{sa and} f
_sb , the sampled value is latched, and the sampled value S is latched.
_a, to output the S _b in two orthogonal components I of the modulated wave, as Q
You.

According to the embodiment of FIG . 14, one analog
Sampling is performed using a digital converter in a time-sharing manner.
Because of this, the circuit scale can be reduced.

FIG . 15 shows another modification of the embodiment (2).
The same items as those in FIG.
, 65 reproduces bit timing from demodulated output
Bit timing reproduction circuit (BTR) 66
It is a do-only memory (ROM) .

As described with reference to FIGS. 6 and 7,
The sampling clock f _sa, which samples the modulated wave _,
As a clock for generating _fsb , the bit of the transmission signal is used.
BTR (bit timing
Playback clock from the BTR
Based on the jitter of the recovered clock,
Changes in the phase of the demodulated signal due to fluctuations in the sample points
And a converter that outputs a value corresponding to the shift of the sample point.
By providing them, quadrature demodulation outputs I and Q having correct phases are provided.
Can be obtained. Note that the phase φ is output as the demodulated output.
You can force it.

In this case, the sample value S
_a, and S _b, the difference from the carrier frequency f _c and BTR65
From the phase shift with the sampling clock.
A ROM 66 for generating tone data can be used.

FIG . 16 shows an embodiment (3) of the present invention.
And the same as in FIGS. 13 and 14.
Are indicated by the same numbers.

[0076] As described above, the modulation of the carrier frequency f _c
Sampling clock for input IF signal
If the phases of f f _and f _sb deviate from the orthogonality by an angle θ
The A / D 45 receives the input IF signal via the OR circuit 46.
And it is given by the sampling clock f _sa, depending on the f _sb
Sampled in a time-division manner and output a sampled value,
47 and 48, depending on the sampling clock f _sa, f _sb
Te, the sample value is latched, out sample value S _a, the S _b
Power. Converter 44, the sample value S _a, from S _b, I =
S _b, the conversion of _{Q = S a / cosθ-S} b tanθ
Demodulation output consisting of two orthogonal components
I and Q can be obtained.

FIG . 17 shows an embodiment (4) of the present invention.
And the same numbers as in FIG.
Is shown.

As described with reference to FIG .
To the input IF signal composed of the modulation wave frequency f _c, Sa
The time difference Δt between the sampling clocks f _{sa and} f _sb is Δt =
(1 / 4fc) × (1 + 4n) (n is a natural number) or Δ
When there is a relationship of t = (1 / 4fc) × (3 + 4n),
The A / D 45 converts the input IF signal via the OR circuit 46
Is given, the sampling clock f _sa, depending on the f _sb
Sampled in a time-division manner and output a sampled value,
47 and 48, depending on the sampling clock f _sa, f _sb
The sample value by latching the sample value.
S _a, and outputs a S _b, transducer 44, the sample value S _a, S _{b
From, I = S b, Q =} S a or _{I = -S b, Q = S} a
, And consists of two orthogonal components
A demodulated output can be obtained.

FIG . 18 shows an embodiment (5) of the present invention.
And the same numbers as in FIG.
And 49 is a conversion for converting the sample value to the phase of the modulated wave.
It is a vessel.

As described with reference to FIG .
D45 gives an input IF signal via an OR circuit 46
Sampling clocks with the same period and different phases
f _sa, by f _sb, time division manner sample to sample
FF47, 48 output the sampling clock
By latching the sample value according to f _{sa and} f _sb
Thus , the converter 49 outputs sample values S _{a and} S _b , and the converter 49
From the sample values S _{a and} S _b , φ = arctan ｛S _a / (S
_b cosθ) -tanθ｝
And outputs the phase φ of the modulated wave.

FIG . 19 shows an embodiment (6) of the present invention.
And the same numbers as in FIG. 18 have the same numbers.
Is shown.

[0082] As described above, the modulation of the carrier frequency f _c
Sampling clock for input IF signal
The time difference Δt between f _{sa and} f _sb is Δt = (1 / 4fc) ×
(1 + 4n) (n is a natural number) or Δt = (1 / 4fc)
) × (3 + 4n), A / D 45 is
The input IF signal is sampled via the OR circuit 46.
Lock f _sa, by f _sb, time division manner sample to support
FF47 and 48 output sampling values.
The sample value can be latched according to the locks f _{sa and} f _sb .
And the sample values S _a, the S _b output transducer 49
Is, from the sample values S _{a and} S _b , φ = arctan (S _a
/ S _b ) or φ = -arctan (S _a / S _b )
And outputs the phase φ of the modulated wave.

FIG . 20 shows an embodiment (7) of the present invention.
And the same numbers as in FIG.
51 is a read only memory (ROM), and 52 is a read only memory (ROM).
Clock generator, 53 is BTR, 54 is up / down
(U / D) counter, 55 is a jitter phase correction data part,
56 is an adder, 57 is a counter, and 58 is a frequency difference correction data.
Data unit, 59 is an addition unit, and 60 is an AFC.

As described with reference to FIG .
D45 is, change by sampling the IF signal of frequency f _c
Obtain a sample value of the amplitude of the harmonic. At this time, OR circuit 4
Sampling clock f _sa given from _6, time is f _sb
A / D45 is shared and time sharing
Use in. And, by FF47,48, sample
Data sampled by the clocks f _{sa and} f _sb
Each sample value S _a, it separated into S _b.

As described with reference to FIG.
The sample value S _a indicating the amplitude _change, type S _b, R
The signal is converted into the phase φ by the converter composed of the OM 51.

As described above, the sampling clock
f _sa, the f _sb, and the master clock of the baseband signal
The timing signal from the BTR 53 is used. Black
The clock generator 52 supplies a clock to the BTR 53.

As described above, the BTR
Based on the operation of 53, the sample point is shifted.
When the demodulation phase changes, the U / D counter 54
And a sampling timer based on jitter in the BTR 53.
Integrates the time change of the imaging and corrects the jitter phase correction data.
At 55, based on the integration result,
The correction data for performing the phase correction is selected, and
, The selected correction data is output to the ROM 51
Addition compensates for phase changes due to jitter.
You.

Alternatively , as described as an action,
Peripheral to the master clock for the rear frequency f _c and a baseband
Phase shift occurs in sample data due to wave number difference
When changing the frequency, the frequency difference is integrated by the counter 57,
In the frequency difference correction data section 58, based on this integration result,
Correction data for performing phase correction of demodulated data
Is selected in the adder 59, and the selected correction data
Is added to the output of the ROM 51 to obtain the frequency difference.
The phase change due to

Alternatively , as described with reference to FIG.
, The master carrier frequency f _c and the baseband signal
When the frequency difference from the clock is small, AFC60
By subtracting this frequency difference, the correct phase
To obtain a demodulated signal.

In the embodiment shown in FIG.
Instead of obtaining the output of phase φ from 1, two orthogonal components
I and Q are output, and the BTR 53 is advanced or delayed.
The correction based on the frequency difference and the correction based on the frequency difference
It may be performed for each of the components I and Q.

FIG . 21 shows an embodiment (8) of the present invention.
And the same as in FIG. 20 with the same numbers
Numeral 61 indicates a delay circuit (D), and numeral 62 indicates an adder.

The operation will be described with reference to FIGS.
As mentioned, the jitter of the recovered clock from the BTR
Therefore, when the phase of the demodulated signal changes, delay detection is used.
The phase of the previous data based on the jitter
Only in prayer yo if the correction of the amount of change, put to BTR53
Product the time change of sampling timing due to
Without separating it into the jitter phase correction data part 55
Selects correction data for performing phase correction of demodulated data
Then, in the adding section 56, the selected correction data is
By adding to the output of M51,
Compensate for phase change.

The operation has been described with reference to FIG.
Sea urchin, the mass of the carrier frequency f _c and a baseband signal
Based on the fact that there is a frequency difference and Takurokku f _s, San
When there is a phase shift of the pull value, one for delay detection
It is only necessary to correct the difference from the phase of the previous data.
The difference from the previous data phase due to the number difference is always 2π
Since constant a f _c / f _s, the constant correction value
Since the correction may be performed, the adder 59 corrects the frequency difference.
Addition of certain correction data in the positive data section 58
And the complement of the delayed demodulated data by
Perform the correction and output the corrected data. Due to jitter
When the phase change is not corrected, the delay
Adder 62 adds the frequency difference correction data
To generate a phase-corrected output.

In the embodiment shown in FIG.
Instead of obtaining the output of phase φ from 1, two orthogonal components
I and Q are output, and the BTR 53 is advanced or delayed.
The correction based on the frequency difference and the correction based on the frequency difference
It may be performed for each of the components I and Q.

FIG . 22 shows an embodiment (9) of the present invention.
And the same numbers as in FIG.
Is shown.

The operation has been described with reference to FIG.
As the carrier frequency f _c of the modulated wave, sampling
The time difference Δt due to the phases of the clocks f _{sa and} f _sb is represented by Δt =
(1 / 4fc) × (1 + 4n) (n is a natural number) or Δ
t = (1 / 4fc) × (3 + 4n), φ =
arctan (S _a / S _b ) or φ = −arc a
n (S _a / S _b ) and the phase change φ from the ROM 51
The circuit configuration can be simplified by outputting
You.

Further , as described above,
And carrier frequency f _c of the modulated wave, the baseband signal
A master clock f _{m is, f m = (f c /} 4) (1 + 2
n) * k (k is a natural number)
And the wave number f _c, and the master clock f _m is always synchronized
Therefore, a phase correction circuit is not required, and the circuit configuration is simplified.
You.

In the embodiment shown in FIG.
Instead of obtaining the output of phase φ from 1, two orthogonal components
I and Q are output, and the BTR 53 is advanced or delayed.
Correction based on the two orthogonal components I and Q, respectively.
It may be performed.

FIG . 23 shows an embodiment (10) of the present invention.
And the same numbers as those in FIG. 20 have the same numbers.
Where 63 is a clock generator for sampling and 64 is a clock generator.
This is a frequency divider for dividing the clock of the lock generator 63.

As described above, the modulation
_Create sampling clocks f _{sa and} f _sb for sampling waves
Clock generator for sample generation
63 and a frequency divider 64 to supply
The sampling clock to an arbitrary frequency.
Can be specified.

In the embodiment shown in FIG.
Instead of obtaining the output of phase φ from 1, two orthogonal components
I and Q are output, and the BTR 53 is advanced or delayed.
The correction based on the frequency difference and the correction based on the frequency difference
It may be performed for each of the components I and Q.

[0102]

As described above, according to the present invention,
Modulation method with information in phase and / or amplitude
Digital demodulation demodulator for demodulating digital signals
Data obtained by directly sampling the input modulated wave signal
The deviation of the sampling clock phase from the orthogonal relationship
The orthogonal processing is performed by the conversion processing in which the necessary correction is added based on the angle θ.
Can output two components I and Q.
It can be downsized by being configured with digital circuits.
Stable and accurate demodulation operation
Can be made possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention, wherein (a) is a configuration for demodulating an amplitude S of a modulated wave, and (b) is a component for demodulating orthogonal two components I and Q of the modulated wave. (C) shows the configuration for demodulating the phase φ of the modulated wave.

FIG. 2 is a diagram illustrating frequency conversion by a sampling method.

FIG. 3 is a diagram showing a sample timing and a phase plane of a modulated wave.

FIG. 4 is a diagram illustrating derivation of a quadrature amplitude and a phase on a phase plane.

FIG. 5 is a diagram showing a phase plane when the phase relationship is different.

FIG. 6 is a diagram illustrating a change in phase of a sample point due to jitter and a method of correcting the change.

FIG. 7 is a diagram showing a circuit for correcting a phase change due to jitter.

FIG. 8 is a diagram illustrating a correction method in the case of differential detection.

FIG. 9 is a diagram showing a circuit for correcting a phase change during delay detection.

FIG. 10 is a diagram showing a phase correction circuit for a frequency difference.

FIG. 11 is a diagram illustrating a phase correction circuit based on a frequency difference during delay detection.

FIG. 12 is a diagram showing an embodiment (1) of the present invention.

FIG. 13 is a diagram showing an embodiment (2) of the present invention.

FIG. 14 is a view showing a modification of the embodiment (2).

FIG. 15 is a diagram showing another modification of the embodiment (2).

FIG. 16 is a diagram showing an embodiment (3) of the present invention.

FIG. 17 is a diagram showing an embodiment (4) of the present invention.

FIG. 18 is a diagram showing an embodiment (5) of the present invention.

FIG. 19 is a diagram showing an embodiment (6) of the present invention.

FIG. 20 is a diagram showing an embodiment (7) of the present invention.

FIG. 21 is a diagram showing an embodiment (8) of the present invention.

FIG. 22 is a diagram showing an embodiment (9) of the present invention.

FIG. 23 is a diagram showing an embodiment (10) of the present invention.

FIG. 24 is a diagram illustrating a conventional detection and demodulator.

[Explanation of symbols]

 Reference Signs List 1 sampling means 2 sampling means 3 sampling means 4 conversion means 5 conversion means 6 BTR 7 correction means 8 integration means 9 correction means 10 integration means

Continuation of the front page (56) References JP-A-3-89651 (JP, A) JP-A-1-256253 (JP, A) JP-A-62-178046 (JP, A) JP-A-60-46157 (JP) , A) JP-A-62-280547 (JP, A) JP-A-5-136837 (JP, A) JP-A-5-260107 (JP, A) Proceedings of the 1992 IEICE Spring Conference, Volume 2 , P. 2-343 1992 IEICE Autumn Conference Proceedings, Supplement, Vol. 2-247 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 27/00-27/38

Claims (5)

(57) [Claims] [Claim 1] What the phase and amplitude of the carrier frequency f _c
Demodulate modulated waves that transmit information by one or both
In a digital quadrature detection demodulator, the modulated waves are sampled at the same period and with different phases.
Sampled by sampling f _sa and f _sb
Sampling means for outputting S _a and S _b , and sampling values S _a and S _b from the sampling means
Conversion means for outputting two orthogonal components I and Q of the modulated wave;
And the conversion means is configured to generate the sampling clocks f _sa and f _sb .
Assuming that the angle of deviation of the phase from the orthogonal relationship is θ, a configuration in which I = S _b Q = S _a / cos θ−S _b tan θ is converted and two orthogonal components I and Q are output.
Digital quadrature detection demodulator characterized by comprising. Wherein any phase and amplitude of the carrier frequency f _c
Demodulate modulated waves that transmit information by one or both
In a digital quadrature detection demodulator, the modulated waves are sampled at the same period and with different phases.
Sampled by sampling f _sa and f _sb
S _a, sampling means for outputting the S _b, the sample value S _a by said sampling means, and S _b, before
Whether the sampling clocks f _sa and f _sb are in a quadrature relationship
Digital quadrature detection demodulation, comprising: conversion means for converting φ = arctan {S _a / (S _b cos θ) -tan θ} based on the deviation angle θ to obtain the phase φ of the modulated wave. vessel. 3. A converter for outputting two orthogonal components I and Q.
Based on the output of the conversion means for finding the phase φ of the stage or modulated wave
The clock is regenerated and the sampling clock f _sa ,
a bit timing recovery circuit for generating f _sb ;
Advance of the phase of the recovered clock from the timing recovery circuit,
The sampling means or the conversion means according to the delay
Correction means for correcting the output phase of
3. A digital quadrature detection demodulator according to claim 1, wherein 4. The reproduction timing of said bit timing reproduction circuit.
The leading and lagging phases of the lock are integrated, and the integrated
Integration means for making corrections in
The digital quadrature detection demodulator according to claim 3 . 5. The sampling circuit according to a master clock.
Clocks f _sa and f _sb and the carrier wave
According to the difference between the frequency f _c and the frequency of the master clock
The output of the sampling means or the conversion means.
Claims wherein a correction means for correcting the phase is provided.
Item 5. A digital quadrature detection demodulator according to any one of items 1 to 4 .