JP2689579B2 - Pseudo-lock detection circuit for Costas loop demodulator - Google Patents

Description

The present invention relates to a pseudo lock detection circuit for a Costas loop demodulator, and is a demodulator for a receiver in a satellite communication system using a digital phase modulation method, for example. The present invention relates to a circuit that detects a pseudo lock state of a Costas loop demodulator.

[Summary of the Invention]

The present invention is a signal of a frequency component that appears at the time of pseudo lock of a Costas loop demodulator at the output of a multiplier that multiplies the Ich multiplication output of a Costas loop demodulator that demodulates a phase-modulated carrier and the Qch multiplication output. The carrier frequency of the input signal of the Costas loop demodulator is the Costas loop demodulator by detecting that the output of the synchronous detection unit and the output of the synchronous detection unit are out of the predetermined range. Of the voltage controlled oscillator of the demodulator in the high frequency direction or in the low frequency direction by an integer multiple of 1/2 of the frequency corresponding to the bit rate of data transmission (hereinafter referred to as the bit rate frequency), Costas When the loop demodulator is in the pseudo lock state, the pseudo lock state of the mode specified by the frequency of the carrier wave used in the synchronous detection means and the above frequency. It is to the direction of displacement can be detected.

[Conventional technology]

Frequency modulation (FM) is used as the analog modulation method, and 2-phase phase modulation (BPSK), 4-phase phase modulation (QPSK), MSK modulation, etc. are used as the digital modulation methods. Is used. The FM modulation method has been used in communication systems mainly for analog voice transmission, but it is not often used in recent satellite communication methods in which digital signals such as images and data are increasing as information to be transmitted. Digital phase modulation methods such as two-phase phase modulation and four-phase phase modulation have become mainstream. Further, in the multiplex communication system by code division, spectrum spreading communication is used.

A so-called Costas loop type demodulator is known as a means for obtaining a demodulated signal from a digital phase modulated wave.
No. 215256 discloses a technology of a Costas loop demodulator that receives by switching between two-phase modulation and four-phase modulation.

[Problems to be solved by the invention]

By the way, the Costas loop type demodulator is a kind of compound phase lock loop (hereinafter referred to as PLL) circuit. That is,
When the carrier frequency of the input signal of the Costas loop demodulator matches the oscillation frequency of the voltage controlled oscillator (hereinafter referred to as VCO) of the Costas loop demodulator and their phases, the lock state (hereinafter referred to as the normal lock state) is established. Therefore, a proper demodulated signal can be obtained. However, if the carrier frequency of the input signal deviates from the oscillation frequency of the VCO in the high frequency direction or the low frequency direction by an integral multiple of 1/2 of the frequency of the bit rate of data transmission, it is as if in a locked state (hereinafter, pseudo state). Lock state). That is, the Costas loop demodulator may enter a pseudo lock state in a plurality of modes. When the Costas loop demodulator is in the pseudo lock state, data cannot be read normally, and once the Costas loop demodulator is in the pseudo lock state, it will be in the normal lock state even if the input signal of the correct carrier frequency is input after that. It takes time to recover.

The pseudo lock detection circuit of the Costas loop demodulator according to the present invention is made in view of the above circumstances, and the carrier frequency of the input signal of the Costas loop demodulator is the VCO oscillation of the Costas loop demodulator. If the Costas loop demodulator is in the pseudo lock state when the data transmission bit rate is shifted by an integer multiple of 1/2 of the frequency in the high frequency direction or low frequency direction relative to the frequency, it is specified by the carrier wave of the synchronous detection means. It is an object of the present invention to provide a circuit for detecting the pseudo-locked state of the selected mode and the direction of the frequency shift.

[Means for solving the problem]

A pseudo lock detection circuit of a Costas loop demodulator according to the present invention is provided in a Costas loop demodulator that demodulates a phase-modulated carrier wave in order to solve the above problems.
Synchronous detection means for synchronously detecting the signal of the frequency component appearing at the time of pseudo lock of the Costas loop demodulator to the output of the multiplier that multiplies the Ich multiplication output and the Qch multiplication output, and demodulates with the Costas loop demodulator. Carrier signal generation means for supplying to the synchronous detection means a carrier signal for synchronous detection containing frequency components 1 to n (n is an integer) times the frequency of the bit rate of the data transmission by the signal, and the synchronous detection means. Is detected to be in a level outside the predetermined range, and outputs a pseudo lock detection signal.

[Action]

According to the pseudo lock detection circuit of the Costas loop demodulator according to the present invention, the carrier frequency of the input signal of the Costas loop demodulator is higher or lower than the oscillation frequency of the VCO of the Costas loop demodulator. If the Costas loop demodulator is in the pseudo lock state due to an integer multiple of 1/2 the frequency of the data transmission bit rate, the pseudo lock of the mode specified by the frequency of the carrier wave used in the synchronous detection means. The state and the direction of the frequency shift can be detected.

〔Example〕

Hereinafter, an embodiment in which the pseudo lock detection circuit of the Costas loop demodulator according to the present invention is applied to a receiver of spread spectrum communication will be described with reference to the drawings.

FIG. 1 shows a demodulation unit in a receiver of spread spectrum communication. First, the demodulation unit will be described. The spread spectrum signal S1 is supplied to the input terminal 1 as an input signal. This input signal is a delay lock loop (DL
It is called L circuit. ) 10 and multiplier 2.

The DLL circuit 10 includes a phase comparator 11, a loop filter 12, and V
It consists of CO13 and spread code generator 14, and VCO13
Generates a clock S2 corresponding to the carrier frequency of the input signal S1. The spreading code generator 14 generates a spreading code S3 and a leading pulse S4 indicating the leading pulse position of each block of the spreading code S3. A local signal generator 30 for generating a carrier wave used for synchronous detection described later by the clock S2 and the head pulse S4.
The spread code S3 is supplied to the multiplier 2.

In the multiplier 2, the spread spectrum signal S1 which is the input signal is multiplied by the spread code S3,
The phase modulation signal S5 is used. This phase modulation signal S5 is supplied to the Costas loop demodulator 20.

The Costas loop demodulator 20 is an Ich multiplier 21, I
ch low pass filter (hereinafter referred to as LPF) 22, Qch multiplier 23, Qch LPF 24, multiplier 25, loop filter 26, VC
It consists of O27 and π / 2 phase shifter 28. In this Costas loop demodulator 20, the phase modulation signal S5 is a multiplier
21 and the multiplier 23. In this multiplier 21, VC
The output signal of O27 and the phase modulation signal S5 are multiplied. On the other hand, in the multiplier 23, the output signal of the VCO 27 is multiplied by the signal in which the phase is delayed by π / 2 in the π / 2 phase shifter 28 and the phase modulation signal S5. The output signals of the multipliers 21 and 23 are supplied to the LPFs 22 and 24, respectively, and the frequency components above a predetermined frequency are removed. The output signal S6 of the LPF22 (Ich multiplication output) and the output signal S7 of the LPF24 (Qch multiplication output) are respectively supplied to the multiplier 25, and are multiplied in the multiplier 25. The output signal S8 of the multiplier 25 is the loop filter 26 and the pseudo lock detection circuit.
Supplied to 40. The output signal of the loop filter 26 is VCO27
And is controlled so that the oscillation frequency and phase of the VCO 27 coincide with the carrier frequency of the phase modulation signal S5. In addition,
The output signal S6 of the LPF22 is the Costas loop type demodulator 20.
And is supplied to the output terminal 2.

On the other hand, the local signal generator 30 includes a sine wave generator 31, n
The amplifiers 32 _{1 to} 32 _n , the n resistors 33 _{1 to} 33 _n , and the buffer up 34. The sine wave device 31 uses the clock S2 and the head pulse S4 to generate a sine wave signal that is an integer number (1 to n) times the frequency of the bit rate of data transmission.
Generate f1 to fn. These sinusoidal signals f1 to fn
Are added in the adding means including the amplifiers 32 _{1 to} 32 _n and the resistors 33 _{1 to} 33 _n, and are added to the pseudo lock circuit 40 via the buffer up 34. That is, the output signal S9 of the buffer up 34 is a signal containing each frequency component of 1 to n times the frequency of the bit rate of data transmission.

The pseudo lock detection circuit 40 is a multiplier for synchronously detecting the output signal S8 of the multiplier 25 of the Costas loop demodulator 20.
It is composed of synchronous detection means composed of 41 and LPF 42, and comparators 43 and 44 for discriminating the level of the synchronously detected signal and transmitting a pseudo lock detection signal.

Now, the output signal S8 of the multiplier 25 of the Costas loop demodulator 20 will be described with reference to FIGS.

FIG. 2 shows the carrier frequency of the phase modulation signal S5 and VCO27.
FIG. 6 is a waveform diagram showing the operation of the Costas loop demodulator 20 in a normal lock state in which the oscillation frequencies and their phases are the same, and the output signal S6 of the LPF 22 that is the Ich multiplication output of the Costas loop demodulator 20. Is shown in a, the waveform of the output signal S7 of the LPF24 which is the Qch multiplication output of the Costas loop demodulator 20 is shown in b, and the Costas loop demodulator 20
The waveform of the output signal S8 of the multiplier 25 is shown in c. In this normal lock state, the output signal S8 of the multiplier 25 has a value close to zero as shown in FIG.

FIG. 3 shows the carrier frequency of the phase modulation signal S5 and VCO27.
Oscillation frequency is 1 / the frequency of the bit rate of data transmission
FIG. 6 is a waveform diagram showing the operation of the Costas loop demodulator 20 that is in the pseudo lock state after being shifted by 2 minutes, and shows the waveform of the output signal S6 of the LPF22, which is the Ich multiplication output of the Costas loop demodulator 20, in a. The waveform of the output signal S7 of the LPF 24, which is the Qch multiplication output of the Costas loop demodulator 20, is shown in b, and the waveform of the output signal S8 of the multiplier 25 of the Costas loop demodulator 20 is shown in c. In this pseudo lock state, the output signal S8 of the multiplier 25 becomes a signal of the frequency component (hereinafter referred to as f component) of the bit rate of data transmission as shown in c of FIG.

FIG. 4 shows the carrier frequency of the phase modulation signal S5 and VCO27.
The Costas loop demodulator in which the oscillating frequency of the device shifted to the frequency of the bit rate of the data transmission and became a pseudo lock state 20
3 is a waveform diagram showing the operation of the Costas loop demodulator
The waveform of the output signal S6 of the LPF22 which is the multiplication output of Ich of 20 is a
The waveform of the output signal S7 of the LPF 24, which is the Qch multiplication output of the Costas loop demodulator 20, is shown in b, and the waveform of the output signal S8 of the multiplier 25 of the Costas loop demodulator 20 is shown in c. In this pseudo lock state, the output signal S8 of the multiplier 25 becomes a 2f component signal as shown in FIG. 4c.

In the above description, the carrier frequency of the phase modulation signal S5 and VCO27
Oscillation frequency is 1 / the frequency of the bit rate of data transmission
Only when it is shifted by 2 minutes or frequency, the multiplier 25
, The carrier frequency of the phase modulation signal S5 and the oscillation frequency of the VCO 27 are shifted by an integral multiple (3, 4, ... N) of 1/2 of the frequency of the bit rate of data transmission. In this case, the output signal of the multiplier 25 becomes a signal of a frequency component corresponding to the integral multiple. That is, the signals have 3f, 4f, ..., Nf components.

Next, the operation of the pseudo lock detection circuit 40 of the Costas loop demodulator according to the present invention when the output signal S8 of the multiplier 25 as described above is input will be described.

In the multiplier 41, the output signal S8 of the multiplier 25 and the output signal S9 of the local signal generator 30 are multiplied, the multiplied signal is supplied to the LPF42, the data included in the output signal S9 Frequency components (f, 2f, 3f, ..., Nf) that are 1 to n times the frequency f of the transmission bit rate are removed. That is, the output signal S8 of the multiplier 25 is synchronously detected using the output signal S9 of the local signal generator 30. The detected signal S10 is supplied to the positive input terminal of the comparator 43 and the negative input terminal of the comparator 44. By the way, the Costas loop demodulator 20
Is locked normally, the Costas loop demodulator 20
Since the level of the output signal S8 of the multiplier 25 is approximately zero as described above, the value of the detected signal S10 is approximately zero.
On the other hand, the carrier frequency of the phase modulation signal S5 shifts in the frequency direction higher than the oscillation frequency of the VCO 27 of the Costas loop demodulator 20 by an integer multiple of 1/2 of the bit rate of data transmission, and the pseudo lock state (hereinafter, the above pseudo Called locked). In this case, the value of the detected signal S10 becomes equal to or higher than the predetermined level TH. Further, the carrier frequency of the phase modulation signal S5 is shifted by an integral multiple of 1/2 of the bit rate of data transmission in the frequency direction lower than the oscillation frequency of the VCO 27 of the Costas loop demodulator 20, and the pseudo lock state (hereinafter, the lower In the pseudo lock state), the value of the detected signal S10 becomes equal to or lower than a predetermined level -TH. That is, the bias voltage of the negative input terminal of the comparator 43 is set to the predetermined level TH, and the bias voltage of the positive input terminal of the comparator 44 is set to the predetermined level −TH by the resistor 4
By setting using 5, 46 and 47, when the Costas loop demodulator 20 is in the normal lock state, the output signal of the comparator 43 and the output signal of the comparator 44 become low level. On the other hand, in the above pseudo lock state, the output signal of the comparator 43 becomes high level and the output signal of the comparator 44 becomes low level. Further, in the pseudo lock state below, the output signal of the comparator 43 becomes low level and the output signal of the comparator 44 becomes high level. Therefore, the normal lock state, the upper pseudo lock state, and the lower pseudo lock state of the Costas loop demodulator 20 can be discriminated. The pseudo lock detection signal detected as described above (either the output signal of the comparator 43 or the output signal of the comparator 44 is at a high level) is output to the output terminal 3 or the output terminal 4.

When the Costas loop demodulator is in the pseudo lock state as described above, the signal of the specific frequency component is output at the output of the multiplier that multiplies the Ich multiplication output and the Qch multiplication output of the Costas loop demodulator. appear. The pseudo lock state of the Costas loop demodulator can be detected by detecting the signal of this specific frequency component using the synchronous detection. That is, the frequency component that appears during pseudo lock is
Pseudo-lock state in each mode, for example, Pseudo-lock state in which the carrier frequency of the input signal of the Costas loop demodulator and the VCO oscillation frequency of the Costas loop demodulator deviate by half the frequency of the bit rate of data transmission And the carrier frequency of the Costas loop demodulator differs from the VCO oscillation frequency of the Costas loop demodulator in the pseudo lock state in which the bit rate of the data transmission is shifted by the frequency. As described above, by using a plurality of (n in the above specific example), it is possible to detect the pseudo lock state in any mode. Further, in this embodiment, since the plurality of carriers are added and used, the pseudo lock state of each mode can be detected at one time. In addition, as described above, the Costas loop demodulator can detect whether it is pseudo-locked at a frequency higher than the normal lock state or pseudo-locked at a low frequency. When an input signal is input, the Costas loop demodulator can be forcibly controlled to a normal lock state based on the detection result. The LPF for the synchronous detection may be a primary LPF, which is economical.

〔The invention's effect〕

As is apparent from the above description, the pseudo lock detection circuit of the Costas loop demodulator according to the present invention can detect the pseudo lock state of the mode specified by the carrier frequency for synchronous detection. Further, it is possible to accurately detect whether the pseudo lock state is in the high frequency or the pseudo lock state in the low frequency with respect to the normal lock state.

Further, by using a plurality of carrier waves for synchronous detection at one time, it is possible to detect pseudo lock states in a plurality of modes at once. Further, although it usually takes time to recover the Costas loop demodulator once in the pseudo lock state, the recovery time can be shortened if the pseudo lock state can be accurately detected.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a demodulator of a spread spectrum communication receiver to which a pseudo lock detection circuit of a Costas loop demodulator according to the present invention is applied, and FIG. 2 is a Costas loop demodulator in a normal lock state. Waveform diagram showing the operation of
Fig. 3 shows that the carrier frequency of the Costas loop demodulator input signal and the VCO oscillation frequency of the Costas loop demodulator deviate by 1/2 of the bit rate of data transmission, and the Costas loop demodulator is pseudo-locked. Fig. 4 shows the waveforms of the operation when the status is changed. Fig. 4 shows the Costas loop demodulator input signal carrier frequency and the Costas loop demodulator VCO oscillating frequency deviated by the frequency of the data transmission bit rate. It is a wave form diagram which shows operation | movement when a loop type demodulator is in a pseudo lock state. 20 …… Costas loop demodulator 25 …… Costas loop demodulator multiplier 40 …… Pseudo lock detection circuit 41 …… Synchronous detection multiplier 42 …… Synchronous detection LPF 43, 44 …… Level comparison vessel

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-63-286043 (JP, A) JP-A-58-162156 (JP, A) JP-A-53-128257 (JP, A) JP-A-60- 224345 (JP, A) JP-A-63-40422 (JP, A)

Claims (1)

(57) [Claims] 1. A frequency component that appears at the pseudo lock of the Costas loop demodulator at the output of a multiplier that multiplies the Ich multiplication output of a Costas loop demodulator that demodulates a phase-modulated carrier and the Qch multiplication output. Detection means for synchronously detecting the signal of No. 1, and 1 to n (n is an integer) of frequencies of the bit rate of data transmission by the signal demodulated by the Costas loop demodulator.
Pseudo lock detection signal by detecting carrier wave signal generating means for supplying a carrier wave signal for synchronous detection containing each frequency component to the synchronous wave detecting means, and detecting that the output of the synchronous wave detecting means is out of a predetermined range. A pseudo lock detection circuit for a Costas loop demodulator, which comprises a level discriminating means for outputting.