JP2001136221A - Carrier reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a carrier reproducing device capable of preventing phase synchronization over a wide frequency range and pseudo synchronization near a normal pulling state where phase error information is almost zero with a simple configuration. SOLUTION: A doubler 2 applies frequency multiplication to the frequency of a carrier signal Fc to be reproduced by the lock of a costas loop 1 into a frequency being the same as that of a sub-carrier Fco while the phase of the signal Fc with the signal Fco as a reference is defined as ϕ, a mixer 6 multiplies an obtained carrier signal F2c by the signal Fco to obtain (1/2)cos(2ωt+ϕ0), a filter 7 outputs a direct current signal Vd with the setting ϕ0=0, and outputs an alternating current signal in a near-by frequency in a pseudo synchronous state, a costas PLL is reset so that pseudo-synchronization can be prevented, and the polarity of a demodulation signal can automatically be corrected by a logical circuit with a simple configuration that does not need the operation of difference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a carrier recovery apparatus and, more particularly, to a carrier recovery apparatus used in a phase modulation digital signal communication system.

[0002]

2. Description of the Related Art BPSK (Binary Phase)
Shift Keying (two-phase shift keying) and QPSK
(Quadrature Phase Shift Ke
phase modulation schemes such as ing (four-phase phase shift keying) have better required band characteristics and error rate characteristics than other modulation schemes such as amplitude modulation and frequency modulation. Widely used for broadcast communication. In this phase modulation method, a carrier wave is reproduced using a Costas loop at the time of demodulation, and the DC component of a phase error signal obtained from the input modulation signal of the Costas loop and the output signal of the voltage controlled oscillator is controlled by the voltage controlled oscillator. It is supplied as a voltage to lock the Costas loop.

In this type of carrier recovery circuit, it is known that the carrier frequency is Fc, the data transmission rate is R, and n is a natural number, and the frequency is pseudo-synchronized with the frequency of Fc ± R / 2n. A demodulator for preventing this pseudo-synchronization is disclosed in Japanese Patent Application Laid-Open No. Hei 4-270507. In this demodulator, when a pseudo-synchronization state is established, the loop is reset once and the correct frequency of the carrier is generated in the voltage-controlled oscillator. After that, the loop pulling is resumed.
However, according to this method, the loop bandwidth of the phase-locked loop becomes narrower, so that the received modulated wave cannot be phase-locked over a wide frequency range, and the phase error information becomes almost zero in the vicinity of the normal pull-in state. No countermeasures have been taken to prevent false synchronization.

On the other hand, in this type of carrier recovery circuit, during normal pull-in synchronization, BPSK has 2
In QPSK, there are four phase-locked states. For example, in BPSK, in a synchronized state in which the phase differs from normal synchronization by π, the phase of the reproduced data differs by π, and the polarity of the demodulated signal is reversed. Will do. For this reason, conventionally, a means for solving this problem is taken by a differential signal. In BPSK, the NRZ signal is converted to the NRZ1 signal.
The signal is converted into a signal, and after demodulation, the signal is converted back to an NRZ signal, thereby solving the problem of the phase change accompanying the demodulation. However, such baseband processing requires a clock, and the circuit configuration for clock recovery from a received signal becomes complicated,
In particular, when having various transmission rates, a large number of clocks are required to be reproduced, which causes problems in terms of the complexity of the circuit configuration and the manufacturing cost.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the present situation of such a carrier recovery circuit as described above, and its object is to provide a simple structure for phase synchronization over a wide frequency range. Another object of the present invention is to provide a carrier recovery apparatus capable of preventing pseudo-synchronization near a normal pull-in state where phase error information is close to zero.

[0006]

In order to achieve the above object, according to the present invention, a phase of a reproduced carrier wave, which is phase-modulated by a main signal and reproduced by a Costas loop, with respect to a reference signal is determined. A carrier recovery device that controls based on the frequency of the recovered carrier,
Frequency conversion setting means for converting and setting the frequency of the reference signal to the same frequency; multiplication means for multiplying the reference carrier by the reproduction carrier whose frequency has been converted and set by the frequency conversion setting means; and Filter means for extracting a DC component of the multiplied signal obtained by the means, phase control means for controlling the phase of the reproduced carrier wave based on the DC component extracted by the filter means, based on the control of the phase control means, And a polarity correcting means for correcting the polarity of the main signal.

[0007] According to such a means, a simple configuration that does not require the operation of converting the differential signal is required, phase synchronization is performed over a wide frequency range, and the phase error information is reduced to 0 by controlling the phase of the carrier signal with respect to the reference signal. Pseudo-synchronization in the vicinity of the near normal pull-in state is prevented.

[0008] Similarly, in order to achieve the above object, according to a second aspect of the present invention, in the first aspect of the invention, the reference signal is a sub-modulated wave phase-modulated by a sub-signal, and The means controls the phase of the reproduced carrier wave when the sub-modulated wave is not modulated.

According to such means, the sub-modulated wave phase-modulated by the sub-signal is used as the reference signal, and the phase control means controls the phase of the reproduced carrier wave when the sub-modulated wave is not modulated. The operation of the invention described in claim 1 is realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the polarity determination circuit of the reproduced carrier of this embodiment, and FIG. 2 is a block diagram showing the configuration of the Costas loop of FIG.

[0011] Costas loop
In p) 1, as shown in FIG.
The mixer 14 is connected to the output terminals of the mixers 10 and 12, and the output terminal of the mixer 14 is connected to V
CO (Voltage controlled OSC)
The modulation signal Fi = mcos {ωt + φ (t)} is input to one of the input terminals of the mixer 10 and the mixer 12, and the signal Fo1 = ac output from the VCO 13
osωt is input to the other input terminal of the mixer 10, and the signal Fo 1 is shifted by π / 2 by the phase shifter 11 connected to the VCO 13.
The signal Fo2 is input to the other input terminal of the mixer 12. Then, in the mixer 10, the multiplication of the modulation signal Fi and the signal Fo1 is performed as follows.

Fa = Fi · Fo1 = mcos ｛ωt + φ (t)｝ · acosωt = (１ ／) am [cos ｛2ωt + φ (t)｝ + cosφ (t)] (1)

In the mixer 12, the multiplication of the modulation signal Fi and the signal Fo2 is performed as follows.

Fb = Fi · Fo 2 = mcos ｛ωt + φ (t)｝ bsinωt = (（) bm [sin ｛2ωt + φ (t)｝-sinφ (t)] (2)

The DC component (１ ／) am · cos (φt) extracted by the loop filter from equation (1) and the DC component (１ ／) bm · cos (φt) extracted by the loop filter from equation (2)
sinφ (t) is multiplied by the mixer 14 as follows.

(1/2) am · cosφ (t) · (1/2) bm · sinφ (t) = (1/8) abm 2 {sin2φ (t)} (3)

In equation (3), φ (t) is 0 or π
Therefore, sin2φ (t) is always 0, and Costas Loop 1 is locked. In this case, the reproduced carrier F
If the phase of o1 is reversed by π and becomes the opposite phase, the polarity of the carrier is inverted, but the lock is in the same state, and the carrier phase cannot be controlled as it is. Also, when the carrier wave is out of phase, the demodulated signal also has amcos (φt) −
amcos (φt), and the logical value of the signal is inverted.

For this purpose, in the present embodiment, the circuit shown in FIG. 1 controls and determines the phase of the carrier signal Fc with reference to the sub-carrier signal Fco, and furthermore, the circuit shown in FIG. The polarity of the demodulated signal is determined. Such a main part of the present embodiment will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing a configuration of a polarity discriminating circuit of a demodulated signal according to the present embodiment. FIGS. 4 and 5 provide a modulation input signal according to the present embodiment, and show the frequency of the main carrier and the subcarrier. Is a block diagram showing a configuration of a modulation circuit having an integer relationship,
FIG. 6 is a characteristic diagram showing the frequency characteristics of the main signal and the sub-signal according to the present embodiment, and FIG. 7 is a characteristic diagram showing the relationship between the reference signal and the reproduced carrier whose frequency is converted and set in the present embodiment. 8 is a flowchart showing the operation of the present embodiment.

In the present embodiment, as shown in FIG. 6, a carrier signal Fc is phase-modulated by a main signal 23 occupying a wide frequency band, and a sub-signal 24 occupying a relatively narrow frequency band. The sub-carrier signal Fco is phase-modulated. And the specific configuration of the modulation circuit is
As shown in FIG. That is, a carrier signal Fc is generated and output based on the frequency of the output signal of the oscillator 15, and the carrier signal Fc is phase-modulated by the main signal 23 in the main signal modulator 18 connected to the oscillator 15, 18 outputs a modulation signal Fmo. The frequency of the output signal of the oscillator 15 is
5, the frequency is multiplied by the doubler 22, and a subcarrier signal Fco having a frequency twice as high as the frequency of the output signal of the oscillator 15 is generated and output.
co is phase-modulated by the sub-signal 24 in the sub-signal modulator 20 connected to the doubler 22, and the sub-signal modulator 20 outputs a modulation signal Fm1. Then, the modulation signal Fmo output from the main signal modulator 18 and the modulation signal Fm1 output from the sub signal modulator 20 are combined into a signal combiner connected to the main signal modulator 18 and the sub signal modulator 20. Signals are synthesized at 21, and a modulated signal Fi is output from the signal synthesizer 21, and the modulated signal is input to the Costas loop 1 of FIG. 1 after transmission.

In the present embodiment, when the Costas loop 1 is locked, the carrier signal Fc reproduced as the output signal of the VCO 13 is transmitted to the doubler 2 connected to the Costas loop 1 as shown in FIG. As shown in (2), the frequency is multiplied by the same frequency as the frequency of the sub-carrier signal Fco, and is converted into the carrier signal F2c. Then, the carrier signal F2c is input to the mixer 6 connected to the filter 3 via the filter 3 connected to the doubler 2, and the sub-carrier signal Fco
Is input to the mixer 6 connected to the filter 5 via the filter 5. With the angular frequency thus standardized as ω, the mixer 6 outputs the carrier signal F2
The multiplication of c and the subcarrier signal Fco is performed as follows in correspondence with the normal phase and the negative phase.

F2c · Fco = cos (ωt + φ ₀ ) · cos (ωt) = (１ ／) {cos (2ωt + φ ₀ ) + cosφ ₀ } (4)

−F2c · Fco = −cos (ωt + φ ₀ ) · cos (ωt) − (1/2) {cos (2ωt + φ ₀ ) + cosφ ₀ } (5)

Here, since the phase φ ₀ can be set freely, if φ ₀ = 0, the frequency 2ωt of the signal after passing through the filter 7 connected to the mixer 6 in the equations (4) and (5) Is removed, and the DC signal Vd is output from the filter 7. In this state, the expression (4) is
/ 2, and the expression (5) becomes -1/2, and it is discriminated as normal and inversion, respectively. In the pseudo-synchronous state at the near frequency, an AC component is present and a DC component is not obtained, and the Costas loop 1 is reset and controlled so as to start resynchronization. The output signal Vd of the polarity determination circuit output from the filter 7 is input to one input terminal of the operational amplifier 25 of the polarity determination circuit 27 shown in FIG.
The offset voltage Vs is input to the other input terminal of the operational amplifier 25, and the output signal Vd of the polarity determination circuit is output.
Is converted into a logical output L or H by the operational amplifier 25. The output terminal of the operational amplifier 25 is connected to one input terminal of the exclusive OR circuit 26, and the signal Vi is input to this input terminal. And the exclusive OR circuit 26
The demodulated signal Fa = amcosφ (t) from the Costas loop 1 is input to the other input terminal of the second input terminal.

The operation of correcting the polarity of the demodulated signal Fa according to the present embodiment will be described with reference to the flowchart of FIG.

In step S1, it is determined whether or not the level of the output signal Vd of the polarity discriminating circuit after passing through the low-pass filter is 0. If it is determined that the level of the output signal Vd is 0, the process proceeds to step S1. Proceeding to S2, it is determined whether or not the modulation operation of the sub-signal is performed at the present time. If the modulation operation of the sub-signal is not performed, it is determined that the pseudo synchronization is performed. The constituent Costas loop 1 is reset and the process ends.

On the other hand, if it is determined in step S2 that the modulation operation of the sub-signal is being performed, and if the process returns to step S1, it is determined that the level of the output signal Vd of the polarity determination circuit is not 0. In step S4, it is determined whether or not the output signal Vd of the polarity determination circuit is a positive value. If the output signal Vd of the polarity discriminating circuit is a positive value, the signal level of the demodulated signal Fa is determined to be positive. In step S5, the input signal Vi of the exclusive OR circuit 26 becomes L, and the demodulated signal Fa Is used as is.
On the other hand, if it is determined in step S4 that the output signal Vd of the polarity discriminating circuit is a negative value, the demodulated signal Fa has an opposite phase, so that the input signal Vi of the exclusive OR circuit 26 is determined in step S6. Becomes H, and the demodulated signal Fa is used after correcting the polarity.

As described above, according to the present embodiment, the carrier signal F reproduced in the locked state of the Costas loop 1 is
The frequency of the subcarrier signal Fco is multiplied by the doubler 2 to the same frequency as the frequency of the subcarrier signal Fco.
c, and the mixer 6 multiplies the carrier signal F2c by the sub-carrier signal Fco to obtain the sub-carrier signal Fco.
During non-modulation of co, ± (1
/ 2) cos φ ₀ is obtained, and by setting φ ₀ = 0, the component of the frequency 2ωt of the signal after passing through the filter 7 is removed, and the output signal Vd of the polarity discrimination circuit is output.
The polarity of the demodulated signal Fa is corrected by determining the opposite phase of the demodulated signal Fa by the operational amplifier 25 and the exclusive OR circuit 26. In this way, when the pseudo-synchronization state is established at the near frequency, the AC component is output from the filter 3, the DC component is not obtained, the Costas loop 1 is reset, and the resynchronization is controlled.
A simple configuration that does not require the operation of converting the differential signal enables phase synchronization over a wide frequency range, and controls the phase of the carrier signal with respect to the reference signal so that the phase error information is close to a normal pull-in state close to zero. It is possible to prevent pseudo-synchronization with high accuracy.

In the above description, as shown in FIG. 4, the output signal of the oscillator 15 is frequency-multiplied by the doubler 22 to generate a sub-carrier signal Fco having a frequency twice the frequency of the carrier signal Fc. However, the present invention is not limited to this embodiment, and as shown in FIG. 5, the double frequency, the triple frequency,. It is also possible to set the frequency ratio between the carrier signal Fc and the sub-carrier signal Fco by extracting with the filters 16 and 17. The carrier signal F
The carrier signal Fc and the subcarrier signal Fco are set to the least common divisor of the frequency of the subcarrier signal Fco and the frequency of the subcarrier signal Fco.
Can be converted.

[0030]

According to the first aspect of the present invention, the phase of the reproduced carrier that is phase-modulated by the main signal and reproduced by the Costas loop with respect to the reference signal is controlled based on the reference signal. By the conversion setting means, the frequency of the carrier signal and the frequency of the reference signal are converted and set to the same frequency, and the carrier signal and the reference signal whose frequencies are converted and set are multiplied by each other by the multiplication means, and the obtained multiplied signal The DC component is extracted by the filter means, the phase control means controls the phase of the reproduced carrier based on the extracted DC component, and the polarity correction means controls the polarity of the demodulated main signal based on the phase control. Is corrected. For this reason, a simple configuration that does not require a differential signal conversion operation becomes possible, and phase synchronization over a wide frequency range becomes possible, and by controlling the phase of the reference signal, the phase error information becomes close to a normal pull-in state close to zero. Can be prevented with high precision, and the polarity of the demodulated main signal can be corrected.

According to the second aspect of the present invention, the sub-modulated wave phase-modulated by the sub-signal is used as the reference signal, and the phase control means controls the phase of the reproduced carrier wave when the sub-modulated wave is not modulated. Thereby, the effect of the invention described in claim 1 is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a polarity determination circuit for a reproduced carrier wave according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of the Costas loop of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a demodulated signal polarity discriminating circuit of the embodiment.

FIG. 4 is a block diagram showing a configuration of a modulation circuit that provides a modulation signal to the embodiment and in which the frequencies of a carrier signal and a subcarrier signal are in an integer relationship.

FIG. 5 is a block diagram showing a configuration of another modulation circuit that provides a modulation signal to the embodiment and in which the frequencies of the carrier signal and the subcarrier signal are in an integer relationship.

FIG. 6 is a characteristic diagram showing frequency characteristics of a main signal and a sub signal in the embodiment.

FIG. 7 is a characteristic diagram showing a relationship between a reference signal and a carrier signal whose frequency has been converted and set in the embodiment.

FIG. 8 is a flowchart showing an operation of the embodiment.

[Explanation of symbols]

1. Costas loop, 2. Doubler, 3, 5. Filter, 6. Mixer, 7. Filter, 10,
12, 14 · · · mixer, 11 · · phase shifter, 13 · · V
CO, 15 ... oscillator, 16, 17 ... filter, 1
8 main signal modulator, 20 sub-signal modulator, 21
Signal combiner, 22 doubler, 25 operational amplifier,
26 ... Exclusive OR circuit, 27 ... Polarity judgment circuit.

Claims (2)

[Claims] 1. A carrier recovery apparatus for controlling, based on a reference signal, a phase of a reproduction carrier that is phase-modulated by a main signal and reproduced by a Costas loop, based on the reference signal. Frequency conversion setting means for converting and setting the frequency of the signal to the same frequency; multiplying means for multiplying the reference carrier by the reproduction carrier whose frequency has been converted and set by the frequency conversion setting means; and Filter means for extracting a DC component of the obtained multiplied signal; phase control means for controlling the phase of the reproduced carrier wave based on the DC component extracted by the filter means; and control of the main signal based on the control of the phase control means. A carrier reproducing apparatus comprising: a polarity correcting unit that corrects a polarity. 2. The method according to claim 1, wherein the reference signal is a sub-modulated wave that is phase-modulated by a sub-signal, and the phase control unit controls the phase of the reproduced carrier when the sub-modulated wave is not modulated. The carrier recovery apparatus according to claim 1.