JPH0678009A - Carrier regenerating circuit for digital modulated wave - Google Patents

Abstract

PURPOSE:To prevent a code error rate from being deteriorated by preventing the generation of a frequency deviation in an input to a spectrum shaping low pass filter(LPF) even when frequency detuning exists. CONSTITUTION:A QPSK modulated input is converted at its frequency through multipliers 2, 3 and a local oscillator 38. The frequency-converted outputs are shaped at their spectrums through digital LPFs 9, 10. The filter outputs are multiplied by a regenerative carrier through a complex multiplier 11 and the multiplied outputs are phase-detected by a phase detector 16 to obtain phase information. The phase information is smoothed by a loop filter 21 and the smoothed output is applied to a local oscillation means 22 and a data converter 23 to control the phase of the regenerative carrier. On the other hand, the smoothed output is obtained as the frequency-detected information of the regenerative carrier by a frequency compensating circuit 27 and the information is used for controlling the oscillation frequency of the oscillator 38 so that the frequency of the regenerative carrier becomes less than a prescribed value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier wave regenerating circuit for a digitally modulated wave used in a device for demodulating a digitally modulated wave or the like which has been QPSK (four phase shift keying) modulated.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a carrier recovery circuit for a QPSK modulated wave that has been conventionally considered.

The QPSK modulated wave introduced to the input terminal 1 is distributed and supplied to the in-phase detector 2 and the quadrature detector 3. The local oscillator signal (hereinafter abbreviated as “local oscillator”) given to the detectors 2 and 3 is divided into a local oscillator 5 having a fixed frequency and a local oscillator 5 having a 0 ° phase and a 90 ° phase. It was done. The outputs of the detectors 2 and 3 are input to the A / D converters 6 and 7, respectively, and converted into digital values. Here, the digitized detection output is input to the complex multiplier 8 that realizes frequency conversion. This complex multiplier 8 has
A local oscillation output from an AFC loop described later is supplied as a frequency conversion carrier.

The output obtained from the complex multiplier 8 is a digital low pass filter (L) having the same frequency transfer characteristic.
PF) 9 and 10, respectively, and spectral shaping is performed. The digital low-pass filters 9 and 10 are filters that form a transfer characteristic required to prevent intersymbol interference in digital data transmission. Generally, when combined with a filter characteristic on the transmission side, a so-called roll-off characteristic is obtained. Is designed to. Therefore, in the outputs of the digital low-pass filters 9 and 10, each detection output is spectrally shaped so that the eye aperture ratio becomes sufficiently large. The outputs of the digital low pass filters 9 and 10 are input to the complex multiplier 11. The complex multiplier 11 can realize exactly the same operation as the frequency converter, that is, the mixer in the intermediate frequency band in the baseband (although a real number type multiplier that does not use a complex number can perform the detection operation,
It is generally not a frequency converter because it cannot represent negative frequency components, so a complex multiplier is used in this system). The output of the complex multiplier 11 is divided into three, and one is supplied to the clock recovery circuit 12 to extract the symbol timing component in the signal and feed it back to the conversion clock inputs of the A / D converters 6 and 7. To be done. The output of the complex multiplier 11 is input to the data reproduction circuit 13, binarized into the I signal and the Q signal, and the demodulated data is output to the output terminals 14 and 15. Further, the output of the complex multiplier 11 is supplied to the phase detector 16 and is also used for detecting the phase difference between the input signal and the output of the numerically controlled oscillator (NCO) 22.

The phase difference information obtained from the phase detector 16 is input to the frequency control terminal of the numerically controlled oscillator 22 via the switch 19 and the loop filter 21 for carrier regeneration. The numerically controlled oscillator 22 is a cumulative addition circuit that does not inhibit overflow, and performs an addition operation up to the dynamic range according to the value of the signal input to the frequency control terminal.
It changes with the value of the control signal. That is, it operates exactly like a voltage controlled oscillator (VCO) in an analog circuit.
The difference from a general VCO is that its oscillation frequency is very stable, and a so-called crystal-based VCXO is used.
It is characterized by the stability and wide frequency variable range that cannot be realized by the VCXO. The output of the numerically controlled oscillator 22 is input to the data conversion circuit 23, converted into a signal of sine and cosine characteristics, and returned to the complex multiplier 11. This loop is a completely digital PLL.
(Phase-locked loop) and if the loop filter 21 includes a circuit having a perfect integration system, the frequency pull-in range of the PLL is infinite in principle, and ideal operation as the PLL can be expected.

Further, an AFC loop is formed in this system. That is, the phase error signal output from the phase detector 16 is input to the frequency error detection circuit 17.
The frequency error detection circuit 17 detects a frequency error between the input signal and the local oscillator. This frequency component is smoothed by the AFC loop filter 24 via the switch 20 and supplied to the frequency control terminal of the numerically controlled oscillator 25. Since the output of the numerically controlled oscillator 25 is a sawtooth signal,
The data conversion circuit 26 converts the signal into a sine and cosine characteristic signal and supplies the signal to the complex multiplier 8. An AFC loop is formed by the above loop.

The output of the frequency error detection circuit 17 is
It is input to the synchronization determination circuit 18 and outputs a loop switching signal according to the frequency error signal. First, the switch 20 is set so that the AFC loop operates at the initial frequency pull-in.
Is turned on, and a loop switching signal for turning off the switch 19 is output. When the frequency error signal becomes sufficiently small, the loop switching signal turns on the switch 19 and turns off the switch 20. As a result, the PLL operation mode is set, and the pull-in operation is started so as to be in carrier synchronization.

[0008]

The above carrier recovery circuit also has a problem of residual frequency error in the AFC operation mode. In the carrier recovery circuit described above, only the AFC operates at the initial frequency pull-in, and when the frequency error signal becomes small, the AFC is switched to the PLL,
After pulling in the residual frequency error at, achieve phase synchronization. However, even after the phase synchronization, the spectrum of the input signal of the digital low pass filters 9 and 10 is as shown in FIG.
As shown in (a), it is asymmetric with respect to the frequency 0 (DC) by the residual frequency error. This spectrum is spectrally shaped by the digital low pass filters 9 and 10. The characteristics of the digital low pass filters 9 and 10 are as follows.
As shown in FIG. 6B, the characteristic is bilaterally symmetric with respect to the direct current, so that the spectrum of the signal is scraped by the residual frequency error. This means that the transmission characteristic for preventing intersymbol interference is not satisfied, and as a result, there is a problem that the eye opening rate becomes small and the code error rate deteriorates. Further, since only the PLL operates after the initial frequency pull-in, when the oscillation frequency of the RF frequency converter changes due to temperature drift or the like, the frequency shift of the input signals of the digital low-pass filters 9 and 10 becomes further large, and the sign There is a problem of degrading the error rate.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a carrier wave regenerating circuit for a digital modulated wave which does not cause deterioration of the code error rate due to the frequency shift of the input signal in the above digital low pass filter.

[0010]

According to the present invention, there is provided a frequency conversion means for multiplying a frequency modulation input by a frequency conversion carrier from a first local oscillation means to obtain frequency conversion, and an output of the frequency conversion means. A low-pass filter that is supplied and performs spectrum shaping, and a loop filter means that multiplies the output of this low-pass filter by a reproduction carrier, performs phase detection on this multiplication output to obtain phase information, and smoothes this phase information. And a phase-locked loop means for supplying the smoothed output of the loop filter means to the second local oscillation means to obtain the reproduction carrier, and the phase-locked loop using the smoothed output of the loop filter means. Means for detecting the frequency of the regenerated carrier, and oscillating the first local oscillation means so that the frequency of the regenerated carrier becomes smaller than a predetermined value. It is obtained and means for controlling the wave number.

[0011]

The phase locked loop (PL
L) achieves frequency locking and phase synchronization. After that, by detecting the frequency of the regenerated carrier and controlling the frequency of the frequency-converted carrier so that the frequency becomes smaller than the specified value, frequency detuning is sufficiently removed in the input signal of the low-pass filter for spectrum shaping. Therefore, the spectrum of the input signal is not partially scraped off, and the code error rate is not deteriorated.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The same parts as those of the circuit of FIG. 2 described above are designated by the same reference numerals.

The QPSK modulated wave introduced to the input terminal 1 is distributed and input to the in-phase detector 2 and the quadrature detector 3. The local oscillator signal (hereinafter abbreviated as “local oscillator”) supplied to the detectors 2 and 3 is generated by the local oscillator 38 from the local oscillator 38.
In this case, the 0 degree phase is locally generated and the 90 degree phase is locally generated. The local oscillator 38 includes a frequency correction circuit 27 described later.
The oscillation frequency is controlled by a control signal obtained by converting the output from the above into an analog signal by the D / A converter 37. The outputs of the detectors 2 and 3 are input to the A / D converters 6 and 7, respectively, and converted into digital values. The detection output digitized here is input to the digital low-pass filters 9 and 10 having the same frequency transfer characteristic, and the spectrum is shaped. These digital low pass filters 9
Reference numerals 10 and 10 are filters that form a transfer characteristic required to prevent intersymbol interference in digital data transmission, and are generally designed to obtain a so-called roll-off characteristic when combined with a filter characteristic on the transmission side. .
Therefore, in the outputs of the digital low-pass filters 9 and 10, each detection output is spectrally shaped so that the eye aperture ratio becomes sufficiently large.

The outputs of the digital low pass filters 9 and 10 are input to the complex multiplier 11. The complex multiplier 11 can realize exactly the same operation as the frequency converter or mixer in the intermediate frequency band in the baseband (a real number type multiplier without a complex number can perform a detection operation, but a negative frequency). It is generally not a frequency converter because it cannot represent its components, so a complex multiplier is used in this system). The output of the complex multiplier 11 is divided into three and one is supplied to the clock recovery circuit 12,
The symbol timing component in the signal is extracted and the A / D
It is fed back to the conversion clock inputs of converters 6 and 7. The output of the complex multiplier 11 is input to the data reproduction circuit 13, binarized into the I signal and the Q signal, and the demodulated data is output to the output terminals 14 and 15. Further, the output of the complex multiplier 11 is supplied to the phase detector 16 and is also used for detecting the phase difference between the input signal and the output of the numerically controlled oscillator (NCO) 22. The phase difference information from the phase detector 16 is input to the frequency control terminal of the numerically controlled oscillator 22 via the loop filter 21 for carrier regeneration. The numerically controlled oscillator 22 is a cumulative addition circuit that does not inhibit overflow, and performs addition operation up to its dynamic range according to the value of the signal input to the frequency control terminal. For this reason, it becomes an oscillation state and its frequency is
It changes with the value of the control signal. That is, it operates exactly like a voltage controlled oscillator (VCO) in an analog circuit.
The difference from a general VCO is that its oscillation frequency is very stable, and a so-called crystal-based VCXO is used.
It is characterized by the stability and wide frequency variable range that cannot be realized by the VCXO. The output of the numerically controlled oscillator 22 is input to the data conversion circuit 23, converted into signals of sine and cosine characteristics, and returned to the complex multiplier 11.
This loop is a completely digital PLL, and if the loop filter 21 includes a circuit having a perfect integration system, the frequency pull-in range of the PLL is infinite in principle, and ideal operation as a PLL. Can be expected.

Further, the output of the integrator of the loop filter 21 is supplied to the frequency correction circuit 27, the frequency and the phase synchronization state of the reproduction carrier are detected, and when the phase synchronization state is judged, the frequency of the reproduction carrier is predetermined. The frequency correction signal is output so as to be smaller than the value. The frequency correction signal is input to the D / A converter 37, converted into an analog signal, and then input to the frequency control terminal of the local oscillator 38 to control the oscillation frequency of the local oscillator 38. Figure 2
Is a specific example of the frequency correction circuit 27.

The output of the integral system of the loop filter 21 is supplied from the input terminal 29 (this signal represents the frequency component of the reproduced carrier). This input signal is input to the phase synchronization determination circuit 30 and the absolute value detection circuit 31, respectively. The phase synchronization determination circuit 30 uses the time change of the input signal to determine the synchronous or asynchronous state. The absolute value detection circuit 31 detects the absolute value of the input signal and supplies it to one input terminal of the subtraction circuit 33. A specified value signal is supplied from the specified value generation circuit 32 to the other input terminal of the subtractor 33, and the calculation result is supplied to the correction signal generation circuit 34.

The sign bit of the input signal is also supplied to the correction signal generation circuit 34. When the input signal is larger than the specified value, the frequency correction signal is output to the output terminal 36 via the switch 35, and the D / A signal is output. It is adapted to be supplied to the converter 37. Here, the phase synchronization determination circuit 30 outputs a control signal to turn on the switch 35 when the phase synchronization determination circuit 30 determines the synchronous state and to turn off the switch 35 when the asynchronous state is determined.

By controlling the frequency of the reproduction carrier to be small after the phase synchronization as described above, that is,
By sufficiently reducing the frequency error between the frequency of the QPSK modulated wave input and the oscillation frequency of the local oscillator 38, deterioration of the eye opening rate due to the frequency shift of the digital low pass filter hardly occurs, and extremely good demodulation of the digital modulated wave is achieved. Is possible.

FIG. 3 shows still another embodiment of the present invention. The same parts as those in the previous embodiment are designated by the same reference numerals.
The QPSK modulated wave introduced to the input terminal 1 is distributed and supplied to the in-phase detector 2 and the quadrature detector 3. In the detectors 2 and 3, a local oscillator 5 having a fixed frequency is locally distributed by the distributor 4.
Thus, it is supplied as a 0 degree phase local oscillation and a 90 degree phase local oscillation. The outputs of the detectors 2 and 3 are input to the A / D converters 6 and 7, respectively, and converted into digital values. The digitized detection output is input to the complex multiplier 8 that realizes frequency conversion. The complex multiplier 8 is supplied with a local oscillator from an AFC loop described later as a frequency conversion carrier. The output obtained from the complex multiplier 8 is a digital low pass filter (LP) having the same frequency transfer characteristic.
F) Input to 9 and 10, respectively, and spectrum shaping is performed. The digital low pass filters 9 and 10 have the same characteristics as described in the previous embodiment. Therefore, in the outputs of the digital low-pass filters 9 and 10, each detection output is spectrally shaped so that the eye aperture ratio becomes sufficiently large. The outputs of the digital low pass filters 9 and 10 are input to the complex multiplier 11.

The complex multiplier 11 can realize exactly the same operation as the frequency converter in the intermediate frequency band, that is, the mixer in the baseband. The output of the complex multiplier 11 is divided into three, and one is supplied to the clock recovery circuit 12 to extract the symbol timing component in the signal and feed it back to the conversion clock inputs of the A / D converters 6 and 7. To be done.
The output of the complex multiplier 11 is input to the data reproduction circuit 13, binarized as an I signal and a Q signal, and output to output terminals 14 and 15 as demodulated data. Furthermore, the output of the complex multiplier 11 is the phase detector 16
And is used for detecting the phase difference between the input signal and the numerically controlled oscillator 22. The phase difference information output from the phase detector 16 is passed through a switch 19 and a loop filter 21, and a numerically controlled oscillator (NCO) 2 for carrier regeneration is used.
2 is input to the frequency control terminal. Numerically controlled oscillator 22
Is a cumulative addition circuit that does not prohibit overflow as described in the previous embodiment. The output of the numerically controlled oscillator 22 is input to the data conversion circuit 23, converted into a signal of sine and cosine characteristics, and returned to the complex multiplier 11. This loop of a loop is a PLL having a completely digital configuration, and ideal operation can be expected as the PLL as described in the above embodiment.

An AFC loop is formed in this system. That is, the phase error information output from the phase detector 16 is supplied to the frequency error detection circuit 17. The frequency error detection circuit 17 detects a frequency error between the input signal and the local oscillator. This frequency component is supplied to one input terminal of the adder 28 via the switch 20.
A frequency correction signal from a frequency correction circuit 27, which will be described later, is supplied to the other input terminal of the adder 28, and the calculation result is given to the loop filter 24. The output of the adder 28 is smoothed by the AFC loop filter 24 and supplied to the frequency control terminal of the numerically controlled oscillator 25. Since the output of the numerically controlled oscillator 25 is a sawtooth signal, it is converted to a sine and cosine characteristic signal by the data conversion circuit 26 and supplied to the complex multiplier 8. AF with the above loop
A C loop is formed.

The output of the frequency error detection circuit 17 is
It is input to the synchronization determination circuit 18. The synchronization determination circuit 18 outputs a loop switching signal according to the frequency error signal and controls the switches 19 and 20. First, when the frequency is initially pulled, the switch 20 is turned on and the switch 19 is turned off so that the AFC loop works. When the frequency error signal becomes sufficiently small, the loop switching signal is switched to the switch 19
Is turned on and the switch 20 is turned off. As a result, the system enters the PLL mode and starts the pull-in operation so that carrier synchronization can be obtained.

The output of the integration system of the PLL loop filter 21 is input to the frequency correction circuit 27.
The frequency correction circuit 27 detects the frequency and the phase-locked state of the reproduction carrier using the input, and when it determines that the frequency is the phase-locked state, outputs a frequency correction signal so that the frequency of the reproduction carrier becomes smaller than a predetermined value. And supplies it to the adder 28.

As described above, after the phase synchronization, the frequency of the reproduction carrier is controlled to be small, that is, the residual frequency error of the AFC is sufficiently small, so that the eye opening due to the frequency shift of the digital low-pass filter. Almost excellent digital demodulated wave demodulation is possible with almost no deterioration of the rate.

FIG. 4 shows a third embodiment of the present invention. The same parts as those in the embodiment described above are designated by the same reference numerals.
Here, description of elements that perform the same operations as those of the above-described two embodiments will be omitted, and portions unique to this embodiment will be described.

In this embodiment, the AFC loop and the PLL exist independently, and the AFC loop is arranged immediately before the digital low pass filters 9 and 10. For PLL,
Since the operation is similar to that of the previous embodiment, the description thereof is omitted, and the AFC loop will be described here. The AFC loop is
A frequency detection circuit 39 to which the output of the complex multiplier 8 is supplied,
The loop filter 40 to which the output of the frequency detection circuit 39 is supplied, the numerically controlled oscillator 25 to which the smoothed output of the loop filter 40 is supplied to the frequency control terminal, and the output of the numerically controlled oscillator 25 are converted into data to obtain the sine and cosine characteristics. The data conversion circuit 26 supplies the signal of 1 to the complex multiplier 8.

The outputs of the A / D converters 6 and 7 are supplied to the complex multiplier 8 and are complex-multiplied with the local output from the data conversion circuit 26. The two outputs of the complex multiplier 8 are input to the digital low pass filters 9 and 10, respectively. It is also input to the frequency detection circuit 39. Frequency detection circuit 3
9 detects a frequency error between the input modulated wave and the frequency-converted carrier, and gives a frequency error signal to the loop filter 40. A frequency correction signal, which will be described later, is also supplied to the loop filter 40, and the correction signal is added to the frequency error signal and then smoothed. The smoothed output is the numerically controlled oscillator 2
5 is supplied to the frequency control terminal 5 to control the frequency of the local oscillation. The local signal is converted into a signal having sine and cosine characteristics by the data conversion circuit 26 and supplied to the complex multiplier 8. By the above, frequency pull-in for frequency detuning is performed,
The PLL achieves phase synchronization after pulling in the residual frequency error of the AFC.

Further, the output of the integration system of the loop filter 21 of the PLL is input to the frequency correction circuit 27 so that the frequency of the reproduced carrier becomes smaller than a predetermined value, that is,
The frequency correction signal is supplied to the loop filter 40 so that the residual frequency error of the AFC becomes small.

By controlling the frequency of the reproduction carrier to be small after the phase synchronization as described above, that is,
By making the residual frequency error of AFC small enough,
The eye aperture ratio hardly deteriorates due to the frequency shift of the digital low-pass filter, and extremely good demodulation of the digital modulated wave becomes possible.

Further, the frequency correction circuit 27 operates so as to detect the phase-locked state and output the frequency-corrected signal after the phase-locked state. However, the frequency-corrected signal is made sufficiently small and the frequency-converted carrier is taken over time. By controlling the above, it is possible to reduce the residual frequency error of the AFC without adversely affecting the PLL even in the process of pulling in the frequency of the PLL. Therefore, the frequency correction circuit is not limited to the above embodiment. For example, a configuration is possible in which the frequency of the reproduction carrier is detected from the output of the loop filter of the PLL, and the frequency correction signal is constantly output so that the frequency is not adversely affected in the pulling operation of the PLL. In addition to this, it goes without saying that the present invention can be variously modified without departing from the scope of the invention.

[0031]

As described above, according to the present invention,
Even if there is frequency detuning, it is possible to eliminate the frequency shift at the input of the low-pass filter for spectrum shaping and prevent the deterioration of the code error rate.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2 is a circuit diagram showing a specific example of the frequency correction circuit of FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing still another embodiment of the present invention.

FIG. 5 is a block diagram showing a digitally modulated wave demodulation device that has been conventionally considered.

FIG. 6 is an explanatory diagram of input signal characteristics and filter characteristics of the digital low pass filter of the circuit of FIG.

[Explanation of symbols]

2, 3 ... Multiplier, 4 ... Distributor, 6, 7 ... A / D converter,
8, 11 ... Complex multiplier, 9, 10 ... Digital low-pass filter, 12 ... Clock recovery circuit, 13 ... Data recovery circuit, 16 ... Phase detector, 17 ... Frequency detector, 18 ... Synchronization determination circuit, 19, 20 ... Switch, 21, 24 ... Loop filter, 22, 25 ... Numerically controlled oscillator, 23, 26
... data converter, 27 ... frequency correction circuit, 28 ... adder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Susumu Komatsu 3-3-9 Shimbashi, Minato-ku, Tokyo, Toshiba Abu E Co., Ltd. (72) Inventor Yasushi Sugita Shin-Sugita-cho, Isogo-ku, Yokohama-shi, Kanagawa No. 8 Toshiba Corporation Visual Media Technology Research Laboratories

Claims (3)

[Claims] 1. A frequency conversion unit that multiplies a modulated wave input by a frequency conversion carrier from a first local oscillator to obtain a frequency conversion output, and a low frequency band that is supplied with the output of the frequency conversion unit and performs spectrum shaping. A pass filter, a means for multiplying the output of the low-pass filter by a reproduction carrier, and subjecting the multiplied output to phase detection to obtain phase information, a loop filter means for smoothing the phase information, and an output of the loop filter means The frequency of the reproduction carrier is detected from its DC component by using the frequency correction means, the frequency is compared with a predetermined value, and a frequency correction signal is output by the comparison output, and the first frequency is corrected by the frequency correction signal. Means for controlling the oscillation frequency of the local oscillator so that the reproduction carrier frequency becomes smaller than a predetermined value. Carrier recovery circuit of the barrel modulated wave. 2. The first local oscillator is an analog local oscillator that outputs a local oscillation output for detecting an in-phase component and a quadrature component of a digital modulated wave input by a detector. Carrier wave regeneration circuit for digitally modulated waves. 3. The first local oscillator is a digital local oscillator for obtaining a frequency-converted output by performing a complex multiplication by multiplying a digital-modulated wave input by digital conversion with a frequency-converted carrier. A carrier recovery device for a digitally modulated wave according to claim 1.