JP2002217992A - Modulation device and modulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct the influence of a phase noise of a local generator of a tuner, without increasing fixed degradation, regardless of the reception state or the modulation system. SOLUTION: An instant phase shift of VCO 901 is corrected in a feed-forward format, in PLL 9 for controlling the tuner VCO 901, by detecting the instant phase shift of VCO 901 from the result of phase comparison between an output of a standard generator 905 and an output of VCO 901 with a phase comparator 909, converting into a carrier phase angle at a phase converter 10, and feedbacking the phase angle of NCO 16 of AFC loop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite / terrestrial / CA
The present invention relates to a demodulation device for digital TV broadcasting.

[0002]

2. Description of the Related Art Conventionally, a demodulation device is disclosed in Japanese Patent No. 276626.
No. 7 is known. FIG. 13 shows the configuration, in which the input signal is a PSK modulated wave. This input signal is divided into two, one of which is a phase comparator 101, a loop filter 102, and a VCO (voltage controlled oscillation) circuit 103.
, And the other is guided to a phase noise detector 104. However, the loop filter 102 used here can adjust the time constant for setting the band. The PLL circuit is configured such that an input signal and a VCO
The phase difference is obtained by comparing the phase with the local oscillation signal from the circuit 103, the phase difference signal is converted into a voltage signal by the loop filter 102, and the oscillation frequency of the VCO circuit 103 is controlled by the voltage signal. The oscillation frequency signal of the VCO circuit 103 is output as a carrier reproduction signal, and is sent to the phase noise detector 104 at the same time. The phase noise detector 104 obtains a relative phase noise intensity from the input signal and the carrier reproduction signal, and controls the band of the loop filter 102 according to the phase noise intensity. The band of the loop filter 102 is controlled to a wide band when the phase noise is large, and to a narrow band when the phase noise is small.

[0003]

The cause of the phase noise deterioration of the modulation signal input to the demodulation device is that the phase noise of the local oscillator used for tuning in the tuner connected to the preceding stage of the demodulation device. Impact is dominant. In the configuration of the conventional example, when the phase noise of the tuner is large, the bandwidth of the loop filter 102 of the PLL that controls the VCO 103 of the demodulator is set to a wide band, so that the phase direction of the demodulated signal generated by the phase noise is increased. Jitter can be suppressed. However, there is a problem that the reception performance is deteriorated (fixed deterioration becomes large) as compared with the case where the phase noise is small because the noise bandwidth of the PLL loop is widened, that is, the loop filter has a narrow band.

As a reference point for determining the amount of phase noise,
In order to use the result of identifying the demodulated signal as code points,
If the reception condition deteriorates due to C / N deterioration, etc., or if N value PS
There is a problem that it is difficult to detect the amount of phase noise when multi-valued by K-value, M-value QAM or the like.

[0005] It is an object of the present invention to remove phase noise generated by a tuner irrespective of a reception state or a modulation method and without increasing fixed deterioration.

[0006]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention relates to a PLL for controlling a local oscillator of a tuner, wherein the instantaneous output of the local oscillator is obtained from a phase comparison output between a reference oscillator output and a local oscillator output inside the PLL. A phase shift is detected, the detected instantaneous phase shift is converted into a carrier phase angle by a phase converter, and the phase angle is fed back to an NFC (Numerically Controlled Oscillator) of an AFC loop or a carrier recovery loop, thereby obtaining a local oscillator. It is provided with a configuration for removing an instantaneous phase shift in a feedforward format.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a demodulation device according to the present invention. In FIG. 1, 1 is an amplifier, 2 and 3 are mixers, 4 and 5 are LPFs (low-pass filters), 6 and 7 are ADCs (A / D converters), 8 is a phase shifter, 9 is a PLL, and 10 is a PLL. Phase converter, 11 is a complex multiplier, 12 and 13 are RRCF (Root Raised Cosine Filter), 14 is a frequency error detector, 15 is a loop filter, 16 is an NCO, 17 is a complex multiplier, and 18 is a phase error detector , 19 is a loop filter, 20 is an NCO, 21
Is a modulation signal input terminal, 22 is an I-axis demodulation signal output terminal, 2
Reference numeral 3 denotes a Q-axis demodulated signal output terminal.

It is assumed that a modulation signal input terminal 21 receives a QPSK modulation signal of a CS digital broadcasting specification having a carrier frequency of 1500 MHz. The QPSK modulation signal input from the modulation signal input terminal 21 is amplified by the amplifier 1, divided into two, and input to the mixers 2 and 3, respectively. When receiving a QPSK modulated signal with a carrier frequency of 1500 MHz, the tuning PLL 9 generates a local oscillation signal of 1500 MHz. In the mixers 2 and 3, the 1500 MHz local oscillation signal generated by the tuning PLL 9 is directly input to the mixer 3, and the phase is shifted by 90 degrees by the phase shifter 8 to the mixer 2. As a result, quadrature detection is performed by the mixers 2 and 3, and a complex baseband signal including the in-phase axis (I axis) and the quadrature axis (Q axis) is obtained.

The baseband signal is supplied to LPFs 4 and 5 at 1/1 of the sampling frequency of the next A / D converter.
Two or more frequency components are removed, digitized by ADCs 6 and 7, and input to complex multiplier 11. Complex multiplier 11
Implements an AFC loop that corrects the difference between the carrier frequency of the received QPSK signal and the oscillation frequency of the local oscillator inside the PLL 9.

The output of the complex multiplier 11 is an RRCF 12,
At 13, the I-axis and Q-axis are independently filtered with the same root roll-off characteristic to remove intersymbol interference. R
Outputs of the RCFs 12 and 13 are input to a complex multiplier 17. The complex multiplier 17 realizes a carrier recovery loop that rapidly corrects minute frequency error components and phase error components that cannot be removed by the AFC loop. The output of the complex multiplier 17 is an I-axis demodulated signal output terminal 2 as a demodulated signal.
2. Output from Q-axis demodulated signal output terminal 23. The output demodulated signal is input to the error correction circuit to restore the original data.

Next, the AFC loop will be described. RR
The signals output from the CFs 12 and 13 are branched and input to the frequency error detector 14. Frequency error detector 14
Detects an error between the carrier frequency of the received signal and the frequency of the local oscillator of the PLL 9. The principle of the frequency error detector 14 is as follows. First, the reception vector (output of the RRCFs 12 and 13)
, And the difference between the angle of the received vector of the n-th symbol and the angle of the received vector of the (n + 1) -th symbol. This is the unit time (1
Since this is a phase rotation during a symbol period, this corresponds to a frequency error. That is, the carrier frequency of the received signal and the PLL
9 corresponds to a frequency error with respect to the frequency of the local oscillator. It should be noted that the received signal of the n-phase PSK has a phase modulation component at an angle that is an integral multiple of 2π / n. Therefore, ± 2π between one symbol
The phase rotation due to the frequency error of the carrier exceeding / 2n is
Since it cannot be separated from the modulation component, it cannot be detected. That is, ± fsym / 2 with respect to the symbol frequency fsym
n is the frequency error detection limit. For example, for a QPSK modulated signal having a symbol frequency of 20 MHz, ± 2.5 MHz
Is the detection limit.

The frequency error obtained by the frequency error detector 14 is averaged by the loop filter 15 and input to the NCO 16. The NCO 16 is an oscillator whose output frequency changes according to the value of the input signal, and outputs an orthogonal sine wave exp (−j (ω0 · t)) to the complex multiplier 11 according to the output of the loop filter 15.

From the above, the complex multiplier 11, RRCF1
2, 13, frequency error detector 14, loop filter 1
5. An AFC loop is formed by the NCO 16 and frequency synchronization of the carrier is obtained.

The operation of the AFC loop will be described using mathematical expressions. The n-th baseband signal is represented by (In + jQn)
Assuming that the angular frequency error component of the baseband signal including the frequency offset input to the complex multiplier 11 is ω0 and the phase error component is θ0, the signal input to the complex multiplier 11 is (In + jQn) exp (j (Ω0 · t + θ
0)). Here, in the steady state, the output of the NCO 16 converges to exp (−j (ω0 · t)), so that the output of the complex multiplier 11 has a frequency error removed after all.

FIG. 11 is a block diagram of the loop filter 15. The loop filter 15 includes a multiplier 1501, an adder 1502, and a latch circuit (D) 1503. The latch circuit 1503 is a latch circuit that holds the output of the adder 1502 in synchronization with the symbol clock.
When the output of the frequency error detector 14 is input to the multiplier 1501, the multiplier 1501 multiplies the output by the constant γ and inputs the result to the adder 1502. The adder 1502 is a latch circuit 1
503 constitute a cumulative adder. Latch circuit 15
03 is the output of the loop filter 15 and becomes the NCO
16 is input. Note that the function of the multiplier 1501 can be easily realized when the value of the constant γ is a power of 2, by shifting the input signal to the multiplier bit by bit and outputting the shifted signal.

FIG. 7 is a block diagram of the NCO 16. N
CO16 is an adder 1601, a latch circuit (D) 160
2, adder 1604, data conversion circuits 1605, 160
6 is included. The adder 1601 and the latch circuit 1602 form a cumulative adder 1603. The cumulative adder 1603 is formed of an adder that does not inhibit overflow, and performs a conversion from an instantaneous frequency to an instantaneous phase by its integration operation. In the adder 1604, the cumulative adder 16
The instantaneous phase of the 03 output and the output of the phase converter 10 are added. The phase converter 10 will be described later. Adder 1
The output signal of 604 is converted into an orthogonal sine wave by data conversion circuits 1605 and 1606 having cosine and sine characteristics, and output to the complex multiplier 11. Note that the data conversion circuits 1605 and 1606 can be realized by a ROM or an arithmetic circuit using function approximation.

Next, the carrier recovery loop will be described.
The output of the complex multiplier 17 is branched to form a phase error detector 18
Is input to The output of the NCO 20 and the RRCFs 12, 1
3 is detected as an error between each received symbol point on the I and Q planes and the closest ideal reception point (code point).

The phase error information from the phase error detector 18 is supplied to the N
Input to CO20. The NCO 20 is an oscillator whose output frequency changes according to the value of the input signal, and the orthogonal sine wave exp (−j (ω1 ·
t)) is output to the complex multiplier 17.

As described above, the complex multiplier 17, the phase error detector 18, the loop filter 19, and the NCO 20 form a carrier recovery loop, and phase synchronization of the carrier is obtained.

The process of carrier recovery will be described using mathematical expressions. That is, the n-th baseband signal is represented by (In +
jQn), the angular frequency error component of the baseband signal including the minute frequency offset and the phase offset input to the complex multiplier 17 is ω1, and the phase error component is θ1, the signal input to the complex multiplier 17 is (In + j
Qn) exp (j (ω1 · t + θ1)).
Here, the output of the NCO 20 is exp (-j
(Ω1 · t + θ1)), and consequently, the baseband signal (In + jQn) is obtained from the output of the complex multiplier 17.

FIG. 10 is a block diagram of the loop filter 19. This configuration is a so-called perfect integration type LPF.
The loop filter 19 includes multipliers 1901 and 1902, adders 1903 and 1905, and a latch circuit (D) 1904. The latch circuit 1904 is a latch circuit that holds the output of the adder 1903 in synchronization with the symbol clock, and the output is provided to the adders 1905 and 1903. The output of the phase error detector 18 is a multiplier 1901,
When input to 1902, the multiplier 1901 multiplies the constant α by the constant α and inputs the result to the adder 1905.
Is multiplied by a constant β and input to the adder 1903.
The adder 1903 and the latch circuit 1904 constitute a cumulative adder. The result of the addition in the adder 1905 is output from the loop filter 19 and input to the NCO 20. Note that the functions of the multipliers 1901 and 1902 can be easily realized when the values of the constants α and β are powers of 2, by shifting the input signal to the multiplier bit by bit and outputting the shifted signal.

FIG. 9 is a block diagram of the NCO 20. N
CO20 is an adder 2001, a latch circuit (D) 200
2. It includes data conversion circuits 2004 and 2005. The adder 2001 and the latch circuit 2002 compose a cumulative adder 2003. The cumulative adder 2003 is formed of an adder that does not prohibit overflow, and performs a conversion from an instantaneous frequency to an instantaneous phase by its integration operation. The output signal of the accumulator 2003 becomes an orthogonal sine wave in the data conversion circuits 2004 and 2005 having cosine and sine characteristics, and is output to the complex multiplier 17. Note that the data conversion circuits 2004 and 2005 can be realized by a ROM or an arithmetic circuit using function approximation.

Next, the mechanism of the phase noise removal constituted by the PLL 9, the phase converter 10, and the NCO 16, which is the point of the present invention, will be described. First, the details of the PLL 9 will be described.
FIG. 4 is a block diagram of the PLL 9. 901 is a VCO
(Voltage controlled oscillator), 902 is an N frequency divider, 903 is a phase comparator, 904 is an M frequency divider, 905 is a reference oscillator, 90
6 is a loop filter, 907 and 908 are L frequency dividers, 90
9 is a phase comparator.

In the digital broadcast receiving tuner, the channel selection P
A 4 MHz crystal oscillator is generally used as an LL reference oscillator. Therefore, the oscillation frequency of the reference oscillator 905 is set to 4 MHz. The phase comparison frequency of the PLL is determined by the setting resolution of the tuning frequency.
kHz. As a result, the phase comparator 903
The phase comparison is performed in Hz, and the value of the frequency division ratio M of the M frequency divider 904 is fixed at 16.

On the other hand, the VCO 90
1 changes, however, in the direct conversion type receiving system of the form shown in FIG.
Needs to be adjusted to the carrier frequency of the modulated signal to be received. Here, since the carrier frequency of the received signal is assumed to be 1500 MHz, the value of the frequency division ratio N of the N frequency divider 902 becomes 6000 in order to divide the frequency to the phase comparison frequency of 250 kHz of the phase comparator 903. By changing the value of N in this manner, a signal of an arbitrary frequency can be received within the frequency variable range of VCO 901. The phase error signal for the reference oscillator 905 of the VCO 901 detected by the phase comparator 903 is
06, the frequency of the VCO 901 is controlled. This PLL loop (VCO 901, N frequency divider 90)
2. The phase comparator 903 and the loop filter 906) control the oscillation frequency of the VCO 901 to be the set frequency (in this case, 1500 MHz).

The fluctuation from the set frequency of the VCO 901 is phase noise, which can be observed by monitoring the difference from the oscillation frequency of the reference oscillator 905. That is,
The output of the phase comparator 903 indicates the phase noise of the VCO 901. Since the phase comparison frequency is set to 250 kHz and the output of the VCO 901 is frequency-divided, the output of the VCO 901 for N cycles of the value of the frequency division ratio is averaged to observe the phase error. In addition, the frequency component of the phase noise generally has a problem up to about several tens kHz. Since the phase comparison frequency is set to 250 kHz, further averaging is possible. Assuming that the outputs of the N divider 902 and the M divider 904 are further divided by L, the L dividers 907 and 908 Connect to Here, as an example, L = 4 and the phase comparison frequency of the phase comparator 909 is 62.5 kHz.

FIG. 6 shows an example of the configuration of the phase comparator 909. FIG. 6 is a block diagram of the phase comparator 909. The phase comparator 909 includes a counter 90901 and a latch circuit 90.
902.

The operation of the phase comparator 909 will be described with reference to FIG. Counter 90901 and latch circuit 90902
Operate in synchronization with the clock CLK. Here, it is assumed that this CLK matches the sampling frequency of ADCs 6 and 7. In receiving satellite digital broadcasts, the sampling frequency is often set to 60 MHz.

The counter 90901 is set to 1 in synchronization with CLK.
The increment operation is performed every time. The counter 90901 has a clear terminal, and is connected to the output of the L frequency divider 908. The output of the L divider 908 is
FREF / M / L with respect to the oscillation frequency fREF, and a negative pulse for one cycle of CLK is output at the falling edge of the waveform (waveform (b) in FIG. 12). . When the clear pulse is input to the counter 90901, the count value returns to 0. In this example, fREF / M
/L=62.5 kHz, and the count output of the counter 90901 operating at 60 MHz CLK is 0 to 95
9 (the waveform shown in FIG. 12D), and the count output is input to the latch circuit 90902.

The latch circuit 90902 has an en terminal, to which the output of the L frequency divider 907 is connected. The output of the L frequency divider 907 has a frequency of fVCO / N / L with respect to the oscillation frequency fVCO of the VCO 901, and further outputs a negative pulse for one cycle of CLK at the rise of the waveform ( FIG. 12A shows the waveform). Latch circuit 90
902 captures the data input from the counter 90901 at the time when the en pulse is input, and reads the next en.
An operation of holding up to the pulse is performed (waveform (e) in FIG. 12).

When the PLL 9 is locked, fRE
Since F / M / L and fVCO / N / L are phase-synchronized, if frequency division is performed so that the duty of these waveforms becomes 50%, clear generated at the falling edge of the waveforms
From the relationship between the pulse and the en pulse generated at the rising edge of the waveform, the en pulse is generated substantially at the center of the count operation from 0 to 959, and the output of the latch 90902 becomes a value around 480.

In a state where the phase noise of the VCO 901 is generated, although the phase synchronization of the PLL 9 is maintained, the phase of fVCO / N / L fluctuates with respect to the reference phase of fREF / M / L. In the output of 90902, a value shifted from 480 is detected. This makes it possible to quantitatively detect the instantaneous phase shift (average of N × L cycles of the waveform) of the VCO 901.

The output of the latch 90902 is
Is input to The phase converter 10 performs the operation of (Equation 1) to convert the phase into a phase angle θ having a positive or negative sign.

Θ = 2π × (CT − ((CTmax + 1) / 2)) / (CTmax + 1) (Equation 1) where CT is the value of the output of the latch 90902 and CTmax
Is the maximum value of the count value of the counter 90901 (959 in this example).

The calculated phase angle θ is equal to the NCO 16 of FIG.
It is input to an internal adder 1604. In the adder 1604, a phase angle θ corresponding to the instantaneous phase shift amount of the VCO 901 is added to the phase signal output from the accumulator 1603 that performs tracking as an AFC loop, with a sign for correcting the phase shift. A quadrature sine wave is generated by the data conversion circuits 1605 and 1606 based on the phase signal output from the adder 1604, and the baseband signal and the complex multiplier 11 whose carrier wave is affected by the instantaneous phase shift of the VCO 901 are used.
Is multiplied by. By the feed-forward operation of the PLL 9, the phase converter 10, and the NCO 16 described above, the phase fluctuation of the VCO 901 can be accurately corrected by the carrier rotator including the NCO 16 and the complex multiplier 11. The effect on the original AFC loop due to the addition of the phase angle θ by the adder 1604 is negligible because it does not occur at a point other than the point where the value of θ changes, but for safety, the AFC loop completes the pull-in operation. Control may be performed so that addition is not performed until the output of the loop filter 15 is fixed.

FIG. 5 shows another example of the configuration of the PLL 9. FIG.
In this case can be shared with the phase comparator 909. The difference is that the L dividers 907 and 908 and the phase comparator 909 are deleted, and the ADC 910 and the LPF 911 are removed.
Is added. The phase comparator 903 is EXO
In the case of the R format, the output is a binary signal whose pulse width changes. Therefore, the ADC 910 can easily convert the phase shift amount into a digital value by counting the pulse width. When the output of the phase comparator 903 is an analog value, a normal A / D
Use a converter. The output of ADC 910 is LPF 91
The signal is smoothed by 1 and sent to the phase converter 10.

FIG. 8 shows another example of the configuration of the NCO 16. The difference from FIG. 7 is that the adder 1604 is deleted and a multiplier 1607 and an adder 1608 are added.
The output of the phase converter 10 is multiplied by the constant μ in the multiplier 1607, added to the output of the loop filter 15 in the adder 1608, and input to the accumulator 1603. In the configuration of FIG. 7, the phase of the orthogonal sine wave is directly controlled by the output of the phase converter 10, so that the phase changes discontinuously. On the other hand, in the configuration of FIG. 8, since the output of the phase converter 10 is input as frequency information and integrated by the accumulator 1603 to obtain phase information, the phase of the orthogonal sine wave continuously changes. .

The above is the description of FIG. FIG. 2 shows a modification. The difference from FIG. 1 is that the output signal of the phase converter 10 is connected to the NCO 20 of the carrier recovery loop without being connected to the NCO 16 of the AFC loop. However, in FIG. 2, the configuration of the NCO 16 is FIG.
The configuration of the NCO 20 is shown in FIG. 7 or FIG. As described with reference to FIG. 1, the output signal of the phase converter 10
The essence of the invention is to correct the carrier phase of the complex baseband signal affected by the phase fluctuation of 01, and the block that actually corrects the carrier phase is an AFC loop.
The same effect can be obtained with a carrier recovery loop or other loops.

As described above, according to the present invention, in the PLL for controlling the local oscillator of the tuner, the instantaneous phase shift of the local oscillator is detected and detected from the phase comparison output between the reference oscillator output inside the PLL and the local oscillator output. The instantaneous phase shift is converted into a carrier phase angle by a phase converter, and the phase angle is converted into an NCO of an AFC loop or a carrier recovery loop.
, The instantaneous phase shift of the local oscillator can be removed in a feedforward manner.

According to the phase noise elimination method of the present invention, the instantaneous phase shift is detected by the PLL of the tuner, so that the detection and correction of the phase noise do not depend on the modulation method or transmission line conditions. Therefore, in FIGS. 1 and 2, the demodulation device for the QPSK modulated signal of the CS digital broadcast has been described. It is provided in common and can be applied to other modulation signals such as 8PSK for BS digital broadcasting, OFDM for digital terrestrial broadcasting, 8VSB, and QAM for CATV. Since the phase noise detection does not depend on the transmission path conditions, the phase noise is not erroneously detected even under the condition of low C / N or the presence of a reflected wave, so that the AFC and the carrier recovery loop do not malfunction. Further, since there is no need to control the bandwidth of the carrier recovery loop as in the conventional example, the fixed deterioration does not increase.

Next, a modified example in which a tuner of a type different from that described above is used will be described. In terrestrial digital broadcasting OFDM, 8VSB and CATV QAM, a double superheterodyne format may be used as a tuner. Although a single superheterodyne tuner may be used, a direct conversion type tuner that performs quadrature detection directly in the RF stage shown in FIG. 1 and a frequency conversion are performed only once and only one PLL of the tuner is used. This is common in a certain point, and the phase noise can be similarly removed by the method described with reference to FIG.

FIG. 3 shows the configuration of a tuner in the case of a double superheterodyne tuner. In FIG. 3, 51
Is an amplifier, 52 is a mixer, 53 is a BPF (bandpass filter), 54 is a mixer, 55 is a BPF, and 56 and 57 are P
LL, 58 and 59 are phase converters, 60 is an adder, 61 is an RF signal input terminal, and 62 is an IF signal output terminal.

The modulated signal input from the RF signal input terminal 61 is amplified by the amplifier 51 and converted to the first intermediate frequency (fIF1) by the mixer 52. The first intermediate frequency is set to a frequency higher than the reception band that the receiver can receive. The local oscillator used for this frequency conversion is PL
L56. The configuration of the PLL 56 is the same as the configuration of the PLL 9 shown in FIG. 4 or FIG. Assuming that the carrier frequency of the modulated signal to be received is fRF, the VCO of the PLL 56
The oscillation frequency fLO1 of 901 is set by changing the value of N of the N frequency divider 902 so that fLO1 = fRF + fIF1. The output of the mixer 52 is passed by the BPF 53 so that only the signal of the receiving channel including the carrier wave fIF1 passes and the signal of the adjacent channel is removed. The output of the BPF 53 is input to the mixer 54. The fIF selected by the mixer 54
The frequency conversion of the one modulated signal is performed to a second intermediate frequency (fIF2) lower than the reception band that can be received by this receiver.
The PLL 57 is a local oscillator used for this frequency conversion. The configuration of the PLL 57 is the same as that of the P shown in FIG.
This is the same as the configuration of LL9. VCO901 of PLL57
Is set by changing the value of N of the N frequency divider 902 so that fLO2 = fIF1−fIF2. The output of the mixer 54 is output from the IF signal output terminal 62 by the BPF 55, passing only the signal of the receiving channel including fIF2 and removing the signal of the adjacent channel. Thereafter, although not shown, a third frequency conversion for converting the signal to a low carrier frequency may be performed so that the A / D converter can easily perform sampling. In the VCO used for the third frequency conversion, a crystal resonator is generally used for the resonator, so that phase noise does not matter. After the third frequency conversion, the signal is digitized by an A / D converter, and then quadrature detection is performed by digital signal processing. After that, the demodulation process is performed by the AFC loop or the carrier wave recovery loop as in FIGS. 1 and 2.

As described above, in order to include two VCOs in the double superheterodyne tuner, it is necessary to add the fluctuations of the respective instantaneous phases and feed them forward to the NFC 16 of the AFC loop or the carrier recovery loop.
The phase converters 58 and 59 convert the instantaneous phase fluctuations of the respective VCOs detected by the phase comparators inside the PLLs 56 and 57 into phase angles θ. The operation is the same as that of the phase converter 10 of FIG. The phase angles obtained by the phase converters 58 and 59 are added by the adder 60 and output to the NCO 16. Note that the sign of the phase angle changes depending on whether the oscillation frequency of the VCO is above or below the input signal frequency for performing frequency conversion by the mixer.

The configuration of the phase comparator 909 described above is merely an example, and any other configuration may be used as long as the phase error information can be digitized. In addition, L, M,
The value of N and the value of the frequency are examples, and are not limited to these values. Further, an LPF for smoothing may be inserted into the output of the phase comparator 909. The delay of the system of the PLL 9, the mixers 2, 3, the LPFs 4, 5, the ADCs 6, 7, and the complex multiplier 11, and the PLL 9, the phase converter 10, the NCO
16. If the relative delay of the system of the complex multiplier 11 cannot be ignored, an appropriate delay adjustment may be provided. Further, in the configuration of FIG. 3, appropriate delay adjustment may be performed in each of the system including the PLL 56 and the system including the PLL 57.

[0046]

As described above, according to the present invention, in the PLL for controlling the local oscillator of the tuner, the instantaneous phase shift of the local oscillator is detected from the phase comparison output between the reference oscillator output and the local oscillator output inside the PLL. The detected instantaneous phase shift is converted into the phase angle of the carrier by the phase converter, and the phase angle is set to the NC of the AFC loop or the carrier recovery loop.
By returning to O, the instantaneous phase shift of the local oscillator can be removed in a feedforward manner.

According to the phase noise elimination method of the present invention, the instantaneous phase shift is detected by the PLL of the tuner, so that the detection and correction of the phase noise do not depend on the modulation method or the condition of the transmission line. Further, since there is no need to control the bandwidth of the carrier recovery loop, the fixed deterioration does not increase.

Further, the method for removing the phase noise in cooperation with the tuner is a particularly effective method when the tuner and the demodulation block by the digital signal processing at the subsequent stage are configured in the same module or the same package LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram of a demodulation device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a demodulation device according to a first modification of the embodiment of the present invention.

FIG. 3 is a block diagram of a demodulation device according to a second modification of the embodiment of the present invention.

FIG. 4 is a block diagram showing a first configuration example of a PLL used in a demodulation device.

FIG. 5 is a block diagram showing a second configuration example of a PLL used in the demodulation device;

FIG. 6 is a block diagram illustrating a configuration example of a phase comparator used in a PLL of the demodulation device.

FIG. 7 is a block diagram showing a first configuration example of an NCO used in a demodulation device;

FIG. 8 is a block diagram showing a second configuration example of the NCO used in the demodulation device.

FIG. 9 is a block diagram showing a configuration example of a normal NCO used in a demodulation device;

FIG. 10 is a block diagram illustrating a configuration example of a loop filter used in a carrier recovery loop of the demodulation device.

FIG. 11 is a block diagram illustrating a configuration example of a loop filter used in an AFC loop of the demodulation device.

FIG. 12 is a waveform chart illustrating the operation of the phase comparator.

FIG. 13 is a block diagram showing a configuration example of a conventional demodulation device.

[Explanation of symbols]

1,51 amplifier 2,3,52,54 mixer 4,5,911 LPF 6,7 ADC 8 phase shifter 9,56,57 PLL 10,58,59 phase converter 11,17 complex multiplier 12,13 RRCF 14 Frequency error detector 15, 19, 906 Loop filter 16, 20 NCO 18 Phase error detector 21 Modulation signal input terminal 22 I-axis demodulation signal output terminal 23 Q-axis demodulation signal output terminal 53, 55 BPF 60, 1601 Adder 61 RF signal input terminal 62 IF signal output terminal 101,903,909 Phase comparator 102 Variable band loop filter 103,901 VCO 104 Phase noise detector 902 N frequency divider 904 M frequency divider 905 Reference oscillator 907,908 L frequency division 910 ADC 90901 counter 1503, 1602, 1904, 2002 90902
Latch circuit 1603, 2003 Cumulative adder 1502, 1604, 1608, 1903, 1905
2001 Adder 1605, 1606, 2004, 2005 Data conversion circuit 1501, 1607, 1901, 1902 Multiplier

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Hisaya Kato 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5K004 AA01 BA02 BB02

Claims (2)

[Claims] 1. A mixer for performing frequency conversion or detection of a received digital modulation signal, PLL means for generating a local oscillation signal for tuning input to the mixer, and the local oscillation signal generated by the PLL means Phase comparing means for detecting the instantaneous phase shift by a phase comparison with a reference oscillation signal inside the PLL means, a phase converter for converting the instantaneous phase shift to a phase angle of a carrier wave, and an output of the mixer Carrier rotation means for changing the phase of the carrier, comprising: controlling the phase of the carrier by the carrier rotation means so as to correct the instantaneous phase shift of the local oscillation signal by the output of the phase converter. Characteristic demodulator. 2. A demodulation method for performing frequency conversion or detection by multiplying a received digital modulation signal and a local oscillation signal for tuning to output a baseband signal, wherein the local oscillation signal is output by a PLL. Generating, detecting an instantaneous phase shift of the local oscillation signal by phase comparison with a reference oscillation signal inside the PLL, converting the detected instantaneous phase shift into a phase angle of a carrier wave, A demodulation method, wherein a phase rotation is applied to a carrier by the phase angle so as to correct the instantaneous phase shift of the local oscillation signal.