JP3265052B2 - Digital modulation wave demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for digitally modulated waves modulated by a method such as QPSK (Quadrature Phase Shift Keying).

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional digital demodulator for demodulating a QPSK modulated wave.
The QPSK modulated wave introduced into the input terminal 1 is distributed and supplied to the in-phase detector 2 and the quadrature detector 3. Local oscillation signal applied to detectors 2 and 3 (hereinafter abbreviated as "local oscillation")
Indicates that the fixed frequency local oscillation from the local oscillator 5 is
In this case, a local oscillation having a phase of 0 degrees and a local oscillation having a phase of 90 degrees are performed. The outputs of the detectors 2 and 3 are input to analog-to-digital (A / D) converters 6 and 7, respectively, and are output by a clock having a frequency twice as high as the symbol rate (hereinafter referred to as 2fs) supplied from the clock recovery circuit 12. Converted to a value. Here, the digitized detection output is input to a complex multiplier 8 that realizes frequency conversion. The complex multiplier 8 operates with a clock of 2 fs, and a local output from an AFC loop described later is supplied as a frequency conversion carrier. Outputs of the I-axis component and the Q-axis component obtained from the complex multiplier 8 are input to digital low-pass filters (LPFs) 9 and 10 having the same frequency transfer characteristics, and are spectrally shaped. These digital low-pass filters 9 and 10 are filters for forming transfer characteristics required for preventing intersymbol interference in digital data transmission, and generally provide a so-called roll-off characteristic when combined with filter characteristics on the transmission side. It is designed to be Therefore, the digital low-pass filters 9, 1
At an output of 0, each detection output is spectrally shaped so that the eye opening ratio is sufficiently large. The output of each of the digital low-pass filters 9 and 10 is a complex multiplier 11
Is input to The complex multiplier 11 operates with a clock of 2 fs, and can realize exactly the same operation as the frequency converter in the intermediate frequency band, that is, the mixer, in the baseband band. (The real number type multiplier that does not use complex numbers can perform the detection operation. However, since it cannot represent negative frequency components, it does not become a general frequency converter.) The output of the complex multiplier 11 is divided into two and one is supplied to the clock recovery circuit 12,
A symbol timing component in the signal is extracted. In the clock recovery circuit 12, the frequency of the symbol rate (hereinafter referred to as f
s) and a clock of 2 fs.
The outputs of the I-axis component and the Q-axis component from the complex multiplier 11 are input to a latch circuit 13, where the I-axis component and the Q-axis component are respectively latched by the clock of fs, and output terminals 14 and 15 is output.

Further, the output of the latch circuit 13 is supplied to a phase detector 16 where the phase difference between the input signal and the oscillation signal of a numerically controlled oscillator (NCO) 22 is detected.
The phase difference information obtained from the phase detector 16 is supplied to a frequency control terminal of a numerically controlled oscillator 22 via a loop filter 21 for carrier recovery. Loop filter 2
A loop switching signal to be described later is also input to 1, and the operation state of the loop filter 21 is switched. The numerically controlled oscillator 22 is a cumulative addition circuit that does not inhibit overflow, and performs an addition operation up to its dynamic range in accordance with the value of the signal input to the frequency control terminal. To change. That is, a voltage controlled oscillator (VCO) in an analog circuit
Works exactly like. The difference from a general VCO is that its oscillation frequency is very stable.
It is characterized by a stability higher than that of a VCO (VCXO) using a so-called crystal and a wide frequency variable range that cannot be realized by the VCXO. The output of the numerically controlled oscillator 22 is input to the data conversion circuits 23 and 24, converted into a signal having sine and cosine characteristics, and returned to the complex multiplier 11 as a frequency conversion carrier. This loop is a phase lock loop (PLL) having a completely digital configuration, and stable operation can be expected as the PLL.

An AFC loop is formed in this system. That is, the phase error signal output from the phase detector 16 is supplied to the frequency error detection circuit 17.
The frequency error detection circuit 17 detects a frequency error between the input signal and the local oscillation. This frequency component is AFC
Numerically controlled oscillator 25 smoothed by loop filter 18
Is supplied to the frequency control terminal of The AFC loop filter 18 receives a loop switching signal from the frequency error detection circuit 17 and performs on / off control of a hold operation of an output signal of the AFC loop filter 18. Since the output of the numerically controlled oscillator 25 is a sawtooth signal, the sine and cosine signals are output from the data conversion circuits 26 and 27.
The signal is converted into a characteristic signal and supplied to the complex multiplier 8. An AFC loop is formed by the above loop.

[0005] The frequency error detection circuit 17 outputs a loop switching signal in accordance with the frequency error signal. First,
At the time of initial frequency pull-in, the AFC loop operates and P
A loop switching signal is output so that LL does not operate. When the frequency error signal becomes sufficiently small, the loop switching signal changes, the output signal of the AFC loop filter 18 is held at that point, and the pull-in operation is started so that the PLL synchronizes with the carrier.

[0006]

The demodulation device having the above configuration also has a problem of spurious response of the frequency conversion carrier and the reproduction carrier of the AFC loop and the PLL. In the above demodulator, when there is a frequency detuning of Δf, the numerically controlled oscillator 25 of the AFC loop operated by the clock of fs
Oscillates at a frequency of approximately Δf, and its output signal is converted into signals having sine and cosine characteristics by the data conversion circuits 26 and 27 and supplied to the complex multiplier 8 operating at 2 fs. The spectrum has spurs as shown in FIG. Similarly, a spurious exists in the reproduction carrier of the data conversion circuits 23 and 24 of the PLL. This spurious interference causes a deterioration of the bit error rate. In addition, since the spurious increases particularly as the frequency (Δf) of the frequency conversion carrier increases, there is a problem when the frequency detuning is large.

Therefore, the present invention provides a filter having characteristics as shown in FIG. 3 (B) to suppress the spurious of the frequency-converted carrier and the reproduced carrier so that the digital modulation does not cause the deterioration of the code error rate due to the spurious interference. An object of the present invention is to provide a wave demodulation device.

[0008]

According to the present invention, there is provided a detecting means for obtaining a detection output by multiplying a modulated wave input by a local oscillation frequency signal from a local oscillator, and a detecting means for converting a detected output of the detecting means into a symbol rate. Digital conversion means for performing digital conversion at twice the frequency, phase information detection means for multiplying the output of the digital conversion means by a reproduction carrier, and performing phase detection on the multiplied output at symbol center timing to obtain phase information; Carrier generating means for smoothing the phase information from the phase information detecting means and supplying it to a numerically controlled oscillator, converting the output of the numerically controlled oscillator into a sine wave to obtain the reproduced carrier, and A filter that raises the sine wave to twice the frequency of the symbol rate and suppresses spurs in the carrier pull-in frequency range. It is obtained by a means.

[0009]

According to the above-mentioned means, after the frequency conversion carrier and the reproduced carrier are doubled in rate, the spurious can be sufficiently removed by passing the filter through a filter for suppressing the spurious, so that the spurious interference does not deteriorate the code error rate. .

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The same parts as those of the circuit of FIG. 2 described above are denoted by the same reference numerals.

The QPSK modulated wave introduced to the input terminal 1 is distributed and supplied to the in-phase detector 2 and the quadrature detector 3. A local oscillation signal (hereinafter, abbreviated as “local oscillation”) supplied to the detectors 2 and 3 is a fixed-frequency local oscillation from a local oscillator 5 at a distributor 4. It was made. The outputs of the detectors 2 and 3 are A /
The frequency is twice as high as the symbol rate input to the D converters 6 and 7 and supplied from the clock recovery circuit 12 (hereinafter 2f).
s) to be converted into digital values. Here, the digitized detection output is input to a complex multiplier 8 that realizes frequency conversion. This complex multiplier 8 has 2 fs
And a local output from an AFC loop described later is supplied as a frequency conversion carrier. Outputs of the I-axis component and the Q-axis component obtained from the complex multiplier 8 are input to digital low-pass filters (LPFs) 9 and 10 having the same frequency transfer characteristics, and are spectrally shaped. These digital low-pass filters 9 and 10 are filters for forming transfer characteristics required for preventing intersymbol interference in digital data transmission, and generally provide a so-called roll-off characteristic when combined with filter characteristics on the transmission side. It is designed to be
Therefore, in the outputs of the digital low-pass filters 9 and 10, each detection output is spectrally shaped so that the eye opening ratio becomes sufficiently large. Digital low-pass filter 9,
Each output of 10 is input to a complex multiplier 11.
The complex multiplier 11 operates with a clock of 2 fs, and can realize exactly the same operation as the frequency converter in the intermediate frequency band, that is, the mixer in the baseband band. (A real number type multiplier that does not use a complex number performs a detection operation. Even if it can, it cannot be a general frequency converter because it cannot represent negative frequency components.) The outputs of the I-axis component and the Q-axis component of the complex multiplier 11 are divided into two and one is supplied to the clock recovery circuit 12. The clock recovery circuit 12 extracts a symbol timing component from the signal, and creates and outputs a clock having a symbol rate frequency (hereinafter referred to as fs) and a clock having 2 fs. The output of the complex multiplier 11 is input to the latch circuit 13, the I-axis component and the Q-axis component are respectively latched by the clock of fs, and output to the output terminals 14 and 15 as demodulated data.

Further, the output of the latch circuit 13 is supplied to a phase detector 16 where the phase difference between the input signal and the oscillation signal of a numerically controlled oscillator (NCO) 22 is detected.
The phase difference information from the phase detector 16 is input to a frequency control terminal of a numerically controlled oscillator 22 via a loop filter 21 for carrier recovery. A loop switching signal described later is also input to the loop filter 21, and the operation state of the loop filter 21 is switched. Numerically controlled oscillator 2
2 is a cumulative addition circuit that does not inhibit overflow,
Since the addition operation up to the dynamic range is performed in accordance with the value of the signal input to the frequency control terminal, an oscillation state is established, and the frequency changes according to the value of the control signal. That is, the operation is exactly the same as that of the voltage controlled oscillator (VCO) in the analog circuit. The difference from a general VCO is that its oscillation frequency is very stable. The stability is higher than that of a VCO (VCXO) using a so-called crystal and VCXO.
There is a feature that has a wide frequency variable range that cannot be realized by O. The output of the numerically controlled oscillator 22 is input to the data conversion circuits 23 and 24, and the sine (sin) and the cosine (cos
s) PLL up-converter 2 which is converted into a signal having characteristics
9. In the PLL up converter 29,
The signal having the sine and cosine characteristics is rate-upped to a clock of 2 fs, and is supplied to the complex multiplier 11 through a low-pass filter (LPF) that sufficiently suppresses spurious in a signal band in a PLL pull-in range. This one loop is a PLL having a completely digital configuration, and stable operation can be expected as the PLL.

An AFC loop is formed in this system. That is, the phase error signal output from the phase detector 16 is supplied to the frequency error detection circuit 17.
The frequency error detection circuit 17 detects a frequency error between the input signal and the local oscillation. This frequency error component is A
The signal is smoothed by the FC loop filter 18 and supplied to a frequency control terminal of a numerically controlled oscillator (NCO) 25. AFC
The loop switching signal is also input from the frequency error detection circuit 17 to the loop filter 18, and the AFC loop filter 1
8 on / off control of the hold operation of the output signal. Since the output of the numerically controlled oscillator 25 is a sawtooth signal, it is converted into a sine and cosine characteristic signal by the data conversion circuits 26 and 27 and the AFC up-converter 28
And the rate is increased to a 2 fs clock,
The signal is supplied to the complex multiplier 8 through a low-pass filter (LPF) that sufficiently suppresses spurious in a signal band in the FC frequency pull-in range.

An AFC loop is formed by the above loop. The frequency error detection circuit 17 outputs a loop switching signal according to the frequency error signal. First, at the time of initial frequency pull-in, the AFC loop operates and PL
A loop switching signal is output so that L does not operate.
Then, when the frequency error signal becomes sufficiently small, the loop switching signal changes, whereby the AFC loop filter 1
The output signal 8 is held at that time, and the pull-in operation is started so that the PLL synchronizes with the carrier.

With the above configuration, even when frequency detuning is present, the spurious of the frequency conversion carrier and the reproduced carrier is suppressed, so that the code error rate does not deteriorate due to spurious interference as in the related art. ,
An extremely good demodulation of a digital modulation wave can be performed.

FIG. 3A shows an AFC up-converter 28.
A specific example will be described. Input terminals 401, 40
Signals from the data conversion circuits 26 and 27 are input to 2 respectively. These signals are 0-insertion circuits 403, 405
Is inserted at every 2 fs clock, and supplied to the low-pass filters (LPF) 404 and 406, respectively. LP
F404 and 406 are filters having characteristics that sufficiently suppress spurious in the frequency pull-in range of the AFC loop.
The outputs whose spurious components have been sufficiently suppressed by the LPFs 404 and 406 are supplied to the complex multiplier 8 from output terminals 407 and 408.

FIG. 2 shows a second embodiment of the present invention. The same parts as those in the circuit of FIG. 1 described above are denoted by the same reference numerals. In this embodiment, carrier regeneration is performed using only the PLL. The QPSK modulated wave introduced into the input terminal 1 is distributed and supplied to the in-phase detector 2 and the quadrature detector 3. The local oscillations applied to the detectors 2 and 3 are obtained by dividing the fixed-frequency local oscillation from the local oscillator 5 into the 0-degree local oscillation and the 90-degree local oscillation by the distributor 4. Detector 2,
3 are input to A / D converters 6 and 7, respectively.
It is converted into a digital value by a clock having a frequency of 2 fs which is twice the symbol rate supplied from the clock recovery circuit 12. Here, the digitized detection output is output from the complex multiplier 8.
Is input to The complex multiplier 8 operates with a clock of 2 fs, and a local output from the up-converter 29 is used as a reproduction carrier. Outputs of the I-axis component and the Q-axis component obtained from the complex multiplier 8 are input to digital low-pass filters (LPFs) 9 and 10 having the same frequency transfer characteristics, and are spectrally shaped. These digital low-pass filters 9 and 10 are filters for forming transfer characteristics required for preventing intersymbol interference in digital data transmission, and generally provide a so-called roll-off characteristic when combined with filter characteristics on the transmission side. It is designed to be Therefore, in the outputs of the digital low-pass filters 9 and 10, each detection output is spectrally shaped so that the eye opening ratio becomes sufficiently large. The output of each of the digital low-pass filters 9, 10 is
One is divided into two and the other is supplied to the clock recovery circuit 12. Here, the symbol timing component in the signal is extracted, and the clock of the symbol rate frequency fs and 2
Output the clock of fs. The outputs of the digital low-pass filters 9 and 10 are input to the latch circuit 13,
The I-axis component and the Q-axis component are each latched by the clock of fs, and are led out to the output terminals 14 and 15 as demodulated data.

Further, the output of the latch circuit 13 is supplied to a phase detector 30, and the phase difference between the input signal and the oscillation signal of the numerically controlled oscillator 22 is detected. The operation from the latch circuit 13 to the data conversion circuits 23 and 24 to be described later is operated by the clock of fs. The phase difference information from the phase detector 30 is input to the frequency control terminal of the numerically controlled oscillator 22 via the loop filter 31 for carrier recovery. The numerically controlled oscillator 22 is a cumulative addition circuit that does not inhibit overflow, and performs an addition operation up to its dynamic range in accordance with the value of the signal input to the frequency control terminal. To change. That is, a voltage controlled oscillator (VCO) in an analog circuit
Works exactly like. The difference from a general VCO is that its oscillation frequency is very stable.
It is characterized by a stability higher than that of a VCO (VCXO) using a so-called crystal and a wide frequency variable range that cannot be realized by the VCXO. The output of the numerically controlled oscillator 22 is input to data conversion circuits 23 and 24, converted into sine and cosine characteristic signals, and supplied to a PLL up-converter 29. In the PLL up-converter 29, the signal having the sine and cosine characteristics is increased to a clock of 2 fs, passed through an LPF that sufficiently suppresses the spurious in the PLL pull-in range, and then supplied to the complex multiplier 8. This loop is a completely digital PLL, and the PLL
A stable operation can be expected. In addition, since the spurious in the frequency pull-in range of the PLL is suppressed, the spurious of the reproduced carrier does not disturb and does not deteriorate the code error rate. In addition to this, it goes without saying that the present invention can be variously modified and implemented without departing from the scope of the invention.

[0019]

As described above, according to the present invention,
Even when frequency detuning exists, by sufficiently suppressing the spurious of the frequency conversion carrier and the reproduction carrier,
There is no degradation of the bit error rate due to spurious interference.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view showing a first embodiment of the present invention.

FIG. 2 is a configuration explanatory view showing a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an embodiment of the up-converter according to the present invention and characteristics of spurious suppression.

FIG. 4 is a diagram showing a digital modulation wave demodulation device conventionally considered.

FIG. 5 is a diagram showing a spectrum of a frequency conversion carrier and its spurious.

[Explanation of symbols]

2 ... in-phase detector, 3 ... quadrature detector, 4 ... distributor, 5 ... local oscillator, 6, 7 ... A / D converter, 8 ... complex multiplier,
9, 10 digital low-pass filter, 11 complex multiplier, 12 clock recovery circuit, 13 latch, 16 phase detector, 17 frequency detection circuit, 18 AFC loop filter, 21 PLL loop filter, 22 Numerically Controlled Oscillator, 23 Data Conversion Circuit, 24 Data Conversion Circuit, 25 Numerically Controlled Oscillator, 26 Data Conversion Circuit, 2
7 Data conversion circuit 28 AFC up-converter
29 ... PLL up converter.

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Susumu Komatsu 3-3-9, Shimbashi, Minato-ku, Tokyo Inside Toshiba AV EE Co., Ltd. (56) References JP-A-4-167646 (JP, A JP-A-4-3639 (JP, A) JP-A-5-41717 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (2)

(57) [Claims] 1. A detecting means for obtaining a detection output by multiplying a modulated wave input by a local oscillation frequency signal from a local oscillator, and digitally converting a detection output of the detecting means at a frequency twice as high as a symbol rate. Digital conversion means, multiplying the output of the digital conversion means by a reproduction carrier,
Phase information detecting means for performing phase detection on the multiplied output at the symbol center timing to obtain phase information; smoothing the phase information from the phase information detecting means and supplying it to a numerically controlled oscillator; Into a sine wave to obtain the reproduced carrier, and the sine wave from the carrier generating means is increased in frequency to twice the symbol rate to suppress spurious in a frequency pull-in range of carrier reproduction. An apparatus for demodulating a digitally modulated wave, comprising: a filter unit. 2. A detecting means for obtaining a detection output by multiplying a modulated wave input by a local oscillation frequency signal from a local oscillator, and digitally converting a detection output of the detecting means at a frequency twice as high as a symbol rate. Digital conversion means; frequency conversion means for multiplying the output of the digital conversion means by a frequency conversion carrier to obtain a frequency conversion output; digital low-pass filter means for supplying the output of the frequency conversion means and performing spectrum shaping; Phase detection means for multiplying the output of the digital low-pass filter means and the reproduction carrier and performing phase detection on the multiplied output at symbol center timing to obtain phase information; and smoothing the phase information from the phase detection means. And supplies it to a first numerically controlled oscillator, converts the output of the first numerically controlled oscillator into a sine wave, and Phase lock loop means for obtaining a phase error, frequency error detection means to which the phase information is input, and to detect a frequency error of a predetermined relationship between the frequency of the modulated wave input and the local oscillation frequency signal; Frequency error output from the second numerically controlled oscillator and supplies the same to a second numerically controlled oscillator, and converts the output of the second numerically controlled oscillator into a sine wave. A digital modulation wave demodulation device, comprising: a filter means for increasing a sine wave to a frequency twice as high as a symbol rate and suppressing spurious in a frequency pull-in range of the frequency conversion means.