JPH11103327A - Carrier wave reproducing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain an effective AFC function even in the case of a high multilevel PSK modulating system by detecting the frequency offset direction of an input signal from the output signal of synchronizing detection and position information at the respective signal points of 1st and 2nd delay signals. SOLUTION: This circuit has a frequency error detection circuit 19, with which the outputs of analog/digital(A/D) converters 6 and 7 are inputted and a frequency error is detected and outputted to an N sample integration circuit 16, and 2-multiplication circuit 20 for inputting the output of a CLK reproducing circuit 18 and outputting the double frequency of a reproduced clock to the A/D converters 6 and 7 as a sampling clock. That frequency error detection circuit 19 is composed of a 1st delay circuit 21, 2nd delay circuit 22 and computing element 23. Based on the output signal of synchronizing detection and the position information at the respective signal points of the 1st delay signal delaying that output signal for one-symbol time and the 2nd delay signal delaying the output signal within one-symbol time, the frequency offset direction of the input signal is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a carrier recovery circuit with an AFC function used for a multi-level PSK modulation system.

[0002]

2. Description of the Related Art In a digital radio system, a carrier recovery circuit has conventionally been used in a demodulator. Then, a carrier recovery circuit having an AFC function has been usually used in order to compensate for a change in radio frequency. As such a conventional carrier recovery circuit with an AFC function, for example, a circuit described in JP-A-63-217753 is known.

FIG. 5 shows a block diagram of a demodulator including a carrier recovery circuit. In FIG. 5, a PSK modulated wave input from a signal input terminal 0 is supplied to multipliers 2 and 3. The modulated wave input to the multiplier 2 is a digital control local oscillator 1
The multiplier 2 multiplies the reproduced carrier wave inputted from 3 by the multiplier. The modulated wave input to the multiplier 3 is output from the digital control local oscillator 13 and passes through the 90 ° phase shifter 1 to 9
It is multiplied by a reproduced carrier wave having a phase difference of 0 °.
The output signals of the multipliers 2 and 3 pass through the reduction filters 4 and 5, respectively, and become demodulated baseband signals. The demodulated baseband signal is converted into a digital signal by analog / digital converters 6 and 7.

[0004] The demodulated baseband signal is input to a clock recovery circuit 18, and a demodulated clock synchronized with the modulated wave is output. The output of the clock recovery circuit 18 becomes a sampling clock signal for the analog-to-digital converters 6 and 7.

The outputs of the analog / digital converters 6 and 7 are both input to a quadrant judging circuit 9 and a tan ^-1 θ circuit 8.

The quadrant judging circuit 9 judges quadrant information of the phase θ of the PSK modulated wave from the MSB of the output of the analog / digital converters 6 and 7, and the tan ^-1 θ circuit 8 calculates the arc tangent from the demodulated baseband signal. Then, the phase θ of the PSK modulated wave is determined in the range of 0 ° to 90 ° excluding the quadrant information.

The decoding circuit 10 receives the output of the quadrant judging circuit 9 and the output of the tan ^-1 θ circuit 8, obtains θ from both inputs, discriminates this and outputs it as a digital demodulated signal.

On the other hand, the carrier reproduction PLL feedback circuit 11 receives the output of the tan ^-1 θ circuit 8, reads the deviation of θ from the normal signal point angle, smoothes the deviation, and outputs a carrier phase synchronization control signal. . The output of the carrier feedback PLL feedback circuit 11 is input to the digital control local oscillator 13 through the adder 12, and forms a phase locked PLL loop of the reproduced carrier.

On the other hand, the digital differential detection circuit 15 calculates the difference between the phase error amount of the current input signal and the phase error amount of the input signal one symbol before, and outputs it as frequency error information.

The output of the digital delay detection circuit 15 is smoothed by an N-sample integration circuit 16 and a 1 / N circuit 17 and input as an AFC control signal to a digital control local oscillator 13 through an adder 12 to correct a frequency error. .

The synchronization establishment detecting circuit 14 is a decoding circuit 10
To detect that the synchronization has been established by detecting the reference pattern from the output data, and outputs the detection result to the carrier reproduction PLL feedback circuit 11 and the N-sample integration circuit 16. When the synchronization is established, the carrier reproduction PLL is output.
Turns on the feedback circuit 11 and the N-sample integration circuit 1
6 as a hold, and a carrier reproduction PLL when asynchronous
Turn off feedback circuit 11, N sample integration circuit 1
6 is switched on to switch between the AFC operation and the PLL operation.

The maximum value of the frequency error that can be corrected in the above-described conventional carrier recovery circuit with an AFC function is in a range where the phase shift due to the frequency error generated between one symbol does not exceed half the interval between the symbols. N-phase PS
In the case of K, the symbol rate is set to fs [symbol / se
c], then ± fs / (2N) [Hz] (1).

[0013]

The above-mentioned conventional AFC
The carrier wave reproducing circuit with the function has a problem that the maximum value of the correctable frequency error decreases when the modulation method becomes multi-valued. The reason is that the maximum value of the frequency error that can be corrected because the frequency error information is obtained from the phase shift information from the normal signal point as shown by the equation (1) is caused by the frequency error generated between one symbol. This is because the maximum value of the frequency error that can be corrected decreases as N increases, since the phase shift does not exceed half the interval between the symbols.

As described above, the present invention provides a high multi-valued PSK.
Effective AFC function can be maintained for the modulation method.
An object is to provide a carrier recovery circuit with an AFC function.

[0015]

According to a first aspect of the present invention, there is provided a carrier recovery circuit for synchronously detecting a digitally modulated input signal and compensating for a frequency offset of the input signal. In the carrier recovery circuit having the AFC means, the AFC means delays the output signal within one symbol time, the output signal of the synchronous detection, a first delay signal obtained by delaying the output signal by one symbol time, and It is characterized by comprising a detecting means for detecting the direction of the frequency offset of the input signal based on the position information of each signal point of the second delay signal.

According to a second aspect of the present invention, the detecting means determines that a signal point position of the first delay signal on the phase plane is a first point from the output signal to the second delay signal.
, The frequency offset is positive when the frequency offset exists on the right side with respect to the vector direction, and negative when the frequency offset exists on the left side.

According to a third aspect of the present invention, the detecting means includes a position information of a third delay signal calculated by a position information of the output signal and the position of the second delay signal, and a signal of the first delay signal. A sign of an outer product of a second vector with a point and the first vector is detected.

According to a fourth aspect, the detecting means includes:
Position information on the phase plane of the input signal, the first delay signal, and the second delay signal is respectively (I ₀ , Q ₀ ),
If (I _{1 / N} , Q _{1 / N} ), (I ₁ , Q ₁ ) (where N is an integer of 2 or more), S = {I _{1 / N} −K (I ₀ +
I ₁ )｝ (Q ₀ −Q ₁ ) + ｛Q _{1 / N} −K (Q ₀ +
Q ₁ )｝ (I ₁ −I ₀ ) (where K is the value of T / N of the impulse response of the filter system, and T is the symbol frequency). When the sign is positive, the frequency offset becomes negative. , Is detected when the frequency offset becomes positive when the sign is negative.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a carrier recovery circuit with an AFC according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of a demodulation device including a carrier recovery circuit with AFC of the present invention. In FIG. 1, 90
° Phase shifter 1, multipliers 2, 3, low-pass filters 4, 5, analog-to-digital converters 6, 7, tan ^-1 θ circuit 8, quadrant judging circuit 9, decoding circuit 10, PLL for carrier reproduction
The feedback circuit 11, the adder 12, the digital control local oscillator 13, the synchronization establishment detecting circuit 14, the N sample integrator 16, the 1 / N circuit 17, and the CLK reproducing circuit 18 are the same as those in FIG. Therefore, a detailed description is omitted here.

In the present invention, in addition to the above configuration, the output of the analog-to-digital converters 6 and 7 is used as an input, and a frequency error detecting circuit 19 for detecting a frequency error and outputting it to the N sample integrator 16 and a CLK reproducing circuit 18 A doubling circuit 20 which receives an output as an input and outputs a frequency twice as high as the reproduction clock to the analog-digital converters 6 and 7 as a sampling clock.

Next, a detailed configuration of the frequency error detection circuit 19 will be described. FIG. 2 is a block diagram of the frequency error detection circuit 19 according to the embodiment of the present invention. In FIG. 2, the frequency error detection circuit 19 includes a first delay circuit 21, a second delay circuit 22, and a calculator 23.

The first delay circuit 21 is a delay circuit constituted by a flip-flop, and delays the outputs I ₁ and Q ₁ of the analog-to-digital converters 6 and 7 by a half symbol time to I _1/2 and Q _{1. / 2} , and the second delay circuit
As in the case of the first delay circuit, the output of the first delay circuit is further delayed by 1/2 symbol time and output as I ₀ and Q ₀ .

These data I ₀ , Q ₀ , I _1/2 ,
Q _1/2 , I ₁ , and Q ₁ are all input to the arithmetic unit 23. The arithmetic unit 23 outputs I ₀ , Q ₀ ,
The following equation is calculated from I ₁ , Q ₁ and I _1/2 , Q _1/2 , and the sign of the resulting S value is output and used as frequency error information.

S = {I _1/2 −K (I ₀ + I ₁ )} (Q ₀ −Q ₁ ) + {Q _1/2 −K (Q ₀ + Q ₁ )} (I ₁ −I ₀ ). 2) Next, the operation of the demodulation device shown in FIG. 1 will be described.

In FIG. 1, a PSK modulated wave input from a signal input terminal 0 is supplied to multipliers 2 and 3. The modulated wave input to the multiplier 2 is multiplied in the multiplier 2 with the reproduced carrier wave input from the digital control local oscillator 13. The modulated wave input to the multiplier 3 is output from the digital control local oscillator 13 and passes through the 90 ° phase shifter 1 to 90 °.
Is multiplied by the given reproduction carrier. The output signals of the multipliers 2 and 3 pass through the reduction filters 4 and 5, respectively, and become demodulated baseband signals. The demodulated baseband signal is converted into a digital signal by analog / digital converters 6 and 7.

The demodulated baseband signal is input to the clock recovery circuit 18, and a demodulated clock synchronized with the modulated wave is output. The output of the clock recovery circuit 18 is 2
Analog-to-digital converters 6 and 7 through multiplication circuit 20
Of the sampling clock signal. The sampling operation will be described below. The symbol rate clock (fs) output from the clock recovery circuit 18 is multiplied by a doubling circuit 20.
Is converted to a 2 fs clock. Since the analog-to-digital converters 6 and 7 are sampled by the 2 fs clock, the sampling points are the symbol timing used in the tan ^-1 θ circuit 8 and the quadrant judging circuit 9 and the timing between the symbols.

The outputs of the analog / digital converters 6 and 7 are both input to the quadrant judging circuit 9 and the tan ^-1 θ circuit 8.

The quadrant judging circuit 9 judges quadrant information of the phase θ of the PSK modulated wave from the MSB of the output of the analog / digital converters 6 and 7, and the tan ⁻¹ θ circuit 8 calculates the arc tangent from the demodulated baseband signal. Then, the phase θ of the PSK modulated wave is determined in the range of 0 ° to 90 ° excluding the quadrant information.

The decode circuit 10 receives the output of the quadrant judging circuit 9 and the output of the tan ^-1 θ circuit 8 as inputs, obtains θ from both inputs, discriminates this and outputs it as a digital demodulated signal.

On the other hand, the carrier reproduction PLL feedback circuit 11 receives the output of the tan ^-1 θ circuit 8, reads the deviation of θ from the normal signal point angle, smoothes the deviation, and outputs a carrier phase synchronization control signal. . The output of the carrier feedback PLL feedback circuit 11 is input to the digital control local oscillator 13 through the adder 12, and forms a phase locked PLL loop of the reproduced carrier.

The frequency error detection circuit 19 receives the outputs of the A / D converters 6 and 7 and outputs them as frequency error information.

The output of the frequency error detection circuit 19 is smoothed by the N-sample integration circuit 16 and the 1 / N circuit 17 and is input as an AFC control signal to the digital control local oscillator 13 through the adder 12 to correct the frequency error. .

The synchronization establishment detecting circuit 14 is a decoding circuit 10
By detecting a reference pattern from the output data, the synchronization is established, and the detection result is output to the N-sample integration circuit 16.

Next, the operation of the frequency error detection circuit 19 will be described in detail with reference to FIG. According to the configuration of FIG.
Inputs I ₁ and Q ₁ , outputs I _1/2 and Q 1 of the first delay circuit 21
_1/2 , outputs I ₀ and Q ₀ of the second delay circuit 22 indicate a current signal point position, a signal point position before T / 2 (T is a symbol period), and a signal point position before T, respectively. .

Here, the demodulation locus of each signal point will be described with reference to FIG. FIG. 3 shows a QPSK signal point arrangement for simplification of the multi-level PSK signal point arrangement.
From the signal point p ₀ at time 0 in the figure shows the trajectory of the up signal points p ₁ at time T after one symbol period. Note that signal points P _{0 to} P ₃ show signal point arrangements in the case where no QPSK frequency offset is received. At this time, the position of the signal at time T / 2 is represented by p _1/2 . Here, the relationship between p ₀ , p _1, and p _1/2 is as follows using the position vectors P ₀ , P ₁ , P _1/2 of the respective points, ignoring the influence from the preceding and following signal points. Is represented by

P _1/2 = K (P ₀ + P ₁ ) (3) Here, K is a value at time T / 2 of the impulse response of the filter system of the transceiver.

Next, the frequency of the reproduced carrier is shifted from the carrier frequency of the modulated wave by a frequency offset f from the specified frequency.
Consider the case where the frequency shift is higher by _d . At this time, the signal that has started moving from p ₀ moves to a position p ₁ ′ rotated counterclockwise by an angle θ with respect to the phase center from p _{1 at} time T due to a shift of the frequency offset f _d . In FIG. 3, this signal point P ₁ ′ is indicated by ●. Here, the relationship between θ and f _d is represented by the following equation.

Θ = f _d × T (4) Similarly, the position of the signal at time T / 2 is from p _1/2 to θ /
Move to p _1/2 'rotated by two. As can be seen from this figure, when the input signal frequency is higher than the specified carrier frequency due to the frequency offset (the frequency offset is referred to as positive).
Trajectory 31 with respect to the locus of the signal points, P ₁ 'from P ₁ to,
It rotates counterclockwise from P _1/2 to P _1/2 'as shown by a locus 32. Conversely, when the frequency is lower than the specified frequency due to the frequency offset (the frequency offset is referred to as negative).
, The trajectory of the signal point rotates clockwise. In this case, the position of the signal point p _1/2 ′ is located on the right side when the frequency offset is positive with respect to the vector P ₀ P ₁ ′ looking at P ₁ ′ from the signal point P ₀ , and conversely, the frequency offset is negative. Is located on the left.

As described above, the signal point P _1/2 ′ is
Whether the frequency offset is higher or lower than the specified frequency can be determined based on whether the frequency offset is on the right side or the left side of the vector P ₀ P ₁ ′.

This relationship can be expressed as follows using a calculation formula. The position of the signal at time T / 2 calculated from p ₀ and p ₁ ′ assuming that there is no frequency shift is p
_1/2 ". Vector P ₀ from signal point P ₀ to P ₁ ′
P ₁ 'was used as a A, p _1/2 from p _1/2 "' vector P to
_{Assuming that 1/2} ″ P _1/2 ′ is B, the following outer product vector is calculated.

A × B (5) Here, the position vectors of p ₀ , p ₁ ′, p _1/2 ′, and p _1/2 ″ are represented by P ₀ = (i ₀ , q ₀ ) and P ₁ ′ = (I ₁ ′,
q ₁ ′ ), P _1/2 '= (i _1/2 ', q _1/2 '),
When P _1/2 ″ = (i _1/2 ″, q _1/2 ″), A × B = (i ₁ ′ −i ₀ ) (q _1/2 ′ −q _1/2 ″) − (q _{1 '-q 0) (i 1/} 2' -i 1/2 ") ... a (6). vector product direction of a × B is notoriously a, B
When they cross at an angle α, the right-handed screw advances. Therefore, when represented by A × B = S (7), when the value of S is negative, B is on the right side of the vector A, and when the value of S is positive, B is on the vector A. Is on the left. As a result, at S <0, P _1/2 ′ is on the right side of the vector P ₀ P ₁ ′, S>
At 0, it can be determined that the vector exists on the left side of the vector P ₀ P ₁ ′.

Next, the signal point P _1/2 "is indicated by P _1/2 (2) equation similar to the P _1/2" because it is _{= K (P 0 + P 1} ') ... (8) Equation (6) is modified as follows.

S = {i _1/2 ′ −K (i ₀ + i ₁ ′)} (q ₀ −q ₁ ′) + {q _1/2 ′ −K (q ₀ + q ₁ ′)} (i ₁ ′) −i ₀ ) (9) where I ₀ and Q ₀ are i ₀ and q ₀ , I ₁ and Q ₁ are i ₁ ′ and q ₁ ′, and I _1/2 and Q _1/2 are i _{1 / 2} ′,
Since it is clear that the signals correspond to q _1/2 ', the expression (2) can be obtained by replacing the symbols in the expression (9).

As a result, the output of the frequency error detection circuit 19 is S> 0 when the frequency offset is negative, and S <0 when the frequency offset is positive.

The output result of the frequency error detection circuit 19 is averaged N times by an N-sample integrator circuit 16 and a 1 / N circuit 17 and then input as an AFC signal through an adder 12 to a digital control local oscillator 13 where the carrier frequency is obtained. The error is corrected.

In the frequency error detecting circuit 19 according to the embodiment of the present invention described above, the QPS
Although K has been described, the frequency offset sign detecting means of the present invention can be similarly applied to, for example, a polyphase PSK or a multilevel QAM modulated signal.

Further, the frequency error detection circuit 19 generates a signal obtained by delaying the input signal by T / 2 in the first delay circuit 21,
The method has been described in which the signal obtained by delaying the input signal by T in the second delay circuit 22 and the frequency offset is obtained.

However, regarding the first delay circuit 21,
The delay is not limited to the T / 2 delay, and may be, for example, T / N (N is an integer of 2 or more).

In this case, a signal obtained by delaying the signals I ₁ and Q ₁ by a 1 / N symbol time by the first delay circuit is I _{1 / N} and Q _{1 / N}
Assuming that the signals delayed by one symbol time in the second delay circuit are I ₀ and Q ₀ , the equation (2) is as follows: S = {I _{1 / N−} K ′ (I ₀ + I ₁ )} (Q ₀ − Q ₁ ) + {Q _{1 / N−} K ′ (Q ₀ + Q ₁ )} × (I ₁ −Q ₀ ) (10) Here, K 'is the T / N value of the filter impulse response.

As a configuration of the frequency error detection circuit 19 when the 1 / N symbol is delayed, for example, a configuration of a block diagram as shown in FIG. 4 is used.

That is, N delay circuits 41 for delaying 1 / N symbol time are connected in series, and the input signals I ₁ and Q ₁ are input to the first delay circuit 41 to obtain a signal delayed by I / N symbol time. I _{1 / N} and Q _{1 / N} are obtained. Further, (N + 1) delay circuits 41 are connected to the output of the first delay circuit 41 to output signals I ₀ and Q _{0 obtained} by delaying the input signals I ₁ and Q ₁ by T symbol times.

The arithmetic unit 42 calculates I ₀ , Q ₀ , I _{1 / N} , Q
_{1 / N} , I ₁ , and Q ₁ are input, and the above (10)
According to the equation, the sign of S is detected.

The maximum value of the frequency error that can be corrected by the above-described configuration is in a range where the phase shift due to the frequency error generated between one symbol and p ₁ ′ does not exceed p ₀ for one symbol. Since the output of the frequency error detection circuit 19 is averaged, the frequency error can be detected if the frequency error can be detected by half or more of all signal points. Therefore, the maximum value of the frequency error is ± fs / 2 [Hz] (11) at which the frequency error can be detected by half of all signal points.

[0054]

An advantage of the present invention is that frequency error information can be efficiently extracted from a high-multilevel PSK modulation system.

The reason is that the frequency error information is extracted not from the deviation from the normal signal point but from the trajectory of two consecutive symbols, so that the frequency error can be detected irrespective of the multilevel number.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a demodulation device including an embodiment of a carrier recovery circuit of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a frequency error detection circuit in FIG. 1;

FIG. 3 is a signal point arrangement diagram showing an operation of the frequency error detection circuit of FIG. 1;

FIG. 4 is a block diagram showing another configuration of the frequency error detection circuit of FIG. 1;

FIG. 5 is a block diagram showing a demodulation device including a conventional carrier recovery circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 90 degree phase shifter 2, 3 Multiplier 4, 5 Reduction filter 6, 7 Analog-digital converter 8 tan ^{-1 (} theta) circuit 9 Quadrant determination circuit 10 Decoding circuit 11 PLL feedback circuit for carrier reproduction 14 Synchronization establishment detection circuit 15 Digital delay detector 16 N sample integration circuit 17 1 / N circuit 18 CLK recovery circuit 19 Frequency error detection circuit 20 Doubler circuit 21, 22 Delay circuit 23 Arithmetic unit

Claims (7)

[Claims] 1. A carrier recovery circuit having a demodulation means for synchronously detecting a digitally modulated input signal and an AFC means for compensating for a frequency offset of the input signal, wherein the AFC means comprises: an output signal of the synchronous detection; A direction of a frequency offset of the input signal is detected based on position information of each signal point of a first delay signal obtained by delaying the output signal by one symbol time and a second delay signal obtained by delaying the output signal within one symbol time. A carrier recovery circuit, comprising: 2. The method according to claim 1, wherein the detecting unit includes:
When the signal point position of the first delay signal is on the right side with respect to the first vector direction from the output signal to the second delay signal, the frequency offset is positive, and is on the left side. 2. The carrier wave recovery circuit according to claim 1, wherein the frequency offset is detected to be negative. 3. The method according to claim 1, wherein the detecting unit calculates a position of the third delay signal and the position information of the third delay signal calculated from the position information of the output signal and the second delay signal. 3. The carrier recovery circuit according to claim 1, wherein a sign of an outer product of a second vector and the first vector is detected. 4. The detecting means according to claim 1, wherein said input signal, said first delay signal, and said second delay signal are position information on a phase plane of (I ₀ , Q ₀ ), (I _{1 / N} , Q _{1 / N} ),
If (I ₁ , Q ₁ ) (where N is an integer of 2 or more), S = {I _{1 / N−} K (I ₀ + I ₁ )} (Q ₀ −Q ₁ ) +
_{{Q 1 / N -K (Q} 0 + Q 1)} (I 1 -I 0) ( where,
K is the value of T / N of the impulse response of the filter system, and T is the symbol frequency). When the sign is positive, the frequency offset is negative, and when the sign is negative, the frequency offset is positive. 4. The carrier wave recovery circuit according to claim 1, wherein the carrier wave is detected by the following. 5. A multiplying means for receiving the digital modulation signal and multiplying the in-phase and quadrature outputs of the VCO output, respectively, and regenerating a clock synchronized with the modulation signal via each of the outputs of the multiplying means via a low-pass filter. A clock regeneration unit; a doubling unit for converting the output of the clock regeneration unit to a double frequency; and an analog-to-digital conversion unit for converting the output of the low-pass filter to a digital signal using the double frequency as a sampling clock. A quadrant judging means for judging quadrant information of a phase of the modulation signal from an MSB of an output of the analog-to-digital conversion means ^; and calculating TAN ^-1 from an output of the analog-to-digital conversion means to detect a phase of the modulation signal. A phase detection unit, a decoder that receives the outputs of the quadrant determination unit and the phase detection unit and outputs a digital demodulated signal Means for detecting a deviation from the normal signal point angle from the output of the phase detection means, and outputting a smoothed carrier phase synchronization control signal; and Frequency error detecting means for outputting a frequency error output indicating the level of a carrier frequency of the modulation signal with respect to a specified frequency; synchronization establishing means for detecting the synchronization of the decoding means output by detecting a reference pattern; and the synchronization establishing means. And N of the output of the frequency error detecting means.
A carrier recovery circuit, comprising: averaging means for taking an average value of times; and control means for controlling the VCO after adding the control signal for carrier phase synchronization and the output of the averaging means. 6. The frequency error detection means includes an output signal of the analog-to-digital conversion means, a first delay signal obtained by delaying the output signal by one symbol time, and a second delay signal obtained by delaying the output signal within one symbol time. 6. The carrier recovery circuit according to claim 5, wherein a frequency offset of the input signal is detected by the predetermined calculation based on position information of each signal point of the second delay signal. 7. The method according to claim 6, wherein the predetermined calculation comprises:
Positions on the phase plane of the first delay signal and the second delay signal
Location information (I₀, Q₀), (I_{1 / N} ,
Q_{1 / N}), (I₁, Q₁(Where N is an integer of 2 or more)
Then, S = ｛I_{1 / N}−K (I₀+ I₁)｝ (Q₀−Q₁) +
｛Q_{1 / N}−K (Q₀+ Q₁)｝ (I₁-I₀) (However,
K is the T / N value of the impulse response of the filter system, and T is
And if the sign is positive, the frequency
If the wave number offset is negative and the sign is negative,
Calculates that the frequency offset is positive
7. The carrier recovery circuit according to claim 5, wherein