JP2808861B2 - Demodulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a demodulator for demodulating a multilevel quadrature amplitude modulation signal, and more particularly to a multilevel quadrature amplitude demodulator suitable for LSI implementation.

(Prior Art) FIGS. 5 and 6 show an example of this type of multilevel quadrature amplitude demodulator.
This will be described with reference to the drawings.

This demodulation device is disclosed in Japanese Patent Application Laid-Open No. 1-158854, and is paired with a multilevel quadrature amplitude modulation device that amplitude-modulates a pair of quadrature carrier signals with a main data signal and outputs a multilevel quadrature amplitude modulation signal. Used in

When the main data signal is an n-bit binary signal, the main data signal can have 2 ⁿ signal values. Then, the multilevel quadrature amplitude modulation signal has 2 ⁿ output signal points on the quadrature phase plane.

To output a pair of quadrature carrier signals, the modulator has an oscillator and a π / 2 phase shifter, as is well known. The multilevel quadrature amplitude modulation signal is sent to a transmitter (not shown). The transmitter performs frequency conversion of the multilevel quadrature amplitude modulation signal and outputs a radio frequency signal in a microwave band. The radio frequency signal is transmitted from a transmitter to a multi-level quadrature amplitude demodulator (hereinafter, simply referred to as a demodulator).

The radio frequency signal is received by a receiver (not shown) and converted into an intermediate frequency multi-level quadrature amplitude modulated signal.

In FIG. 5, the demodulation device receives a multilevel quadrature amplitude modulation signal as a demodulation device input signal AM having an input signal phase. The demodulator input signal AM has 2 ⁿ received signal points that correspond one-to-one to the output signal points described above. The demodulation device demodulates the demodulation device input signal AM and outputs an in-phase side demodulation signal ID and a quadrature side demodulation signal QD. The demodulation device includes a processing unit 10 that processes the demodulation device input signal AM and outputs an in-phase processing signal IDS and a quadrature processing signal QDS.

The processing unit 10 has a quadrature detector 11 that receives the demodulation device input signal AM. The quadrature phase detector 11 performs phase detection of the demodulator input signal AM using the first and second local carrier signals. In order to output the first and second local carrier signals,
The quadrature detector 11 has a π / 2 phase shifter (not shown).
The π / 2 phase shifter receives a reference carrier signal having a fixed frequency from the reference carrier oscillator 12 and outputs a first local carrier signal and a second local carrier signal having a quadrature phase difference with respect to this signal. . Here, the demodulator input signal AM has a phase shift of φ (radian) with respect to the reference carrier signal.

The phase detection signal and the quadrature phase detector 11 respectively output the in-phase baseband signal IBS and the quadrature baseband signal QBS,
The signals are supplied to the in-phase side low-pass filter 13 and the quadrature-side low-pass filter.
The in-phase baseband signal IBS can have 2 ^{n / 2} levels depending on the input signal phase as the in-phase signal level. The orthogonal baseband signal QBS can have 2 ^{n / 2} levels depending on the input signal phase as the orthogonal signal level. The in-phase side low pass filter 13 and the quadrature side low pass filter 14 output the in-phase side filtered signal and the quadrature side filtered signal to the in-phase side A / D converter 15 and the quadrature side A / D converter 16, respectively. In-phase A / D converter 15, quadrature A / D converter
16 operates as a well-known multi-value discriminator, and converts the in-phase conversion signal and the quadrature-side conversion signal into in-phase digital filters
17. Output to orthogonal digital filter 18. The in-phase side digital filter 17 and the quadrature-side digital filter 18 perform digital filtering of the in-phase side converted signal and the quadrature side converted signal by a known method called roll-off shaping, respectively, and convert the in-phase side digital filtered signal into the in-phase side processed signal. ID
Then, the quadrature side digital filtered signal is output as the quadrature side processed signal QDS, respectively. The in-phase processing signal IDS and the quadrature processing signal QDS have an in-phase component and a quadrature phase component, respectively. The phase control circuit 19 controls the in-phase phase component and the quadrature phase component by the method described below.

 The phase control circuit 19 will be described with reference to FIG.

The phase control circuit 19 is for performing phase rotation of the in-phase processing signal IDS and the quadrature processing signal QDS on the phase plane about the origin by detecting the phase shift φ.

The phase control circuit 19 includes an in-phase side demodulation signal ID and a quadrature side demodulation signal.
It has a control unit 190 that receives the QD. As shown in the aforementioned publication, the control unit 190 detects the phase shift φ and
It outputs first and second control signals representing φ and cosφ. The first multiplier 191 outputs the first control signal and the in-phase processing signal IDS.
And outputs a first product signal representing a first product between sinφ and the in-phase side signal level. The second multiplier 192 is
Upon receiving the first control signal and the quadrature-side processed signal QDS, a second product signal representing a second product between sinφ and the quadrature-side signal level is output.

The third multiplier 193 receives the second control signal and the in-phase processing signal IDS and outputs a third signal between cos φ and the in-phase signal level.
And outputs a third product signal representing the product of. Fourth multiplier 194
Receives the second control signal and the quadrature-side processed signal QDS, and
A fourth product signal representing a fourth product between φ and the orthogonal signal level is output.

The adder 195 receives the second and third product signals, and receives the second and third product signals.
, And outputs an addition signal representing these addition values. The subtractor 196 receives the first and fourth product signals, performs subtraction between the first and fourth products, and outputs a subtraction signal representing the subtraction value. By the above calculations, the in-phase side demodulation signal ID and the quadrature side demodulation signal QD have the in-phase side control phase and the quadrature side control phase that match the input signal phase, respectively. Thus, the phase control circuit 19 can remove the phase shift φ, and reproduces the in-phase side demodulated signal ID and the quadrature side demodulated signal QD at a certain code error rate.

By the way, in order to reduce the cost and volume of the demodulation device and stabilize the performance, the phase control circuit 19, the combination of the in-phase A / D converter 15 and the quadrature-side A / D converter 16 and the in-phase The combination of the side digital filter 17 and the orthogonal side digital filter 18 is realized by an LSI. Such a demodulator is called an LSI demodulator.

(Problems to be Solved by the Invention) However, in the conventional demodulator, if a quadrature phase shift, that is, a quadrature shift α (radian) occurs between the first and second local carrier signals, the code error rate is reduced. Deterioration becomes remarkable. The quadrature phase shift α is caused by the performance of the π / 2 phase shifter in the quadrature detector 11. This is because the π / 2 phase shifter is affected by fluctuations in ambient temperature and aging. The conventional phase control circuit 19 does not have a function of removing the quadrature phase shift α as described above. Therefore, π / 2
The phase shifter must be strictly designed to be free from the effects of ambient temperature fluctuations and aging.
There is a disadvantage that the cost of the demodulation and demodulation device is increased.

Therefore, an object of the present invention is to provide a demodulator capable of compensating for a quadrature phase shift in a quadrature detector.

Another object of the present invention is to provide a demodulation device suitable for LSI implementation.

(Means for Solving the Problems) The present invention is an apparatus for demodulating a quadrature amplitude modulation signal obtained by quadrature amplitude modulation of a main data signal into an in-phase side demodulation signal and a quadrature side demodulation signal. A processing unit for processing the signal to output an in-phase processing signal having an in-phase component and a quadrature processing signal having a quadrature phase component; and receiving the in-phase processing signal and the quadrature processing signal and receiving the in-phase processing signal. A common-mode phase control unit that controls the common-mode phase component in response to a common-mode control signal and outputs a common-mode phase control signal including a common-mode data signal and a common-mode error signal as the common-mode demodulated signal; Receiving the side processing signal and the quadrature processing signal, controlling the quadrature phase component according to the quadrature control signal, and demodulating the quadrature phase control signal including the quadrature data signal and the quadrature error signal into the quadrature demodulation. As a signal A quadrature-side phase control unit that receives and outputs the in-phase error signal and the quadrature-side data signal, and outputs an in-phase multiplication signal obtained by multiplying the received signals as the in-phase control signal; A quadrature multiplier for receiving the quadrature error signal and the in-phase data signal and multiplying the quadrature error signal and the in-phase data signal to output a quadrature multiplication signal as the quadrature control signal.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS.

This demodulator is a quasi-synchronous demodulator, and the processing unit 10
Has the same function as the processing unit 10 shown in FIG.

Here, it is assumed that each of the in-phase processing signal IDS and the quadrature processing signal QDS has a phase difference of θ (radian) between the demodulator input signal AM and the reference carrier signal. In this case, the in-phase processing signal IDS and the quadrature processing signal QDS respectively receive the in-phase baseband signal IBS and the quadrature baseband signal QBS which are the outputs of the quadrature phase detector 11,
Since they are orthogonal to each other, the in-phase processing signal IDS is sin
θ and the quadrature side processing signal QDS are cos θ. However, since the demodulator input signal AM has a multi-level amplitude component, the in-phase processing signal IDS and the quadrature processing signal QDS actually have amplitude components, but do not affect the following description. Treat as unit amplitude. The phase difference θ will be described later, and includes a modulation phase component (m), a phase rotation component (2πΔft) generated at a difference frequency between the center frequency of the demodulator input signal AM and the reference carrier signal, and a quadrature phase shift (α). In. The components excluding the necessary information (m) are removed by the in-phase phase controller 20 and the quadrature-side phase controller 21 as described later.

The demodulation device includes an in-phase phase controller 20, a quadrature-side phase controller 21, an in-phase multiplier 22, and a quadrature-side multiplier 23. As will be described later, the in-phase phase controller 20 and the quadrature-side phase controller 21 each operate as an infinite phase shifter. The in-phase phase controller 20 and the quadrature-side phase controller 21 are
It is realized by a digital type infinite phase shifter suitable for the implementation. The in-phase side phase controller 20 is supplied with the in-phase side control signal generated by the in-phase side multiplier 22 in addition to the in-phase side processing signal IDS and the quadrature side processing signal QDS. The quadrature phase controller 21 is supplied with the quadrature control signal generated by the quadrature multiplier 23 in addition to the in-phase processing signal IDS and the quadrature processing signal QDS.

As will be described later in detail, the in-phase controller 20 outputs an in-phase control signal as the in-phase demodulated signal ID.
Similarly, the quadrature-side phase controller 21 outputs the quadrature-side phase control signal as the quadrature-side demodulated signal QD. The in-phase side demodulation signal ID and the quadrature side demodulation signal QD are each the first (most significant bit)
To (n + x) -th (least significant bit) from (n + x) parallel bits (where x is a natural number). The in-phase side demodulation signal ID includes an in-phase side data signal represented by first to n-th bits and an in-phase side error signal represented by (n + 1) to (n + x) bits. The quadrature-side demodulated signal QD is
To the n-th bit and the (n +
1) to the quadrature-side error signal represented by the (n + x) -th bit.

As is well known, the received signal point of the demodulator input signal AM is
It is inevitable that a position shift, that is, a phase shift, from each output signal point in the multilevel quadrature amplitude modulation signal occurs. Each of the in-phase error signal and the quadrature error signal generally indicates the position shift.

These signals are described in, for example, JP-A-62-279757.
(Hereinafter, referred to as a gazette). Simply put, the control signal is generated when the in-phase processing signal IDS causes a phase rotation from a normal state and causes a phase shift with a signal that performs the same operation as C2 in FIG. If the infinite phase shifter included in the phase controller 20 is controlled by this signal, the infinite phase shifter attempts to compensate for the above-described phase shift, so that the in-phase processing signal IDS can be returned to a normal state. The normal state refers to a state in which an input signal is correctly demodulated without a phase shift, for example, a state in which a signal point is located at a circle in FIG.

The in-phase multiplier 22 receives the in-phase error signal and the quadrature data signal, multiplies them, and outputs the in-phase multiplication signal as an in-phase control signal. On the other hand, the quadrature-side multiplier 23 receives the quadrature-side error signal and the in-phase data signal, multiplies them, and outputs the result as a quadrature-side multiplication signal and a quadrature-side control signal.

This signal is a signal that performs the same operation as, for example, C1 in FIG. 4 in the above publication, and generates a control signal when the quadrature processing signal QDS causes a phase rotation from a normal state and causes a phase shift. If the infinite phase shifter included in the phase controller 21 is controlled by this signal, the quadrature processing signal QDS can be returned to a normal state because the infinite phase shifter operates to compensate for the phase shift.

The in-phase controller 20 receives the in-phase control signal and operates so that the in-phase error signal has a minimum value. Similarly, the quadrature phase controller 21 receives the quadrature control signal and operates so that the quadrature error signal has the minimum value.

The in-phase phase controller 20 and the quadrature phase controller 21 will be described with reference to FIG. The in-phase side phase controller 20 has an in-phase side logic processing circuit 25 that receives an in-phase side control signal.

As described later in detail, the in-phase side logic processing circuit 25
The first and second in-phase coefficient signals representing the first and second in-phase variable values given by cos β and sin β are output. The first in-phase multiplier 26 is supplied with the in-phase processed signal IDS and the first in-phase coefficient signal, and multiplies sin θ and cos β to obtain a first in-phase multiplication value sin θ · cos β. Output the in-phase side multiplication signal of. Similarly, the second in-phase multiplier 27 is supplied with the quadrature-side processed signal QDS and the second in-phase coefficient signal, and
multiplies osθ and sinβ to obtain a second in-phase multiplication value cos
A second in-phase multiplication signal representing θ · sin β is output.

The first and second in-phase multiplication signals are supplied to an in-phase adder 28. The in-phase side adder 28 outputs a first in-phase side multiplication value sin θ
Add the cos β and the second in-phase multiplication value cos θ · sin β, and output an in-phase addition signal representing the in-phase addition value given by (sin θ · cos β + cos θ · sin β). By the way, (sinθ · cosβ + cosθ · sinβ) is sin (θ + β)
In-phase control signal (θ + β) (radian)
In-phase control phase. This means that the first and second in-phase multipliers 26 and 27 respectively have first and second in-phase variable values cos
Giving β and sinβ means that the in-phase control phase is variable.

The above description also applies to the quadrature phase controller 21. The quadrature phase controller 21 includes a quadrature logic processing circuit 30, first and second quadrature multipliers 31, 32, and a quadrature subtracter 33.

As will be described later, the orthogonal side logic processing circuit 30 calculates cosγ, s
The first and second orthogonal coefficient signals representing the first and second orthogonal variable values given by inγ are output. The first orthogonal side multiplier 31 is supplied with the orthogonal side processing signal and the first orthogonal side coefficient signal, and performs multiplication of cos θ and cos γ to obtain a first orthogonal side multiplier cos θ · cos γ An orthogonal multiplication signal is output. Similarly, the second quadrature-side multiplier 32 is supplied with the in-phase processing signal and the second quadrature-side coefficient signal, and performs multiplication of sinθ and sinγ to represent a second quadrature-side multiplication value sinθ · sinγ. The second orthogonal multiplication signal is output.

The first and second orthogonal multiplication signals are supplied to the orthogonal subtractor 33. The orthogonal side subtractor 33 calculates the first orthogonal side multiplied value cos θ
Subtracting cosγ from the second orthogonal multiplier sinθ · sinγ to output an orthogonal subtraction signal representing an orthogonal subtraction value given by (cosθ · cosγ−sinθ · sinγ).

To summarize, the same-side multiplier 22 and the orthogonal-side multiplier
An infinite phase shifter including first and second in-phase multiplication shifts 26 and 27 and an in-phase adder 28, and first and second quadrature multipliers 31 and 32 and a quadrature subtractor 33 by the control signal from 23. In order to control the infinite phase shifter, a signal conversion circuit is necessary, so that an in-phase side logic processing circuit 25 and a quadrature side logic processing circuit 30 are provided. The in-phase side logic processing circuit 25 and the quadrature side logic processing circuit 30 have the same function and can interface with an infinite phase shifter as an output.
It outputs sinφ and cosφ (φ is a substantially continuous value of 0 to 2π). Note that both β and γ described above are substantially the same as substantially continuous values of 0 to 2π (of course, the same applies to φ).
When the circuit operates, the control amounts of the infinite phase shifters on the quadrature side and the in-phase side are different, so different symbols are used for convenience.

By the way, (cosθ · cosγ−sinθ · sinγ) is cos
(Θ + γ), and the quadrature phase control signal is (θ + γ)
(Radian) orthogonal control phase. This is the first,
By giving the first and second orthogonal variable values cosγ and sinγ to the second orthogonal multipliers 31 and 32, respectively, it means that the orthogonal control phase is variable.

Incidentally, the phase difference θ is represented by (m + 2πΔft) (where m is the modulation phase component, and Δf is the demodulator input signal AM
And the frequency of the reference carrier signal). Now, assuming that a quadrature phase shift α exists in the quadrature phase detector 11, the in-phase control signal is sin (m + 2πΔf
t), the quadrature phase control signal is represented by cos (m + 2πΔft + α). Here, the in-phase multiplier 22 outputs a control signal corresponding to a phase shift of 2πΔft, and the quadrature-side multiplier 23 outputs (2πΔft
+ Α), respectively. Therefore, if the circuit shown in FIG. 1 is configured, the in-phase side controller 22 and the quadrature-side phase controller 23 respectively control the in-phase side phase controller 20 and the quadrature side phase controller 21 so that these phase shifts become zero. By controlling, the phase shift is compensated. As a result, the normal data signals ID and Q having no phase shift of sin (m) as the in-phase side control signal and cos (m) as the quadrature side phase control signal.
D can be played.

Thus, according to the present invention, the in-phase processing signal IDS,
The quadrature-side processed signal QDS is compensated for phase shift by the in-phase multiplier 22, the quadrature-side multiplier 23, and the in-phase side phase controller 20 and the quadrature-side phase controller 21 which are independently provided control signal generators. Therefore, it is possible to compensate for a quadrature phase shift α that is not a phase shift common to the in-phase processing signal IDS and the quadrature processing signal QDS.

In the above description, the in-phase multiplier 22 is supplied with (n + 1) to (n + x) bits of the in-phase demodulated signal and the first to n-th bits of the quadrature-side demodulated signal. Only the (n + 1) bits of the in-phase side demodulated signal and the first bit of the quadrature side demodulated signal may be supplied. The reason is shown in the above-mentioned publication. This also applies to the orthogonal multiplier 23.

The in-phase side logic processing circuit 25 will be described with reference to FIG. The in-phase side logic processing circuit 25 has an additional in-phase side adder 34 to which the in-phase side delay signal and the in-phase side control signal are supplied. The in-phase side adder 34 calculates an in-phase side accumulated value between the in-phase side delay signal and the in-phase side control signal, and outputs an in-phase side accumulated signal representing the same in a series of time slots. That is, the in-phase side accumulated signal has a plurality of bits constituting 1
Accommodated in one time slot. The in-phase delay unit 35
Upon receiving the in-phase accumulated signal, the signal is delayed by one time slit and output as an in-phase delayed signal. The first in-phase coefficient signal generator 36 receives the in-phase accumulated signal,
A first common-mode coefficient signal representing a first common-mode variable value given by β is output. The second in-phase coefficient signal generator 37 receives the in-phase accumulated signal and outputs a second in-phase coefficient signal representing a second in-phase variable value given by sinβ.

The first and second common-mode coefficient signal generators 36 and 37 are provided with a ROM
(Read only memory). If the in-phase side accumulated signal consists of 8 bits, the first in-phase side coefficient signal generator 36 obtains 256 kinds of first types of 256 obtained by equally dividing the range of sin0 to sin2π by 256 (= 2 ⁸ ). In-phase variable values are stored in advance.

In consideration of the above points, the in-phase side logic processing circuit 25 functions as a voltage control transmitter. Assuming that the in-phase processing signal IDS
Has a quadrature phase shift α, the in-phase control signal has a certain value. As a result, the in-phase accumulated value of the in-phase accumulated signal increases at a speed corresponding to the quadrature phase shift α. Subsequently, the first and second in-phase multipliers 26 and 27 independently use the first and second in-phase coefficient signals at the above-mentioned speed to generate the in-phase processed signal ID.
S, performs phase rotation of the quadrature processing signal QDS. As a result of such a phase rotation, the in-phase controller 20 operates so that the in-phase control signal has a minimum value, thereby removing the quadrature phase shift α.

 The above description also applies to the orthogonal logic processing circuit 30.

Referring to FIG. 4, the orthogonal side logic processing circuit 30 has an additional orthogonal side adder 38 to which an orthogonal side delay signal and an orthogonal side control signal are supplied. The quadrature adder 38 calculates a quadrature cumulative value between the quadrature delay signal and the quadrature control signal, and outputs a quadrature cumulative signal representing this value in a series of time slots. The orthogonal delay section 39 receives the orthogonal accumulated signal, delays this signal by one time slot, and outputs the resultant signal as an orthogonal delayed signal. The first orthogonal coefficient signal generator 41 receives the orthogonal accumulated signal and outputs a first orthogonal coefficient signal representing a first orthogonal variable value given by cosγ. Second
The orthogonal coefficient signal generator 42 receives the orthogonal accumulated signal,
A second orthogonal coefficient signal representing a second orthogonal variable value given by nγ is output.

As described above, the present invention has been described with reference to the preferred embodiments.
The present invention is capable of various modifications. For example, the in-phase controller 20 and the quadrature controller 21 may be realized by an analog type infinite phase shifter. In this case, the in-phase controller 20 and the quadrature controller 21 What is necessary is just to arrange it before the digital filter 17 on the side and the digital filter 18 on the orthogonal side.

(Effects of the Invention) As described above, according to the present invention, since the phase control unit using the infinite phase shifter is provided on each of the in-phase side and the quadrature side, and the control signals are independently supplied,
Even if a quadrature phase shift occurs in the quadrature detector, this can be automatically compensated. Further, since the infinite phase shifter can be of a digital type, it is possible to provide a demodulator having a configuration that can be easily integrated into an LSI.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
FIG. 2 is a block diagram showing the configuration of the in-phase side phase controller and quadrature-side phase controller shown in FIG. 1, and FIG. 3 shows the configuration of the in-phase side logic circuit shown in FIG. FIG. 4 is a block diagram showing the configuration of the orthogonal logic processing circuit shown in FIG. 2, FIG. 5 is a block diagram showing an example of a conventional demodulator, and FIG. FIG. 2 is a block diagram of the phase control circuit shown in FIG. In the figure, 10 is a processing unit, 26 and 27 are first and second in-phase multipliers, 28 is an in-phase adder, 31 and 32 are first and second quadrature multipliers, and 33 is quadrature subtraction. vessel.

Claims (6)

(57) [Claims] An apparatus for demodulating a quadrature amplitude modulation signal obtained by quadrature amplitude modulation of a main data signal into an in-phase side demodulation signal and a quadrature side demodulation signal. A processing unit for outputting an in-phase processing signal having a quadrature-side processing signal and a quadrature-side processing signal having a quadrature-side phase component, and receiving the in-phase processing signal and the quadrature-side processing signal and receiving the in-phase processing signal in response to the in-phase control signal. An in-phase side control section for controlling an in-phase side component and outputting an in-phase side phase control signal comprising an in-phase side data signal and an in-phase side error signal as the in-phase side demodulated signal; and the in-phase side processing signal and the quadrature side processing. A quadrature-side phase that receives the signal and controls the quadrature-side phase component according to the quadrature-side control signal and outputs a quadrature-side phase control signal composed of a quadrature-side data signal and a quadrature-side error signal as the quadrature-side demodulated signal A common-mode multiplier that receives the common-mode error signal and the quadrature-side data signal and multiplies them to output a common-mode multiplied signal as the common-mode control signal, and the quadrature-side error signal. A demodulator comprising: a quadrature multiplier that receives the in-phase data signal and multiplies the quadrature multiplied signal and outputs the quadrature multiplied signal as the quadrature control signal. 2. The quadrature detector according to claim 1, wherein said processing section performs quadrature phase detection on the quadrature amplitude modulation signal and outputs an in-phase baseband signal and a quadrature baseband signal. An in-phase low-pass filter that filters the in-phase baseband signal and outputs an in-phase filtered signal; and a quadrature-side low-pass filter that filters the quadrature baseband signal and outputs a quadrature filtered signal. And an in-phase side A- which receives the in-phase side filtered signal and converts it into an in-phase side digital signal.
A D-converter, a quadrature-side A / D converter that receives the quadrature-side filtered signal and converts the quadrature-side digital signal into a quadrature-side digital signal, and receives the in-phase side digital signal and converts it into an in-phase side digital filtered signal to convert the in-phase side processed signal And a quadrature digital filter that receives the quadrature digital signal, converts the quadrature digital signal into a quadrature digital filtered signal, and outputs it as the quadrature processing signal. 3. The demodulating apparatus according to claim 1, wherein said in-phase control section receives said in-phase control signal and displays first and second in-phase variable values. An in-phase side logic circuit that outputs a side-coefficient signal; and a first inter-phase signal between the in-phase side component and the first in-phase side variable value upon receiving the in-phase side processed signal and the first in-phase side coefficient signal. A first in-phase multiplier for outputting a first in-phase multiplication signal representing an in-phase product; and receiving the quadrature processing signal and the second in-phase coefficient signal to receive the quadrature phase component and the second And a second in-phase multiplier for outputting a second in-phase multiplication signal representing a second in-phase multiplication signal between the in-phase side variable value and the first and second in-phase side multiplication signals. An in-phase side adder for outputting a first in-phase side addition signal representing a sum of the first and second in-phase side products. Demodulator for. 4. The demodulator according to claim 1, wherein said quadrature-side phase control unit receives said quadrature-side control signal and represents first and second quadrature values representing first and second quadrature-side variable values. A quadrature-side logic circuit that outputs a side-coefficient signal; and a first logic circuit that receives the quadrature-side processed signal and the first quadrature-side coefficient signal and performs a first operation between the quadrature-side phase component and the first quadrature-side variable value. A first quadrature-side multiplier that outputs a first quadrature-side multiplication signal representing a quadrature-side product of the first and second quadrature-side processing signals and the second quadrature-side coefficient signal. A second orthogonal side multiplier for outputting a second orthogonal side multiplication signal representing a second orthogonal side product between the second orthogonal side variable value and the first orthogonal side variable value;
A demodulator for receiving a second orthogonal multiplication signal and outputting a first orthogonal subtraction signal representing a difference between the first and second quadrature products. 5. The demodulator according to claim 3, wherein said in-phase side logic circuit receives an in-phase side delay signal and said in-phase side control signal, and accumulates them to generate an in-phase side accumulated signal representing an in-phase side accumulated value. An additional in-phase side adder for receiving the in-phase side accumulated signal, receiving the in-phase side accumulated signal and delaying the same by a predetermined time, outputting a signal as the in-phase side delayed signal, and receiving the in-phase accumulated signal. A first in-phase coefficient signal generator for outputting the first in-phase coefficient signal having the first in-phase variable value determined by the in-phase cumulative value; And a second in-phase coefficient signal generator for outputting the second in-phase coefficient signal having the second in-phase variable value determined by the side accumulated value. 6. The quadrature logic circuit according to claim 4, wherein said quadrature logic circuit receives the quadrature delay signal and said quadrature control signal, and accumulates the quadrature delay signal and quadrature control signal. An additional quadrature-side adder that outputs the quadrature-side accumulated signal, a quadrature-side delay circuit that receives the quadrature-side accumulated signal and delays the signal by a predetermined time and outputs the signal as the quadrature-side delayed signal, A first orthogonal coefficient signal generator for outputting the first orthogonal coefficient signal having the first orthogonal transform value determined by the orthogonal cumulative value, and And a second orthogonal coefficient signal generator for outputting the second orthogonal coefficient signal having the second orthogonal variable value determined by the side cumulative value.