JP2513327B2 - Digital demodulator - Google Patents

Description

The present invention relates to a digital demodulator for synchronously detecting a quadrature amplitude modulation wave.

[Conventional technology]

In recent years, in order to put various microwave digital transmission systems into practical use, a large number of digital demodulation devices adapted to them have been developed. One of them is a digital demodulator for synchronously detecting a quadrature amplitude modulated wave, and an example thereof is shown in FIG.

In FIG. 3, 1 is a quadrature phase detector (QAM DET),
2 is a fixed reference carrier oscillator (LO), 3 and 4 are low-pass filters (L)
PF), 5 and 6 are multilevel discriminators (A / D), and 7'is a transversal equalizer (TRSV EQL).

An input signal which is a quadrature amplitude modulation wave enters a quadrature phase detector 1, where a quadrature phase detection is performed by a fixed reference carrier from a fixed reference carrier oscillator 2 to obtain quasi-synchronized demodulation signals P and Q. The quasi-synchronized demodulation signals P and Q include a phase rotation component of 2πΔf. However, the difference frequency Δf is expressed by the following equation.

Δf = f _c −f _{LO in the} equation, f _c is the center frequency of the input signal, and f _LO is the fixed reference carrier frequency.

These quasi-synchronized demodulated signals P and Q signals are input to multi-level discriminators 5 and 6 via low-pass filters 3 and 4 for waveform shaping, and converted into multi-bit data signals here.

The transversal equalizer 7'connected to the multi-level discriminators 5 and 6 is of a digital processing type, and is composed of a multi-tap weighting circuit for the real axis part and a multi-tap weighting circuit for the imaginary axis part, It has the ability to compensate for the phase rotation component of 2πΔf described above. Therefore, the quasi-synchronized demodulated signals P and Q converted into multi-bit digital signals are compensated by the phase rotation component of 2πΔf in the transversal equalizer 7'and converted into demodulated signals phase-synchronized with the input signal.

[Problems to be Solved by the Invention]

In this way, in the conventional digital demodulation device, a demodulated signal that is phase-locked with the input signal can be obtained.
In order to compensate the phase rotation component of f, the weighting circuit of all taps of the transversal equalizer 7'is used, and the maximum compensable value of 2πΔf is the value of each tap of the transversal equalizer 7 '. It will depend on the response speed of the control loop. Normally, the transversal equalizer 7'has many taps, and the respective control loops influence each other. Therefore, in order to stabilize the operation, it is necessary to make the response speed too fast. Can not. Therefore, in the conventional device, the difference frequency Δ
Since f cannot be increased so much, there is a problem that the allowable frequency fluctuations of the input signal and the fixed reference carrier oscillator cannot be increased.

An object of the present invention is to provide a digital demodulation device capable of increasing such allowable frequency fluctuation.

[Means for solving the problem]

The digital demodulation device of the present invention includes a quasi-synchronous demodulation means for quadrature-phase detecting an input quadrature amplitude modulated wave using a fixed reference carrier to obtain a quasi-synchronous demodulation signal, and inputting the quasi-synchronous demodulation signal to an imaginary axis A transversal equalizer excluding the main tap and an infinite phase means for outputting a demodulation signal phase-synchronized with the quadrature amplitude modulated wave, and the output of the quasi-synchronization demodulation means is a transversal equalizer. Connect to the other end of the infinite phase shifting means to be input to the other, and set the response speed of the control loop in the infinite phase shifting means to be faster than the response speed of the control loop in the transversal equalizer. ing.

The infinite phase shift means includes a logic circuit that calculates the control signal, a multiplier that multiplies the output of the logic circuit and demodulated signals that are orthogonal to each other, and an adder or subtractor that adds or subtracts the output of each multiplier. It consists of.

[Action]

In this configuration, the infinite polyphase device operates so as to optimize the demodulated signal with respect to the detection phase and compensates for the phase rotation component due to the difference frequency Δf, so that the difference frequency Δf can be increased without destabilizing the operation. , It is possible to increase the maximum fluctuation allowable value.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a digital demodulation device of the present invention. In the figure, reference numerals 1 to 6 are third
This is the same as the conventional configuration shown in the figure. Further, 7 is a transversal equalizer, 8 and 9 are infinite phase shifters (EPS), and 10 and 11 are multipliers.

Here, the operation of the quadrature detector 1, the fixed reference carrier oscillator 2, the low-pass filters 3, 4 and the multi-level discriminators 5, 6 is the same as the conventional operation, but now the input signal is 2 ⁿ Assuming a × 2 ⁿ value (n is a natural number) quadrature amplitude modulation wave, P and Q are 2 ⁿ value analog baseband signals. Further, the multi-value classifiers 5 and 6 have a configuration of (n + x) bits (x is a natural number of 3 or more). Further, in the transversal equalizer 7, the main tap of the imaginary axis part is deleted, so that the transversal equalizer 7 operates only for compensation of intersymbol interference, and the phase shift rotation component due to the difference frequency Δf. I don't know anything about it and give no response.

Here, compensation of the phase rotation component by the difference frequency Δf is performed by the infinite phase shifters 8 and 9. That is, the outputs of the multivalued discriminators 5 and 6 enter independent infinite phase shifters 8 and 9, respectively, so that a demodulated signal phase-locked to the input signal is obtained as the output of the infinite phase shifters 8 and 9. , The phases of the input signals of the infinite phase shifters 8 and 9 are controlled. The control signal a of the infinite phase shifter 8 includes a plurality of (n + 1) th or lower bits of the output of the infinite phase shifter 8,
That is, an error signal indicating how much the demodulated signal deviates from the normal position and a plurality of bits from the MSB to the n-th of the output of the infinite phase shifter 9 which is a demodulated signal orthogonal to this, that is, the main data signal. Is obtained by digital multiplication by the multiplier 10. Therefore, the infinite phase shifter 8 operates so that the error signal at its output is minimized by the control signal a. In other words, the output demodulated signal of the infinite phase shifter 8 operates so as to be optimum with respect to the detection phase.

The infinite phase shifter 9 also operates as follows. The control signal b of the infinite phase shifter 9 includes a plurality of (n + 1) th or less bits of the output, that is, an error operation indicating how much the demodulated signal deviates from the normal position, and a demodulated signal orthogonal to the error operation. It is obtained by digitally multiplying a plurality of bits from the MSB to the nth bit, that is, the main data signal, of the output of a certain infinite phase shifter 8 by the multiplier 11. Therefore, the demodulated signal output from the infinite phase shifter 9 operates so as to be optimum with respect to the detection phase.

In this way, the compensation of the phase rotation component by the difference frequency Δf is performed by the infinite phase shifters 8 and 9, but the control loops of the infinite phase shifters 8 and 9 are independent and have no correlation with other loops. , Its response speed can be considerably increased without destabilizing the operation. Therefore, the maximum variation allowable value of the difference frequency Δf can be increased.

In addition, the infinite phase shifters 8 and 9 provided independently corresponding to the quasi-synchronized demodulation signals P and Q respectively have independent control signals.
Controlled by a and b, the demodulated signals of the outputs of the infinite phase shifters 8 and 9 operate independently of each other with respect to the detection phase. In other words, this means that even if a quadrature shift occurs in the quadrature phase detector 1, it is completely compensated by the infinite phase shifters 8 and 9 provided independently.

Although a plurality of (n + 1) th and lower bits are used as the error signal, only the (n + 1) th bit may be used, and the MSB, that is, quadrant bits may be used instead of the nth plurality of bits from the MSB as the main data signal.

FIG. 2 is a specific example of the infinite phase shifters 8 and 9, where 12 is an adder, 13 is a subtractor, 14 and 15 are logic circuits, and 16 to 19 are multipliers.

P ′ and Q ′ are demodulated signals that are orthogonal to each other, and are 1: tan α
The phases of P'and Q'can be changed by α by adding or subtracting with the amplitude ratio of.

Now, looking at the infinite phase shifter 8 in FIG. 2 as P ′ = sin θ, Q ′ = cos θ (where θ represents the phase difference between the input and the output of the fixed reference carrier wave oscillator 2). , The output of the multiplier 16 is P ′ = cos α · sin θ, the multiplier 17
Output is Q ′ = sin α · cos θ, and as a result, the output P ″ is cos α · sin θ + sin α · cos θ = cos (θ +
α), and if the coefficients cos α, sin α are given to the multipliers 16 and 17, the output phase of the multiplier 12 is changed by α.

 The infinite phase shifter 9 operates similarly.

The logic circuits 14 and 15 are used to match the interfaces between the control signals a and b and the multipliers 16 to 19.

Here, the present invention can be applied not only to a demodulator using a digital infinite phase shifter but also to an analog infinite phase shifter. In that case, the silent phase shifter is installed in front of the multilevel discriminator. The same effect can be obtained even if the infinite phase shifter is provided before the transversal equalizer.

〔The invention's effect〕

As described above, according to the present invention, the infinite phase shifter whose response speed is set higher than the response speed of the control loop of the transversal equalizer operates to operate the difference frequency Δf.
To realize a digital demodulator capable of increasing the difference frequency Δf without making the operation unstable and increasing the allowable frequency fluctuations of the input signal and the fixed reference carrier oscillator because the phase rotation component is compensated by There is an effect that can be. Further, with this configuration, it is easy to make an LSI, and the circuit scale of the device can be reduced. Furthermore, the demodulated signals obtained by a plurality of infinite phase shifters can be independently set to the optimum state with respect to the detection phase, and the quadrature shift of the quadrature phase detector can be compensated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital demodulating device of the present invention, and FIG. 2 is a block diagram showing a specific example of an infinite phase shifter.
FIG. 3 is a block diagram of a conventional digital demodulator. 1 ... Quadrature phase detector, 2 ... Fixed reference carrier oscillator,
3,4 ...... Low-pass filter, 5,6 ...... Multilevel discriminator, 7,7 '…… Transversal equalizer, 8,9 …… Infinite phase shifter, 10,11 ……
Multiplier, 12 ... Adder, 13 ... Subtractor, 14, 15 ... Logic circuit, 16-19 ... Multiplier.

Claims (2)

(57) [Claims] 1. A quasi-synchronous demodulation means for quadrature-phase detecting an input quadrature-amplitude modulated wave using a fixed reference carrier to obtain a quasi-synchronous demodulated signal, and the quasi-synchronous demodulated signal being input to an imaginary axis main tap. , And an infinite phase shift means for outputting a demodulation signal phase-locked with the quadrature amplitude modulated wave, and the output of the quasi-synchronous demodulation means is infinitely shifted with the transversal equalizer. Connected so as to be input to the other through one of the phase means, and set the response speed of the control loop in the infinite phase shifting means to be faster than the response speed of the control loop in the transversal equalizer. A digital demodulator characterized in that 2. The infinite phase shift means comprises a logic circuit for calculating a control signal, a multiplier for multiplying an output of the logic circuit by a demodulated signal orthogonal to each other, an adder for adding or subtracting the output of each multiplier, or The digital demodulation device according to claim 1, wherein the control loop includes a subtractor.