JPH02249330A - Pseudo lock detection circuit for costas loop type demodulator - Google Patents

Abstract

PURPOSE:To output a pseudo locking detection signal by applying synchronous detection to a signal with a frequency component appearing at the output of a multiplier multiplying the multiplication output of Ich and the multiplication output of Qch of a COSTAS loop type demodulator demodulating a phase- modulated carrier at the pseudo lock of the COSTAS loop type demodulator. CONSTITUTION:When a COSTAS loop type demodulator 20 is locked normally, since the level of an output signal S8 of a multiplier 25 of the COSTAS loop type demodulator 20 is nearly zero, the value of the detected signal S10 is nearly zero. On the other hand, when the carrier frequency of an input modulation signal S5 is shifted by the integer multiple of the bit rate of the data transmission in the increasing direction more than the oscillated frequency of a VCO 27 of the COSTAS loop type demodulator 20 and the pseudo lock state takes place, the level of the detected signal S10 reaches a prescribed level TH or above. Thus, the pseudo locking state of the COSTAS loop type demodulator is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a pseudo lock detection circuit for a Costas loop demodulator, for example, a 191
The present invention relates to a circuit for detecting a false lock state of a Costas loop type demodulator, which is a receiver demodulator in a star communication system.

[Summary of the Invention] The present invention provides a phase modulated carrier wave ist1! Means for synchronously detecting a signal of a frequency component that appears when a Costas loop demodulator is pseudo-locked to the output of a multiplier that multiplies the Ich multiplication output of the Costas loop demodulator for J and the Qch multiplication output; By detecting that the output of the means is at a level outside the predetermined range and outputting a pseudo lock detection signal, the carrier frequency of the input signal of the Costas loop demodulator is changed to the oscillation of the voltage controlled oscillator of the Costas loop demodulator. A deviation of an integral multiple of 1/2 of the frequency corresponding to the bit rate of data transmission (hereinafter referred to as bit rate frequency) in the high frequency direction or low frequency direction with respect to the frequency, the Costas loop demodulator enters a pseudo-lock state. When this occurs, it is possible to detect a pseudo-locked state of the mode specified by the frequency of the carrier wave used by the synchronous detection means and the direction of the frequency shift.

(Prior art) Modulation methods used in satellite communications include frequency modulation (FM) as an analog modulation method, and diphase phase shift 11 (BPsi()) and four-phase phase modulation as digital modulation methods. (QPSK), MSK modulation, etc.The FM modulation method has been used in communication systems mainly based on analog voice transmission, but as the information to be transmitted is increasingly digital signals such as images and data. In recent years, satellite communication systems have not been used much, and digital phase modulation methods such as binary phase modulation and quadrature phase modulation have become mainstream.Also, spread spectrum communication is used in multiplex communication systems using code division. ing.

A so-called Costas loop demodulator is known as a means for obtaining a demodulated signal from a digital phase modulated wave, and is disclosed in Japanese Patent Application Laid-Open No. 58-1989.
No. 215256 discloses a technology of a Costas loop demodulator that switches between two-phase phase modulation and four-phase phase modulation for reception.

[Problems to be Solved by the Invention] By the way, the Costas loop demodulator is a type of composite phase-locked loop (hereinafter referred to as P1., L) circuit. That is, the carrier frequency of the input signal of the Costas loop demodulator and the voltage controlled oscillator (hereinafter v) of the Costas loop demodulator
It's called CO. ) when the oscillation frequencies and their phases match, the locked IIM (hereinafter referred to as a normal locked state).

), and a proper demodulated signal can be obtained. However, if the carrier frequency of the above input signal deviates from the oscillation frequency of the above Co in the high frequency direction or the low frequency direction by an integral multiple of 172 of the frequency of the data transmission bit rate, it will appear as if it were in a lock state (hereinafter referred to as pseudo lock state). condition) may occur.

In other words, the Koscslube type detector may enter a pseudo-lock state in multiple modes. When a Costas loop demodulator enters a pseudo-lock state, data cannot be read correctly, and once a Costas loop demodulator enters a pseudo-lock state, it will not lock normally even if an input signal of a new carrier frequency is input manually. It takes time to return to normal condition.

The pseudo-lock detection circuit for a Costas loop demodulator according to the present invention was made in view of the above-mentioned circumstances, and the carrier frequency of the input signal of the Costas loop demodulator is If the Costas loop demodulator enters a pseudo-lock state due to a deviation in the high frequency direction or low frequency direction with respect to the oscillation frequency by an integer multiple of 172 of the frequency of the data transmission bit rate, it is determined by the carrier wave of the synchronous detection means. An object of the present invention is to provide a circuit that detects a pseudo-lock state in a mode and the direction of the frequency deviation.

[Means to solve the problem]

In order to solve the above-mentioned problems, the pseudo-ronc detection circuit for a Costas loop demodulator according to the present invention has the following advantages:
means for synchronously detecting a signal of a frequency component that appears when the Costas loop demodulator is pseudo-locked by the output of the multiplier that multiplies the multiplier horn of the channel by the multiplier output of the Qch; It is characterized by comprising a level discriminating means which detects that the lock is at a level other than that and outputs a pseudo lock detection circuit.

[Effect]

According to the pseudo lock detection circuit of the Costas loop demodulator according to the present invention, the carrier frequency of the human input signal of the Costas loop demodulator is in a higher frequency direction or lower than the oscillation frequency of CO of the Costas loop demodulator. If there is a shift in the frequency direction by an integral multiple of 172 of the frequency of the data transmission bit rate, and the Costas loop demodulator enters a pseudo-lock state,
It is possible to detect the pseudo-lock state of the mode specified by the frequency of the carrier wave used by the synchronous detection means and the direction of the frequency deviation.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment in which a pseudo long detection circuit of a Costas loop demodulator according to the present invention is applied to a receiver for spread spectrum communication will be described with reference to the drawings.

FIG. 1 shows a demodulator in a receiver for spread spectrum communication. First, this demodulation section will be explained.

The input terminal I is supplied with a spread spectrum signal Sl as an input signal. This input signal is supplied to a digital lock loop (hereinafter referred to as a DLL circuit) 10 and a multiplier 2.

The DLL circuit 10 has a phase comparator 11. It is composed of a loop filter 12, a VCO 13, and a spreading code generator 14, and the VCO 13 generates a clock S2 corresponding to the carrier frequency of the input signal Sl. The spreading code generator 14 generates a spreading code S3 and a leading pulse S4 indicating the position of the leading pulse of each block of the spreading code S3. The clock S2 and the leading pulse S4 are supplied to a local signal generator 2130 that generates a carrier wave used for synchronous detection, which will be described later, and a spreading code S3 is supplied to the multiplier 2.

In the multiplier 2, the spectrum-spread signal S1, which is the input signal, is multiplied by the spreading code S3 to obtain a phase modulated signal S5. This phase modulated signal S5 is supplied to the Costas loop demodulator 20.

The Costas loop demodulator 20 includes an Ich multiplier 2
1. Icl+ low pass filter (hereinafter referred to as LPF).

) 22, Qch multiplier 23, Qch LPF 24, multiplier 25, loop filter 26, VC027, and π/2 phase shifter 28. In this Costas loop demodulator 20, the phase modulation signal S5 is transmitted to a multiplier 21,
The signal is supplied to a multiplier 23. In this multiplier 21, V
The output signal of CO27 and phase modulation signal S5 are multiplied. On the other hand, in the multiplier 23, the output signal of the VCO 27 is
The signal whose phase is delayed by π/2 by the /2 phase shifter 28 is multiplied by the phase modulation signal S5. The output signals of multipliers 21 and 23 are respectively supplied to LPFs 22 and 24, and frequency components above a predetermined frequency are removed.

Output signal S6 of LPF22 ([ch multiplication output) and L
The output signals 57 (Qch multiplication outputs) of the PF 24 are respectively supplied to the multipliers 25 and multiplied therein. The output signal S8 of this multiplier 25 is transmitted to the loop filter 2.
6 and the pseudo lock detection circuit 40. The output signal of the loop filter 26 is supplied to the VCO 27, and the VCO
The oscillation frequency and phase of 27 are controlled to match the carrier frequency of the phase modulation signal S5. In addition, the above LPF2
The output signal S6 of No. 2 is a demodulated signal of the Costas loop demodulator 20, and is supplied to the output terminal 2.

On the other hand, the local signal generator 30 includes a sine wave generator 31,
n amplifiers 32. to 32AS, n resistors 33. 335 and a buffer up 34. The sine wave generator 31 generates n integers (of the frequency of the data transmission bit rate) from the clock S2 and the first pulse S4.
1 to n) times the sine wave signals fl to rn.

These sine wave signals rl to fn are transmitted to the amplifier 32.
to 327 and resistor 33. to 33I, and are added to the pseudo lock circuit 40 via the buffer up 34. That is, the output signal S9 of the buffer amplifier 34 is a signal containing frequency components of 1 to n times the frequency of the data transmission bit rate.

The pseudo-lock detection circuit 40 includes a synchronous detection means comprising a multiplier 41 and an LPF 42 for synchronously detecting the output signal S8 of the multiplier 25 of the Costas loop demodulator 20;
It consists of comparators 43 and 44 that determine the level of the synchronously detected signal and send out a suspicious rotor detection signal.

Here, the multiplier 25 of the Costas loop demodulator 20
The output signal S8 will be explained using FIGS. 2 to 4ryi.

FIG. 2 shows the carrier frequency of the phase modulation signal S5 and the VCO
27 is a waveform diagram showing the operation of the Costas loop demodulator 20 in a normal lock state where the oscillation frequencies and their phases match, and the I of the Costas loop demodulator 20 is
The waveform of the output signal S6 of the LPF 22, which is the multiplication output of the channel, is shown in a, and the Qc
The waveform of the output signal S7 of the LPF 24, which is the multiplication output of h, is shown in b, and the waveform of the output signal S8 of the multiplier 25 of the Costas loop demodulator 20 is shown in c. In this normal lock state, the output signal S8 of the multiplier 25 has a value close to zero, as shown at C in FIG.

FIG. 3 shows the carrier frequency and VC of the phase modulation signal S5.
FIG. 10 is a waveform diagram showing the operation of the Costas loop demodulator 20 in which the oscillation frequency of the O27 is shifted by 1/2 of the frequency of the data transmission pit-ray 1, resulting in a pseudo-lock state, and the Ich of the Costas loop demodulator 20 is LP, which is the multiplication power of
The waveform of the output signal S6 of the F22 is shown in a, and the waveform of the output signal S7 of the LPF 24, which is the Qch multiplication output of the Costas loop demodulator 20, is shown in b. The waveform of S8 is shown in C.

In this pseudo-lock state, the output signal S8 of the multiplier 25 becomes a signal having a frequency component (hereinafter referred to as f component) of the pit rate of data transmission, as shown in C in FIG.

FIG. 4 shows the carrier frequency of the phase modulation signal S5 and the VCO
27 is a waveform diagram illustrating the operation of the Costas loop demodulator 20 in which the oscillation frequency of the Costas loop demodulator 20 is shifted by the frequency of the data transmission pit-ray] and is in a pseudo-lock state. The waveform of the output signal S6 of the LPF 22 which is the output is shown in a, and the waveform of the output signal S7 of the LPF 24 which is the Qch multiplication output of the Costas loop demodulator 20 is shown in b.
The waveform of the output signal S8 of the multiplier 25 is not shown in C. In this pseudo-locked state, the output signal S8 of the multiplier 25 becomes a 2f component signal as shown in C of FIG.

In addition, in the above, the carrier frequency of the phase modulation signal S5 and the VCO
Only when the oscillation frequency of the multiplier 27 is shifted by 172 or a frequency of the data transmission bit rate, the output signal of the multiplier 25 -! , ;, I explained S 8, but
When the general transmission frequency of the phase modulation signal S5 and the oscillation frequency of the VCO 27 deviate from each other by an integral multiple of 172 (3, 4, . . . n) of the frequency of the data transmission bit rate, the multiplier 2
The output signal of No. 5 is a signal with a frequency component corresponding to the above-mentioned integer multiple. That is, the signals are 3r, 4r, . . . nf acid component signals.

Next, the operation of the pseudo lock detection circuit 40 of the Costas loop demodulator according to the present invention when the output signal S8 of the multiplier 25 as described above is input will be described.

In the multiplier 41, the output signal S of the multiplier 25
8 is multiplied by the output signal S9 of the local signal generator 30, this multiplied signal is supplied to the LPF 42, and the frequency of the data transmission bit rate included in the output signal S9 is 1 to n times. The frequency components (r, 2f, 3f,
--=nf) is removed. That is, the output signal S8 of the multiplier 25 is synchronously detected using the output signal S9 of the local signal generator 30. This detected signal SIO is supplied to the positive input terminal of the comparator 43 and the negative input terminal of the comparator 44.

By the way, when the Costas loop demodulator 20 is in a normal lock state, the multiplier 25 of the Costas loop demodulator 20
Since the level of the output signal S8 is approximately zero as described above, the value of the detected signal 510 is approximately zero. On the other hand, the carrier frequency of the phase modulation signal S5 shifts in the frequency direction higher than the oscillation frequency of the VCO 27 of the Costas loop demodulator 20 by an integral multiple of 172 of the data transmission bit rate, resulting in a pseudo-lock state (hereinafter referred to as the above pseudo-lock state). ), the value of the detected signal 510 becomes equal to or higher than the predetermined level TH. Further, the carrier frequency of the phase modulation signal S5 is oscillation 1 of the VCO 27 of the Costas loop demodulator 20.
If the detected signal deviates by an integer multiple of 1/2 of the data transmission bit rate in the frequency direction that is higher than the M wave number, and a pseudo lock state (hereinafter referred to as the lower pseudo lock state) occurs, the detected signal The value of 510 is below the predetermined level -TH. That is, the bias voltage of the negative input terminal of the comparator 43 is set to the predetermined level TH, and the bias voltage of the positive input terminal of the comparator 44 is set to the predetermined level TH.
47, when the Costas loop demodulator 20 is in a normal lock state, the output signal of the comparator 43 and the output signal of the comparator 44 are at a low level. −
When the sumo wrestler is in a pseudo-locked state, the output signal of the comparator 43 is at a high level, and the output signal of the comparator 44 is at a low level. Further, in the lower pseudo-lock state, the output signal of the comparator 43 is at a low level, and the output signal of the comparator 44 is at a high level. Therefore, it is possible to determine whether the Costas loop demodulator 20 is in a normal lock state, an upper pseudo-lock state, or a lower pseudo-lock state. The pseudo-lock detection signal detected as described above (either the output signal of the comparator 43 or the output signal of the comparison 2=44 is assumed to be at a high level) is output to the output terminal 3 or the output terminal 4.

As described above, when the Costas loop demodulator enters a pseudo-lock state, the output of the multiplier that multiplies the Ici+ multiplication output and the Qch multiplication output of the Costas loop demodulator contains a signal of a specific frequency component. appear. By detecting this specific frequency component signal using synchronous detection, it is possible to detect a lock state of the Costas loop demodulator. In other words, the above frequency components that appear during pseudo-locking are caused by the pseudo-locking state of each mode, for example, when the carrier frequency of the human signal of the Costas loop demodulator and the oscillation frequency of the VCO of the Costas loop demodulator are the same as the data transmission rate. Pseudo-locked mode with frequency shifted by 1) 2 minutes,
and the pseudo-lock state in which the carrier frequency of the input signal of the Costas loop demodulator and the oscillation frequency of the VCO of the Costas loop demodulator are shifted by the frequency of the data transmission bit rate. By using a plurality of carrier waves (n in the above specific example) as described above,
A pseudo-lock state in either mode can be detected. Furthermore, in this embodiment, since the plurality of V9 transmission waves described above are added and used, the pseudo mouth/tuck state of each mode]' can be detected at the same time. In addition, as mentioned above, it is possible to detect whether the Costas loop demodulator has falsely locked at a frequency higher than the normal lock state or falsely locked at a lower frequency. When a carrier frequency input signal is input, it is also possible to forcibly control the Costas loop demodulator to a normal state based on the detection result. In addition, the above F
, 11 The LPF for mountain waves may be a first-order LPF, which is economical. Further, the present invention is not limited to the above-mentioned embodiment, and the local signal generator 30 described above may output carrier waves used for synchronous detection one by one in sequence. In other words, synchronous detection may be performed by scanning the carrier wave.

In this case, by scanning, it is possible to specify in which mode the Costas loop demodulator is in a pseudo-lock state.

Further, by using a plurality of carrier waves for synchronous detection at once, detection of pseudo-lock states in a plurality of modes can be performed at once. Furthermore, by scanning the carrier wave for synchronous detection, it is possible to specify which mode is in the locked state. Furthermore, although it generally takes time for a Costas loop demodulator to recover from a pseudo-lock state, the recovery time can be shortened if the pseudo-lock state can be accurately detected.

〔Effect of the invention〕

As is clear from the above description, according to the pseudo-lock detection circuit of the Costas loop demodulator according to the present invention, it is possible to detect a pseudo-lock state in a mode specified by the frequency of the carrier wave for synchronous detection. In addition, it is possible to accurately detect whether a pseudo-lock state occurs at a high frequency or a pseudo-lock state at a low frequency with respect to a normal lock state.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the demodulation section of a receiver for spread spectrum communication to which the pseudo-lock detection circuit of the Costas loop demodulator according to the present invention is applied, and FIG. 2 shows the Costas loop demodulator in a normal lock state. Figure 3 is a waveform diagram showing the operation of the Costas loop demodulator, where the carrier frequency of the input signal and the oscillation frequency of the VCO of the Costas loop demodulator are shifted by ]/2 of the frequency of the data transmission bit rate. A waveform diagram showing the operation when the Costas loop demodulator enters a pseudo-lock state, FIG. 4 shows the carrier frequency of the input signal of the Costas loop demodulator and the vC of the Costas loop demodulator.
FIG. 6 is a waveform diagram showing the operation when the oscillation frequency of O is shifted by the frequency of the data transmission bit rate and the Costas loop demodulator enters a pseudo-lock state. Waveform diagram of C output right signal S8 self-registration check Figure 2 20 ・ ・ 25 ・ ・ 40 ・ ・ ・ 41 ・ ・ ・ 42 ・ ・ ・ 43, 44 Costas loop demodulator Costas Multiplier pseudo-lock detection circuit of loop type demodulator Multiplier for synchronous detection LPF for synchronous detection ...Level comparator special fraud applicant

Claims (1)

[Claims] A frequency that appears at the time of pseudo lock of the Costas loop demodulator in the output of a multiplier that multiplies the Ich multiplication output and the Qch multiplication output of the Costas loop demodulator that demodulates a phase-modulated carrier wave. A pseudo-lock of a Costas loop demodulator, which comprises means for synchronously detecting component signals, and level determining means for detecting that the output of the synchronous detection means is at a level outside a predetermined range and outputting a pseudo-lock detection signal. detection circuit.