JP3366286B2 - Digital receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to quaternary phase modulation (Qu
The present invention relates to a digital receiver that demodulates a digital modulation signal modulated by adrature Phase Shift Keying (hereinafter referred to as 4-phase PSK).

[0002]

2. Description of the Related Art An analog carrier wave is modulated and transmitted by a digital signal (symbol: a signal such as voice or image encoded into a pulse train, or a data signal) having a binary signal level. As a digital modulation method, for example, (1) ASK (Amplitude Shift Keying: amplitude modulation) (2) FSK (Frequency Shift Keying: frequency modulation) (3) PSK (Phase Shift Keying: phase modulation) is known. The PSK method has the smallest carrier-to-noise power ratio (C / N) for the same code error rate,
It is resistant to noise and is widely used in existing microwave communication and digital radio systems. In the PSK system, four-phase PSK is generally used, there are a path length type and a ring type as a modulator, and a synchronous detection is used as a demodulator. Synchronous detection is a method in which a received signal and a reference carrier created on the receiving side are subjected to product modulation to extract a low frequency component.
Generally, the low frequency component extracted by the above method is compared with a predetermined symbol level, and the closest symbol level is determined as the reproduction symbol value. This digital demodulator is provided with a clock phase synchronizing section for demodulating an accurate symbol so as to reproduce a clock signal phase-synchronized with the sampling timing on the digital modulator side.

[0003]

The conventional fine adjustment of the carrier frequency of the received signal and the frequency generated by the receiver is performed by A / D.
An analog filter having a steep frequency characteristic is used as a filter, whether it is performed by calculation after conversion or the like. For example, in the demodulation device of Japanese Patent Laid-Open No. 08-335959, fine adjustment is performed by calculation using a complex multiplier after digitalization and a digital voltage controlled oscillator (DVCO). Further, in Japanese Patent Laid-Open No. 09-199997, an analog filter is used. When using an analog filter,
When the steep frequency characteristic is provided, the group delay characteristic deteriorates.

Further, as described in Japanese Patent Laid-Open No. 9-130443, for example, when an accurate symbol determination value cannot be obtained, the time required for retracting the carrier phase synchronization control and the clock phase synchronization control becomes long. There is a problem that the synchronization control becomes unstable due to the mutual interference between the carrier phase synchronization control and the clock phase synchronization control.To solve this problem, it is necessary to adjust the clock phase error detected from the output of the carrier removing means. Technology for generating clocks with different frequencies has been published.

According to the present invention, an input intermediate frequency (hereinafter, I
To provide a demodulator for compensating a frequency error between a carrier frequency of a signal and a frequency output by a voltage controlled oscillator (hereinafter referred to as VCO) by finely adjusting the frequency of the VCO and extracting an accurate symbol. With the goal.

[0006]

The present invention provides an A / D converter for sampling and digitizing an IF signal input to a receiver in synchronization with a clock signal generated by a VCO, and the A / D converter. An orthogonal separation unit that orthogonally separates the reception data digitized by the converter in synchronization with the clock signal generated by the VCO, and a frequency component generated by the sampling is synchronized with the clock signal generated by the VCO. A first low-pass filter that removes the received data, and a symbol rate synchronization unit that changes the frequency of the reception data that is synchronized with the sampling frequency of the VCO to frequency data that depends on the symbol rate.
A second low-pass filter that is connected to the latter stage of the symbol rate synchronization unit, operates in synchronization with a symbol rate-dependent clock, and has a steep frequency characteristic to limit the band of received data, and synchronizes with the symbol rate-dependent clock. The phase difference between the carrier frequency of the input IF signal and the output frequency of the VCO is calculated from the phase detector detecting the phase data and deriving the frequency error and the phase data detected by the phase detector. A frequency error detector,
In a four-phase PSK modulation type digital receiver including the VCO, the VCO receives an input I from the frequency error detector.
It is characterized by receiving information of a frequency error between the carrier frequency of the F signal and the output frequency of the VCO and finely adjusting the frequency error.

The present invention also provides a four-phase PS according to claim 1.
In the K modulation type digital receiver, the clock signal generated by the VCO and the symbol rate dependent clock signal are independent of each other.

According to the present invention, for example, the four-phase P shown in FIG.
In the SK receiver, signal processing after A / D conversion is performed with a simple configuration, and the frequency error between the carrier frequency of the input IF signal and the output frequency of the VCO 3 is calculated by the VCO 3
The frequency is finely adjusted to compensate. The present invention simplifies the SIN / COS table of the orthogonal separating unit 2 by making the operating frequencies of the A / D converter 1 for digitizing the IF signal and the orthogonal separating unit 2 for orthogonally separating the digitized signal the same. To do. Also, the symbol rate synchronization unit 5 and the low-pass filter (hereinafter referred to as LPF)
6. The phase detector 7 operates in synchronization with the symbol rate dependent clock. The operation of the LPF 6 connected to the latter stage of the symbol rate synchronization unit 5 and having a steep characteristic is synchronized with the symbol rate and separated from the frequency of the VCO 3, and therefore does not depend on the frequency of the VCO 3. Thus, the operation of the LPF 6 is not affected even if the frequency of the VCO 3 is adjusted.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. In recent demodulators for digitally modulated signals, the digitally modulated signal is once converted into an IF frequency by a tuning circuit, and digitally demodulated from this IF frequency.

FIG. 1 shows a block diagram of a receiver after the QPSK modulated signal is frequency-converted into an IF signal. The A / D converter 1 receives the I input to the receiver.
The F signal is sampled and digitized in synchronization with the signal of the oscillation frequency generated by the VCO 3. The received data digitized by the A / D converter 1 is sent to the orthogonal separator 2 and orthogonally separated. The orthogonal separation unit 2 is also a VCO 3
It operates in synchronization with the oscillation frequency signal. The separated reception signal passes through the LPF 4 and enters the symbol rate synchronization unit 5.

In the symbol rate synchronization unit 5, the VCO 3
The frequency is changed from the sampling frequency to the frequency data depending on the symbol rate. That is, the equipment at the stage after the symbol rate synchronization unit 5 operates in synchronization with the symbol rate dependent clock. The received data changed to the frequency depending on the symbol rate is L
The band is limited by the PF 6 and sent to the phase detector 7.

The LPF 6 has a π / 4 shift four-phase differential QDPSK (Quadrature Different Phase) which is generally used in TDMA mobile communication systems in Japan and North America.
Narrow band modulation using Shift Keying) is performed.
Then, a frequency error is derived from the phase data detected by the phase detector 7. The error detected by the frequency error detector 8 is sent to the VCO 3, and the frequency of the VCO 3 is finely adjusted by the sent frequency error.

Next, the operation of the receiver shown in FIG. 1 will be described. The IF signal of the received 4-phase PSK signal is A /
The digital signal is converted by the D converter 1. The sampling signal when converting to this digital signal is
Generated by VCO3. There is an error between the frequency of the signal generated by the VCO 3 and the carrier frequency of the received modulated signal, which requires adjustment.

In the present invention, the VCO 3 adjusts the error from the carrier frequency of the received modulated signal. The orthogonal separation unit 2 performs orthogonal separation on the signal digitized by the A / D converter 1 using SIN / COS data. At this time, in the present invention, the sampling clock of the A / D converter 1 and the operation clock used in the quadrature separation unit 2 are the same, and even if the frequency is finely adjusted by the VCO 3, the configuration of the quadrature separation unit 2 or the SIN / COS is used. The data can be used without modification.

Next, after removing the frequency components generated by the sampling by the LPF 4, the signal digitized by the symbol rate synchronizing section 5 is synchronized with the clock depending on the symbol rate to change the clock. Subsequent digital signal processing is operated with a clock synchronized with a frequency dependent on the symbol clock.
The signal whose clock has been changed by the symbol rate synchronization 5 enters the LPF 6 having a steep frequency characteristic and limits the band. In the present invention, by changing the clock as described above, the frequency adjustment of the VCO 3 does not affect the subsequent digital signal processing. Therefore, LP
F6 may constitute a filter having a single characteristic without considering the frequency fine adjustment of VCO3.

Further, the signal band-limited by the LPF 6 is sent to the phase detector 7 and converted into phase data. The frequency error detector 8 derives a frequency error between the carrier frequency of the received modulated signal and the frequency generated by the VCO 3 from the transition of the phase data generated by the phase detector 7. The frequency error derived by the frequency error detector 8 is sent to the VCO 3, and the VCO 3 finely adjusts the frequency error.

[0017]

According to the present invention, the clock used in the circuit is A
Since the sampling clock of the / D converter and the clock for orthogonal separation are the same and the clock that depends on the symbol rate is used after that, even if the frequency error is finely adjusted by the VCO, it is not performed. Compared with the case, the effect that the circuit scale after digitization does not change is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital demodulation device of the present invention.

[Explanation of symbols]

1 ... A / D converter 2 ... Orthogonal separation section 3 ... Voltage controlled oscillator (VCO) 4 ... First low-pass filter (LPF) 5 ... Symbol rate synchronization unit 6 ... Second low-pass filter (LPF) 7 ... Phase detector 8 ... Frequency error detector

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-117451 (JP, A) JP-A-9-130443 (JP, A) JP-A-8-335959 (JP, A) JP-A-9- 199997 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/22 H04L 7/00

Claims (2)

(57) [Claims] 1. An intermediate frequency signal (IF) input to a receiver.
Signal) is sampled in synchronization with a clock signal generated by a voltage controlled oscillator (VCO) and digitized, and received data digitized by the A / D converter is generated by the VCO. An orthogonal separation unit that performs orthogonal separation in synchronism with a clock signal that is generated, and a frequency component generated by the sampling
A first low-pass filter that removes in synchronism with a clock signal generated by a CO, and symbol rate synchronization for changing the frequency of received data synchronized with the sampling frequency of the VCO to frequency data that depends on the symbol rate. A second low-pass filter that is connected to a subsequent stage of the symbol rate synchronization unit, operates in synchronization with a symbol rate-dependent clock, and band-limits received data with a predetermined frequency characteristic; A phase detector that operates in synchronization with a clock to detect phase data and derive a frequency error, and a frequency error between the carrier frequency of the input IF signal and the output frequency of the VCO from the phase data detected by the phase detector. A four-phase PSK modulation type digital receiver comprising: In the digital reception, the VCO receives information on a frequency error between the carrier frequency of the input IF signal and the output frequency of the VCO from the frequency error detection unit, and finely adjusts the frequency error. Machine. 2. The digital receiver according to claim 1, wherein the clock generated by the VCO and the symbol rate dependent clock are independent of each other.