JP3074752B2 - Minimum displacement modulation wave demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for clock recovery means of a digital satellite communication system. In particular, the present invention relates to a clock recovery means in a minimum displacement modulation wave (hereinafter, referred to as MSK) modulation / demodulation method.

[0002]

2. Description of the Related Art FIG. 4 shows a clock recovery means of a conventional MSK demodulation circuit for demodulating an MSK modulated wave. However, MS
The center frequency of the IF signal input to the K demodulation circuit is F0, and the bit rate of the transmitted data is FS. The input IF signal (MSK modulated wave) is VCO
Regenerated carrier wave output from circuit 23 (frequency is F)
, And outputs two series of baseband signals. These two series of signals are referred to as I and Q (both have a baud rate of FS / 2). The outputted I and Q are used as reproduction data and are input to the phase detection circuit 22. The input IF signal is also input to the clock recovery circuit 21,
The clock recovery circuit 21 recovers the FS / 2 clock and supplies it to the phase detection circuit 22. The phase detection circuit 22 uses the ACO of the VCO circuit 23 so that F = F0 by the Costas method.
Supply PC voltage. FIG. 5 shows an example of the clock recovery circuit 21 in detail. As shown in FIG. 5 , one of the IF signals is supplied to a phase comparator 33 (this is referred to as IF1), and the other is delayed by 90 ° in a 90 ° shift circuit 31, and TS = 1 / If FS, T
The signal is supplied to the phase comparator 33 with a delay of S (this is referred to as IF2). FIG. 6A shows the phase relationship between IF1 and IF2 supplied to the phase comparator 33. However a of the is shown in solid line is shown in dashed lines in IF1 is IF2, the frequency of the MSK modulated wave F0 + FS / 4 and F
Since 0-FS / 4, this is referred to as F1 and F1, respectively.
If it is 2, F1 is from 0 to TS, F2 is from TS to 2TS, and F1 is from 2TS to 3TS. Assuming that the phase difference between IF1 and IF2 in the phase comparator 33 is Φ, the phase comparator 33 outputs sinΦ and supplies it to the extraction circuit 34. FIG. 6B shows the output at this time. Then, the FS component is extracted by the extraction circuit 34, and the phase comparator 35
This output is supplied to the phase comparator 33 at the center frequency FS.
Is output to the phase comparator 35. The output of this component is compared with the output of the VCO circuit 36 having the center frequency FS by the phase comparator 33, and the result appears as an error voltage at the output. AP to VCO circuit 36 after passing through 37
A closed loop that is supplied as a C voltage and controls the output of the VCO circuit 36 so as to cancel out the frequency phase error in the phase comparator 37 (hereinafter, this phase comparator 35, the low-pass filter 37 and the VCO circuit 36 PLL (PH
ASE LOCKED LOOP) circuit. The output of the VCO circuit 36 is also input to a 1/2 frequency dividing circuit 38 to reproduce a clock having a baud rate FS / 2, and this reproduced clock is supplied to the phase detection circuit 22 in FIG. 4 as a reproduced clock. Generally, in the 1/2 frequency divider 38, phase ambiguities of 0 ° and 180 ° occur. In this case, as shown in FIG. 7, the phase relationship between the baseband signal of a-1 and the clock of a-2 is most desirable, but due to this ambiguity, b-1 and b-
A phase relationship like 2 occurs. To solve this problem, the Costas method in the MSK demodulation method is as follows.
By multiplying the two series of baseband signals and further multiplying this by the FS / 2 clock, the phase relationship as shown in a-1 and a-2 with respect to the ambiguity of the clock is as follows. Is configured to be held.

[0003]

When the clock is to be reproduced by the conventional method, the operation tends to be unstable because the reproduction is to be performed using the IF signal, as can be seen from FIGS. 4 and 5. There is a disadvantage that the circuit scale is relatively large.

An object of the present invention is to provide a minimum displacement modulation wave demodulation circuit which can perform a clock recovery operation stably with a relatively small circuit.

[0005]

According to the present invention, there is provided a multiplier for synchronously detecting a minimum displacement modulation wave with a reproduced carrier to generate a two-series baseband signal, and a two-series baseband signal generated by the multiplier. A clock recovery circuit for recovering a clock having a baud rate equal to the baud rate of the band signal, multiplied by two series of baseband signals generated by the multiplier, and further multiplied by a clock recovered by the clock recovery circuit to generate a phase synchronization signal And a voltage-controlled oscillation circuit that provides the multiplier with a reproduction carrier having a frequency corresponding to the signal supplied to the control input. Based on one of the two series of baseband signals generated by the multiplier, the baud rate of the baseband signal is equal to the baud rate of the baseband signal. A configuration for reproducing a clock frequency, pulling the low-pass filter phase-locked signals generated by the phase detection circuit is provided, the phase phase synchronization signal generated by the detection circuit is provided, the phase of the clock a synchronization detection circuit for detecting whether or not the clock is locked, and when the synchronization detection circuit detects that the clock phase is not pulled, the output frequency of the voltage-controlled oscillation circuit is changed in a predetermined direction, And a control circuit that generates a control signal that instructs the voltage-controlled oscillation circuit to perform an automatic frequency control operation when detecting that the control signal has been pulled, a signal that has passed through the low-pass filter, and a control signal that has been generated by the control circuit. And an adder for adding the sum to the control input of the voltage controlled oscillation circuit.

The clock recovery circuit includes a rectifier circuit for performing full-wave rectification on one of the two series of baseband signals generated by the multiplier, and a rectification circuit for performing full-wave rectification using the rectifier circuit. An extraction circuit for extracting a clock having a frequency equal to the baud rate of the baseband signal from the baseband signal, and a phase locked loop circuit connected to the output of the extraction circuit may be provided.

[0007]

The clock is reproduced from the baseband signal. Here, when the beat frequency of the output of the multiplier is high, the phase synchronization circuit gives the phase synchronization information at that time to the synchronization detection circuit, and the synchronization detection circuit controls the sweep / AFC circuit to switch the voltage controlled oscillation circuit to a predetermined state. When sweeping in the direction, the beat frequency gradually lowers, a clock is pulled in, and thereafter, the operation shifts to automatic frequency control to synchronize the reproduced carrier.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are block diagrams showing this embodiment. In this embodiment, as shown in FIG. 1, a multiplier 1 for synchronously detecting a minimum displacement modulation wave with a reproduced carrier to generate a two-series baseband signal, and a two-series baseband signal generated by the multiplier 1 A clock recovery circuit 3 for recovering a clock having a baud rate equal to the baud rate of the band signal is multiplied by a two-series baseband signal generated by the multiplier 1, and further multiplied by the clock recovered by the clock recovery circuit 3 to obtain a phase. Phase detection circuit 2 for generating synchronization signal
And a voltage-controlled oscillating circuit 4 for providing the multiplier 1 with a reproduced carrier having a frequency corresponding to the signal given to the control input,
Further, as a characteristic feature of the present invention, the clock recovery circuit 3 is configured to output a signal having a frequency equal to the baud rate of the baseband signal based on one of the two series of baseband signals generated by the multiplier 1. This is a configuration for recovering a clock, in which a low-pass filter 6 to which a phase synchronization signal generated by the phase detection circuit 2 is provided and a phase synchronization signal generated by the phase detection circuit 2 are provided, and the phase of the clock is drawn. A synchronous detection circuit 8 for detecting whether or not the clock phase is not pulled in. When the synchronous detection circuit 8 detects that the clock phase is not pulled in, the output frequency of the voltage control oscillation circuit 4 is changed in a predetermined direction, sweep-self is a control circuit for generating a control signal for instructing the automatic frequency control operation in the voltage control oscillator circuit 4 detects that the draw phase It includes a frequency control circuit 7, and an adder 5 adds the control signal generated by the signal and the control circuit which has passed through the low-pass filter 6 gives to the control input of the voltage controlled oscillator 4. Here, the clock recovery circuit 3
Is a rectifier circuit 10 for full-wave rectification of one of the two series of baseband signals generated by the multiplier 1, and a baseband signal obtained by full-wave rectification by the rectifier circuit 10. An extraction circuit 11 for extracting a clock having a frequency equal to the baud rate of a signal;
A phase comparison circuit 12, a low-pass filter 13, and a voltage-controlled oscillation circuit, which are phase-locked loop circuits connected to the output of 11,
14 is provided.

It is assumed that the center frequency of the IF signal (MSK modulated wave) is F0 and the data bit rate is FS. The input IF signal is output from a multiplier 1 to a VCO having a center frequency F0.
It is synchronously detected by the reproduced carrier from the circuit 4 and outputs two series of baseband signals (referred to as I and Q).
The baud rate of this baseband signal is FS / 2.
The two series of baseband signals and the clock of frequency FS / 2 reproduced by the clock reproduction circuit 3 are supplied to the phase detection circuit 2. The phase detection circuit 2 supplies a phase synchronization signal to the low-pass filter 6 and the synchronization detection circuit 8 using the Costas method based on the two series of baseband signals and the reproduced clock. Further, the synchronization detection circuit 8 detects whether or not the phase of the clock is pulled in based on the given phase synchronization information, and outputs the detection signal to the sweep / automatic frequency control circuit 7.
When the sweep / automatic frequency control circuit 7 receives a detection signal indicating that the phase of the clock is being pulled in,
When the output frequency of the VCO circuit 4 is stepwise changed in a certain direction, for example, from a high frequency to a low frequency at a certain speed (hereinafter referred to as a sweep), and the clock phase is pulled in, the detection signal at that time is received. VCO circuit 4
Is supplied to the adder 5 so as to cause the AFC operation. The adder 5 adds the output from the low-pass filter 6 and the output from the sweep / automatic frequency control circuit 7 and controls the VCO circuit 4 by the output. The reproduced carrier wave output from the VCO circuit 4 is multiplied by a multiplier. 1 and used for synchronous detection. FIG. 2 is an example of the clock recovery circuit 3 in FIG. One of the two series of signals demodulated by the multiplier 1 is supplied to a rectifier circuit 10, and the output thereof is input to an extraction circuit 11 after being subjected to full-wave rectification. Unlike the prior art, the present invention regenerates a clock from a baseband signal, so the extraction circuit 11 extracts the FS / 2 component and outputs the output to a PLL circuit comprising a phase comparator 12, a low-pass filter 13 and a VCO circuit 14. To obtain a reproduced clock of FS / 2. As described above, since the clock recovery method of the present invention performs clock recovery from the baseband signal,
Assuming that the frequency of the reproduced carrier supplied to the multiplier 1 is F, if the difference between the input IF frequencies F0 and F is large, the multiplier 1
The frequency of the beat signal output from the transmitter is fast, and as a result, two series of data on the transmitting side are respectively transmitted to I0 and Q
If 0, I0 and Q0 are mixed in one channel on the receiving side, and one baseband signal is I0 or Q0.
It is well known that, assuming that the time during which only one of 0 is held is T, the shorter the beat frequency, the shorter the T, and the slower the beat frequency, the longer the T. In the case of the MSK modulation / demodulation method, as shown in FIG. 3, between I0 and Q0 and between I and Q
Since there is a phase difference of 180 °, a signal having two phases in one baseband signal is input to the PLL circuit of FIG. 2, so that the time required for the clock phase to be pulled in is represented by T0. Then, when T <T0, two types of phases are mixed in the input signal of the rectifier circuit 10, the clock phase is not locked, and the reproduction clock is also multiplied by the Costas method in the MSK modulation / demodulation method as described above. Also, the phase of the recovered carrier is not synchronized. Therefore, FIG.
In the figure, a sweep / automatic frequency control circuit 6 is provided. When the beat frequency of the output of the multiplier 1 is fast (when T <T0), the phase detection circuit 2 supplies the phase synchronization information at that time to the synchronization detection circuit 8, and the synchronization detection circuit 8 performs a sweep / automatic frequency control circuit. 7 is given an "H" signal, whereby the sweep / automatic frequency control circuit 7 sweeps the VCO circuit 4 in a fixed direction. During this fixed sweep, the beat frequency gradually decreases, and when T> T0, the phase of the clock is pulled in. The synchronization detection circuit 8 receiving the synchronization information at that time outputs "L", and the sweep / auto The frequency control circuit 7 shifts to the AFC operation, after which the reproduced carrier is also synchronized.

[0010]

As described above, according to the present invention, since the clock is reproduced from the demodulated signal, a relatively small-scale and stable operation can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock recovery circuit in FIG. 1;

FIG. 3 is a diagram showing a phase relationship between two series of baseband signals.

FIG. 4 is a block diagram showing the configuration of a conventional example.

FIG. 5 is a block diagram showing a configuration of a clock recovery circuit in FIG. 2;

FIG. 6 is a view showing a phase relationship between two inputs of the phase comparator in FIG. 5;

FIG. 7 is a view showing a phase relationship between a clock from a 1/2 frequency divider circuit in FIG. 5 and a baseband signal;

[Explanation of symbols]

1, 20 Multiplier 2, 22 Phase detection circuit 3, 21 Clock recovery circuit (CLK recovery circuit) 4, 23, 36, 14 Voltage control oscillation circuit (VCO circuit) 5 Adder 6, 37, 13 Low-pass filter 7 Sweep / automatic frequency control circuit (Sweep / AFC circuit) 8 Synchronization detection circuit 10 Rectification circuit 11, 34 Extraction circuit 12, 33, 35 Phase comparator 31 90 ° shift circuit 32 Delay circuit 38 1/2 frequency dividing circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-206349 (JP, A) JP-A-60-208146 (JP, A) JP-A-60-183858 (JP, A) JP-A 61-208 216555 (JP, A) JP-A-58-70664 (JP, A) JP-A-62-222744 (JP, A) JP-A-59-75743 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) [Claims] 1. Synchronous detection of a minimum deviation modulation wave with a reproduced carrier wave
A multiplier for generating two series of baseband signals, and a two-phase baseband signal generated by the multiplier.
Clock that reproduces a clock with a baud rate equal to the
And a two-phase baseband signal generated by the multiplier.
And the clock recovered by the clock recovery circuit.
Phase detection circuit that locks and generates a phase synchronization signal
And a reproduced carrier having a frequency corresponding to the signal supplied to the control input.
And a voltage-controlled oscillator for providing the multiplier with
In the displacement modulation wave demodulation circuit, the clock recovery circuit is a two-system clock generated by the multiplier.
One of the baseband signals in the row
Equal to the baud rate of this baseband signal based on the signal
It is a configuration that reproduces the clock of the frequency, and receives the phase synchronization signal generated by the phase detection circuit.
A low-pass filter, and a phase synchronization signal generated by the phase detection circuit.
The phase of the clockToDetecting whether or not the user is engaged
The synchronization detection circuit and the clock phaseToNot retracted
That the output frequency of the voltage controlled oscillator circuit is
Change in a predetermined direction, phaseToCheck that you are
The automatic frequency control operation to the voltage controlled oscillator circuit
A control circuit for generating a control signal for instructing, a signal passed through the low-pass filter and the control circuit
Adding the generated control signal to the voltage-controlled oscillation circuit
And an adder to be applied to the control input of, The clock recovery circuit includes a two-system clock generated by the multiplier.
One of the baseband signals in the row
Rectifier circuit that performs full-wave rectification on signals and full-wave rectification with this rectifier circuit
Of the baseband signal from the baseband signal
Circuit that extracts a clock with a frequency equal to the rate
And the position connected to the output of this extraction circuit Phase locked loop times
With the road A minimum displacement modulation wave demodulation circuit, characterized in that:
Road.