JPH04262649A - Demodulation circuit for minimum deviation modulation wave - Google Patents

Abstract

PURPOSE:To attain stable operation with a comparatively small scale by reproducing a clock from a demodulation signal. CONSTITUTION:A clock reproduction circuit 3 reproduces a clock with a frequency equal to a baud rate of a base band signal based on either base band signal of two systems of base band signals generated by a multiplier 1. When a beat frequency being an output of the multiplier 1 is high, a phase detection circuit 2 gives phase synchronization information at that time to a synchronization detection circuit 8. The synchronization detection circuit 8 controls a sweep AFC circuit 7 to allow a voltage control oscillator circuit 4 to be swept in a prescribed direction, then the beat frequency gets lower gradually thereby locking the clock. Then the automatic frequency control is transited and a reproduced carrier is synchronized.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention is applied to clock recovery means for a digital satellite communication system. In particular, the present invention relates to clock recovery means in a minimum deviation keyed wave (hereinafter referred to as MSK) modulation and demodulation system.

0002

2. Description of the Related Art FIG. 4 shows a clock recovery means of a conventional MSK demodulation circuit for demodulating an MSK modulated wave. However, M.S.
Let the center frequency of the IF signal input to the K demodulation circuit be F0, and the bit rate of the transmitted data be FS. The input IF signal (MSK modulated wave) is converted to VC by the multiplier 20.
Synchronous detection is performed using the regenerated carrier wave (frequency is F) output from the O circuit 23, and two series of baseband signals are output. These two series of signals are referred to as I and Q (both have a baud rate of FS/2), and the output I and Q are used as reproduction data and are input to the phase detection circuit 22. The input IF signal is also input to the clock regeneration circuit 21, which regenerates the FS/2 clock and supplies it to the phase detection circuit 22. The phase detection circuit 22 uses the Costas method to set VC so that F=F0.
The APC voltage of the O circuit 23 is supplied. FIG. 2 shows an example of the clock recovery circuit 21 in detail. As shown in FIG. 2, one of the IF signals is supplied to the phase comparator 33 (this is referred to as IF1), and the other one is supplied to the 90° shift circuit 31 with a phase delay of 90°, TS=1/ If it is FS, it is further delayed by TS in the delay circuit 32 and then supplied to the phase comparator 33 (this is designated as IF2). This phase comparator 3
FIG. 6A shows the phase relationship between IF1 and IF2 supplied to IF1 and IF2. However, what has been shown in actual combat is IF1
The dashed line in IF2 is IF2, and the frequencies of the MSK modulated wave are F0+FS/4 and F0-FS/4, so if these are F1 and F2, respectively, 0 to T
Up to S is designated as F1, from TS to 2TS is designated as F2, and from 2TS to 3TS is designated as F1. IF at phase comparator 33
If the phase difference between IF1 and IF2 is Φ, the phase comparator 33 outputs sinΦ and supplies it to the extraction circuit . Figure 6b shows the output at this time. Then, the extraction circuit 34 extracts the component of FS and supplies it to the phase comparator 35, and the phase comparator 33 extracts the component of the center frequency FS and supplies it to the phase comparator 35. The phase is compared with the output of the VCO circuit 37 at the center frequency FS in the device 33, and the result appears as an error voltage at the output, passes through the low-pass filter 36, and is output to the VCO circuit 37.
It is supplied as a PC voltage and becomes a closed loop that controls the output of the VCO circuit 37 so as to cancel the frequency phase error in the phase comparator 35 (hereinafter, it is composed of this phase comparator 35, low-pass filter 36, and VCO circuit 37) This circuit is called a PLL (PHASE LOCKED LOOP) circuit). The output of the VCO circuit 37 is the 1/2 frequency divider circuit 3.
8, a clock with a baud rate of FS/2 is regenerated, and this regenerated clock is supplied to the phase detection circuit 22 in FIG. 4 as a regenerated clock. Generally, in the 1/2 frequency divider circuit 38, phase ambiguities of 0° and 180° occur. In this case, as shown in FIG. 7, the phase relationship between the baseband signal of a-1 and the clock of a-2 is originally the most desirable, but due to this ambiguity, the phase relationship between b-1 and b-2 is A phase relationship like this will occur. To solve this problem, the Costas method in the MSK demodulation method multiplies two series of baseband signals and then adds FS/
By multiplying the clock by 2, the pull-in phase of the regenerated CARR becomes a-1 and a
-2 is configured to maintain the phase relationship shown in FIG.

0003

[Problems to be Solved by the Invention] When attempting to reproduce a clock using the conventional method, as can be seen from FIGS. 4 and 5, the operation tends to become unstable because the reproduction is attempted using an IF signal. However, the disadvantage is that the circuit scale is relatively large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a minimum deviation modulated wave demodulation circuit which is a relatively small-scale circuit and which can stably perform a clock recovery operation.

[0005]

[Means for Solving the Problems] The present invention provides a multiplier that generates two series of baseband signals by synchronously detecting a minimum deviation modulated wave using a regenerated carrier wave, and a multiplier that generates two series of baseband signals by synchronously detecting a minimum deviation modulated wave using a regenerated carrier wave. A clock regeneration circuit that regenerates a clock with a baud rate equal to the baud rate of the band signal is multiplied by the two series of baseband signals generated by the multiplier, and then multiplied by the clock regenerated by the clock regeneration circuit to generate a phase synchronized signal. and a voltage-controlled oscillation circuit that provides the multiplier with a recovered carrier wave having a frequency corresponding to a signal applied to a control input. , is configured to reproduce a clock having a frequency equal to the baud rate of the baseband signal based on one of the baseband signals of the two series of baseband signals generated by the multiplier, and the clock having a frequency equal to the baud rate of this baseband signal is generated by the phase detection circuit. A low-pass filter is provided with a phase synchronization signal, a synchronization detection circuit is provided with a phase synchronization signal generated by the phase detection circuit, and detects whether or not the phase of the clock is being pulled in. A control signal that changes the output frequency of the voltage controlled oscillation circuit in a predetermined direction when it detects that the phase of and an adder that adds the signal passed through the low-pass filter and the control signal generated by the control circuit and supplies the result to the control input of the voltage-controlled oscillation circuit. shall be.

[0006] Here, the clock regeneration circuit includes a rectifier circuit that performs full-wave rectification of one of the two series of baseband signals generated by the multiplier, and a rectifier circuit that performs full-wave rectification of one of the two baseband signals generated by the multiplier. It may also include an extraction circuit that extracts a clock having a frequency equal to the baud rate of the baseband signal from the baseband signal, and a phase-locked loop circuit connected to the output of the extraction circuit.

[0007]

[Operation] Regenerates the clock from the baseband signal. Here, when the beat frequency of the output of the multiplier is high, the phase synchronization circuit provides the phase synchronization information at that time to the synchronization detection circuit, and the synchronization detection circuit controls the sweep/AFC circuit to control the voltage controlled oscillation circuit to a predetermined level. When swept in the direction, the beat frequency gradually decreases, and the clock is pulled in.
After this, the system shifts to automatic frequency control and the regenerated carrier wave is also synchronized.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are block diagrams showing this embodiment. This embodiment, as shown in FIG. A clock regeneration circuit 3 that regenerates a clock with a baud rate equal to the baud rate of the band signal is multiplied by the two series of baseband signals generated by the multiplier 1, and further multiplied by the clock regenerated by the clock regeneration circuit 3 to generate a phase signal. It comprises a phase detection circuit 2 that generates a synchronization signal, and a voltage controlled oscillation circuit 4 that supplies the multiplier 1 with a recovered carrier wave of a frequency corresponding to a signal applied to a control input, and furthermore, as a feature of the present invention, The clock regeneration circuit 3 is configured to regenerate a clock having a frequency equal to the baud rate of the baseband signal based on one of the two series of baseband signals generated by the multiplier 1, and uses phase detection. A low-pass filter 6 is provided with the phase synchronization signal generated by the circuit 2, and a synchronization detection circuit 8 is provided with the phase synchronization signal generated by the phase detection circuit 2 and detects whether or not the clock phase is being pulled in. When this synchronization detection circuit 8 detects that the phase of the clock is not pulled in, it changes the output frequency of the voltage controlled oscillation circuit 4 in a predetermined direction, and when it detects that the phase is pulled in, it changes the output frequency of the voltage controlled oscillation circuit 4. A sweep/automatic frequency control circuit 7, which is a control circuit that generates a control signal that instructs automatic frequency control operation, and a low-pass filter 6.
and a control signal generated by the control circuit, and an adder 5 for adding the signal passed through the control circuit and the control signal generated by the control circuit and applying the result to the control input of the voltage controlled oscillation circuit 4. Here, the clock regeneration circuit 3 is
A rectifier circuit 1 that performs full-wave rectification of one of the two series of baseband signals generated by the multiplier 1.
0, an extraction circuit 11 that extracts a clock having a frequency equal to the baud rate of this baseband signal from the baseband signal full-wave rectified by this rectification circuit 10, and a phase locked loop circuit connected to the output of this extraction circuit 11. It includes a phase comparison circuit 12, a low-pass filter 13, and a voltage-controlled oscillation circuit 14.

However, the center frequency of the IF signal (MSK modulated wave) is F0, and the data bit rate is FS. The input IF signal is sent to the VCO with center frequency F0 by multiplier 1.
Synchronous detection is performed using the reproduced carrier wave from the circuit 4, and two series of baseband signals (these are referred to as I and Q) are output. The baud rate of this baseband signal is FS/2. These two series of baseband signals and the clock of frequency FS/2 regenerated by the clock regeneration circuit 3 are supplied to the phase detection circuit 2. The phase detection circuit 2 applies a phase synchronization signal to the low-pass filter 6 and the synchronization detection circuit 8 using the Costas method using two series of baseband signals and a regenerated clock. Furthermore, the synchronization detection circuit 8 detects whether or not the clock phase is pulled in based on the given phase synchronization information, and uses the detected signal as a sweep/automatic frequency control circuit 7.
When the sweep/automatic frequency control circuit 7 receives a detection signal indicating that the clock phase is decreasing,
When the output frequency of the VCO circuit 4 is changed stepwise in a certain direction, for example from a high frequency to a low frequency, at a certain speed (hereinafter referred to as a sweep) and the phase of the clock is pulled in, the detection signal at that time is received. VCO circuit 4
A control signal is given to the adder 5 to perform the AFC operation. The adder 5 adds the output from the low-pass filter 6 and the output from the sweep/automatic frequency control circuit 7, controls the VCO circuit 4 by the output, and the recovered carrier wave output from the VCO circuit 4 is sent to the multiplier. 1 and used for synchronous detection. FIG. 2 is an example of the clock recovery circuit 3 in FIG. One of the two series of signals demodulated by the multiplier 1 is supplied to a rectifier circuit 10, and its output is input to an extraction circuit 11 after being full-wave rectified. Unlike the conventional method, in the present invention, the clock is regenerated from the baseband signal, so the extraction circuit 11 extracts the FS/2 component, and the output is sent to the PLL circuit consisting of the phase comparator 12, the low-pass filter 13, and the VCO circuit 14. It is possible to obtain a recovered FS/2 clock by inputting the FS/2 clock into the FS/2 clock. As described above, since the clock recovery method of the present invention performs clock recovery from the baseband signal, if the frequency of the recovered carrier wave supplied to the multiplier 1 is F, the difference between the input IF frequency F0 and F is large. and the frequency of the beat signal output from multiplier 1 is fast,
As a result, the two series of data on the transmitting side are
0 and Q0, I0 and Q0 will be mixed in one channel on the receiving side, and one baseband signal will be I
It is well known that if the time during which only one of 0 and Q0 is held is T, the earlier the beat frequency is, the shorter T is, and the slower the beat frequency is, the longer T is. In the case of MSK modulation and demodulation, there is a 180° phase difference between I0 and Q0 and between I and Q as shown in Figure 3, so a signal with two phases in one baseband signal is Therefore, if the time required for the clock phase to be pulled in is T0, then when T<T0, the input signal to the rectifier circuit 10 has two types of phases, The clock phase is not locked, and as mentioned above, M
In the Costas method of the SK modulation and demodulation method, the reproduced clock is also multiplied, so the phase of the reproduced carrier wave is also not synchronized. Therefore, a sweep/automatic frequency control circuit 6 is provided in FIG. When the beat frequency of the output of the multiplier 1 is fast (T<T0), the phase detection circuit 2 provides the phase synchronization information at that time to the synchronization detection circuit 8, and the synchronization detection circuit 8 performs a sweep/automatic frequency control circuit. 7 is given an "H" signal, thereby causing the sweep/automatic frequency control circuit 7 to sweep the VCO circuit 4 in a fixed direction. Then, during this fixed sweep, the beat frequency gradually becomes slower and T>
At T0, the phase of the clock is pulled in, the synchronization detection circuit 8 that has received the synchronization information at that time outputs "L", the sweep/automatic frequency control circuit 7 shifts to AFC operation, and then the reproduced carrier wave is also synchronized.

0010

As explained above, the present invention has the advantage that since a clock is regenerated from a demodulated signal, stable operation can be achieved on a relatively small scale.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing the configuration of the clock recovery circuit in FIG. 1.

FIG. 3 is a diagram showing the phase relationship between two series of baseband signals.

FIG. 4 is a block configuration diagram showing the configuration of a conventional example.

5 is a block configuration diagram showing the configuration of the clock recovery circuit in FIG. 2. FIG.

6 is a diagram showing the phase relationship between two inputs of the phase comparator in FIG. 5. FIG.

FIG. 7 is a diagram showing the phase relationship between the clock from the 1/2 frequency divider circuit in FIG. 5 and the baseband signal.

[Explanation of symbols]

1, 20 Multiplier 2, 22 Phase detection circuit 3, 21
Clock regeneration circuit (CLK regeneration circuit) 4, 23, 36, 14 Voltage controlled oscillation circuit (VCO circuit) 5 Adder 6, 37, 13 Low pass filter 7
Sweep/Automatic frequency control circuit (Sweep/AF
C circuit)

Claims (2)

[Claims] 1. A multiplier that generates two series of baseband signals by synchronously detecting a minimum deviation modulated wave using a regenerated carrier wave;
A clock regeneration circuit that reproduces a clock having a baud rate equal to the baud rate of the two series of baseband signals generated by the multiplier, and a clock regeneration circuit that multiplies the two series of baseband signals generated by the multiplier. a phase detection circuit that generates a phase-synchronized signal by multiplying the clock regenerated by the control input, and a voltage-controlled oscillator circuit that provides the multiplier with a regenerated carrier wave with a frequency corresponding to the signal applied to the control input. In the modulated wave demodulation circuit, the clock regeneration circuit is configured to regenerate a clock having a frequency equal to the baud rate of the baseband signal based on one of the two series of baseband signals generated by the multiplier. A low-pass filter is provided with the phase synchronization signal generated by the phase detection circuit, and a low-pass filter is provided with the phase synchronization signal generated by the phase detection circuit, and detects whether or not the clock phase is being pulled in. When the synchronization detection circuit detects that the phase of the clock is not pulled in, it changes the output frequency of the voltage controlled oscillation circuit in a predetermined direction, and when it detects that the phase is pulled in, it changes the output frequency of the voltage controlled oscillation circuit. a control circuit that generates a control signal that instructs the circuit to perform automatic frequency control; and a control input for the voltage controlled oscillation circuit that adds the signal that has passed through the low-pass filter and the control signal generated by the control circuit. A minimum deviation modulated wave demodulation circuit comprising: 2. The clock regeneration circuit includes a rectifier circuit that performs full-wave rectification of one of the two series of baseband signals generated by the multiplier, and a rectifier circuit that performs full-wave rectification of one of the baseband signals of the two series of baseband signals generated by the multiplier. Minimum deviation modulation wave demodulation according to claim 1, further comprising an extraction circuit for extracting a clock having a frequency equal to the baud rate of the baseband signal from the baseband signal, and a phase-locked loop circuit connected to the output of the extraction circuit. circuit.