JPS62118660A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To attain carrier recovery without hungup even to a modulation wave by eliminating a modulation component so as to give a hysteresis characteristic to a phase comparison characteristic. CONSTITUTION:A biphase PSK modulation signal is inputted to an input signal terminal 1 and a difference component between an error phase of an input signal of sin(2theta-2theta') and a phase of a signal from a voltage controlled oscillator 10 is obtained at a multiplier output 7 as a signal 701. Sin(thetak+theta-theta') and cos(thetak+theta-theta') being outputs of LPFs 5, 6 are inputted to square devices 13, 14 in addition to the signal sin(2theta-2theta') to generate signals sin<2>(thetak+theta-theta') and cos<2>(thetak+theta-theta'), which are given to an adder 15 to form a signal cos(2theta-2theta'), and phase difference signals 701, 1501 whose phase is shifted by theta/2 radian are obtained. Thus, in inputting the output of level decision devices 11, 12 to a phase comparator 8', a control voltage not causing hungup is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a carrier regeneration circuit for creating a reference signal necessary for synchronously detecting a modulated signal in which a carrier component has been suppressed.

(Prior art) The Costas loop method, which is one of the carrier wave regeneration methods, uses baseband processing to remove the modulation components of the received signal, and uses this baseband processing to remove the voltage-controlled excavator (
A phase difference signal can be obtained to control the VCO). For this reason, the Costas loop method is easy to digitize the circuits that make up the system, and the carrier regeneration circuit is small and
This method allows for low metering and low power consumption.

However, this carrier wave regeneration circuit using the Costas loop method suffers from a phenomenon called a hang-up phenomenon in which the phase pull-in characteristic deteriorates, making it difficult to apply it where phase synchronization must be established in a short period of time.

First, the hang-up phenomenon will be explained using an example of the Costas loop method. FIG. 2 is a diagram showing the basic configuration of a carrier wave regeneration circuit using the Costas loop method.

In Figure 2, 1 is the received signal input terminal, 2, 3
．． 7 is a multiplier, 4 is a π/2 radian phase shifter, 5 and 6 are low pass filters (LPF), 8 is a phase comparator, 9 is a loop filter, and IO is a voltage controlled oscillator (VCO). The figure shows a configuration example in the case of a two-phase PSK system, and the received signal S (t) of the k-th time slot is expressed as in equation (1).

S (t) = A cos (10 for ωct+θ)
-(1)(k-1)TkutkukT However, T is the boat rate, ω. is the carrier wave angular frequency, and θ is the phase information. In the case of the two-phase PSK method, θ is given a phase of 0 for information “1” and a phase of π radian for information “0”, for example. A indicates the signal amplitude level, and θ indicates a phase error due to noise on the transmission path. The received signal in equation (1) is the regenerated carrier cos (ωe1
10) and the signal sin (ωat10) whose phase is shifted by π/2 radians to
and are respectively multiplied by 2.3 output signal 201°3
01 passes through low-pass filters 5 and 6, respectively, to remove high frequency components, resulting in signals 501 and 60.
1 is each sin (θ×10−〇); COS (
The signal is expressed as θ, 10-0).

The signals of 501 and 601 are multiplied by multiplier 7, and 5in(
2θ, +2O−20) signal 701 is output. Here, since the system is a two-phase PSK system, either O1π is selected for θ. Therefore, it becomes 0 or 2π at 20, which means that the modulation component at θ has been removed, and only the phase difference component of the received signal phase error θ and the control phase θ from the voltage controlled oscillator 10 has been extracted. Become.

5 inches (2θ-20) is input to the phase comparator 8, and the phase difference (
2θ-20) is output. The control voltage 801 is applied to the voltage controlled oscillator lO via the loop filter 9, and a recovered carrier wave having a control phase of θ such that (2θ−20) becomes zero is outputted from the voltage controlled oscillator 10 as 1001. In this way, the Costas loop method is suitable for digitization because modulation components can be removed by baseband processing.

However, as can be seen from the phase comparison characteristics in FIG. The oscillation phase of the oscillator 10 does not change and the phase difference is π
It becomes stable as it is, and synchronization becomes impossible. This phenomenon is called a hang-up phenomenon. Furthermore, even if the phase difference is not exactly π, when it is extremely close to π, a phenomenon that can be regarded as a hang-up occurs, and the output of the phase comparator 8 becomes a value close to zero, and it takes a long time to establish the synchronization probability. There were drawbacks. Because of these drawbacks, it has been difficult to employ the Costas loop method as a carrier wave regeneration circuit when demodulating a TDMA signal consisting of a plurality of mutually asynchronous burst signals. This is because each burst signal must be demodulated while creating a reference signal, and the carrier regeneration circuit must establish phase synchronization within an extremely short period of time.

In order to solve this problem, the present applicant has previously proposed a phase-locked circuit that relieves the hang-up phenomenon and improves the synchronization pull-in characteristic (Japanese Patent Application No. 137269/1982).

This prior art will be briefly described below.

In this method, the phase comparison characteristic has
It is characterized by having hysteresis characteristics with two types of phase comparison outputs depending on the history of phase changes.

FIG. 4 shows an example of the configuration of a phase-locked circuit having hysteresis characteristics in its phase comparison characteristics.

1° is a signal input terminal, and it is assumed that an unmodulated signal from which modulation components have been removed is input to 1''.

The human-powered non-modulated signal is phase-detected using a 2.3 multiplier with the signals from the 10 voltage-controlled oscillators and the π/2 radian phase-shifted signal, and passes through a 5.6 LPF to remove harmonic components. sin θ having a phase difference θ between the input signal and the signal from the voltage controlled oscillator 10 at 51° and 61°,
cos θ is output. These signals are processed by the level determiner 11.12, which determines the logic level of the signal 1101.
1201. These logic level signals 11
01.1200 is input to a phase comparator 8°, where logic processing is performed, and a phase comparison output 801' corresponding to the logic level of each signal is produced.

FIG. 5 shows the relationship between the waveforms of each part and the phase comparison characteristics. (a) shows the waveform (cosine wave) of the output signal 51' of the LPF 5, and (b) shows the waveform (cosine wave) of the output signal 61' of the LPF 6. sine wave), (C) is the waveform of the output signal 11 inches of the level judger 11, (d) is the waveform of the output signal 1201 of the level judger 12, (e) is the waveform (C) and (d) of the logic level. (f) is the phase comparison characteristic. In addition,
(f) The arrow in the figure indicates the control direction (convergence direction) of the voltage controlled oscillator 100.

That is, the phase comparator 8' basically has a phase difference θ of -π/2 between the input signal and the output signal of the voltage controlled oscillator 10.
When it is in the range of ~π/2, it outputs sin&, and when it is in the range of π/2~
+1 when it is in the range of 3π/2. −3π/2～−π/
If it is in the range of 2, outputs ~1. The voltage controlled oscillator 10 controlled by this output has a phase difference θ of -3π/2 to 3
When it is between π/2, it operates so as to converge to the phase indicated by 0 in the figure (f).

Here, the hysteresis characteristics will be explained. For example, when the phase difference θ exceeds +3π/2, the phase comparator 8' outputs sin θ again. This is to cause a kind of phase slip to converge to the point indicated by 2π in the diagram (f).

Therefore, even if the phase difference θ becomes smaller than 3π/2 again, it is treated as a range of -π/2 to -3π/2 from the point of 2π, so the output of the phase comparator 8' becomes -1. . Furthermore, when the phase difference θ becomes smaller and falls within π/2,
The output of the phase comparator 8° becomes sin θ again, causing a phase slip here as well, and operates to converge to the point indicated by 0 in the figure (f). After this, if the phase difference θ becomes larger than π/2 again, the output of the phase difference comparator 8' becomes +1.
becomes.

As described above, the phase comparator 8' operates so that the phase difference θ has a bisteresis width of ±π/2 around π or 1π. Here, these two types of phase comparison outputs are the fourth
Control can be achieved by processing two logic levels having a phase shift of π/2 radians, as shown in FIG. 3(e).

By imparting the bisteresis characteristic to the phase comparison @8'' in this way, the drawbacks of the prior art described in FIGS. 2 and 3 are solved as follows.

As can be seen from the difference in phase comparison characteristics between FIG. 3 and FIG. 5(f), in FIG. 5(f), for example, −2π,
Since the output of the phase comparator 8° never becomes 0 or its vicinity except at the convergence point indicated by 0, 2π, the hang-up phenomenon seen in the prior art cannot occur. Also,
Even if the phase difference θ exceeds ±π/2, the output of the phase comparator 8' remains at the maximum value of the control voltage value without decreasing, so that the voltage controlled oscillator 10 can be controlled at high speed.

(Problem to be solved by the invention) The hydraulic type that has a hysteresis characteristic in the phase comparison characteristic can avoid the hang-up phenomenon, but as explained above, the input signal of the circuit is unmodulated. It needs to be a signal. Therefore, it is necessary to remove modulation components from the modulation signal in some way in terms of this circuit. Generally, a multiplication method is considered as a means for removing the modulation component of the PSK signal, but in this case, it is also necessary to divide the frequency of the reproduced carrier wave by the multiplied amount, and a multiplier circuit and a frequency division circuit are required. When realizing these circuits, it is difficult to digitize them when the frequency is high, and this remains a problem that must be solved in order to achieve smaller size, lighter weight, and lower power consumption.

(Means for Solving the Problems) The present invention has been made to solve the above-mentioned drawbacks of the prior art. The purpose is to realize a regeneration circuit.

The feature of the present invention is to create a new phase difference signal that is phase-shifted by π/2 radians from the phase difference signal input to the phase comparator in the Costas loop circuit of the prior application, and to convert these two signals. This is used in a carrier wave regeneration circuit that operates a phase comparator having a hysteresis characteristic in its phase comparison characteristic.

(Structure and operation of the invention) FIG. 1 shows an embodiment of the present invention, (a)
(b) is a 2-phase PSK signal as a modulation signal, and (b) is a 4-phase PSK signal.
This figure shows a carrier wave regeneration circuit assuming a signal.

The embodiment shown in FIG. 1(a) will be described in comparison with the conventional Costas loop circuit shown in FIG.

In FIG. 1(a), 1 is an input signal terminal, into which a two-phase PSK modulated signal is input. As explained in FIG. 2, the difference component between the error phase of the input signal of 5 inches (2θ-20) and the phase of the signal from the voltage controlled oscillator of 10 is obtained as a signal 701 at the output of the multiplier 7.

In the present invention, in addition to sin (2θ-20), 5
．． Input sin (θ1 + θ-〇) and cos (θ, +θ-θ), which are the LPF outputs of 6, into the squarer of 13.14,
+θ-〇) is created and these signals are passed through 15 adders to synthesize cos (2θ-2θ). Therefore, phase difference signals having a phase shift of θ/2 radians are obtained as the signal 701 and the signal 1501, respectively. This is the same as the signals 51' and 61' in the phase synchronized circuit having a hysteresis characteristic in the phase comparison characteristic shown in FIG. Therefore, as explained in FIG. 4, by manually inputting the 11°12 level determiner output to the 8° phase comparator, a control voltage that does not cause the hang-up phenomenon can be obtained.

As a result, by making the operation after the output of 7.15 in Figure 1(a) the same as the operation after the output of 5.6 in Figure 4, the circuit of Figure 1(a) can be used as an input signal. This provides a carrier wave regeneration circuit that can handle modulated signals as they are and does not cause a hang-up phenomenon.

On the other hand, FIG. 1(b) shows a case where one input signal is assumed to be a four-phase PSK signal. In the case of a 4-phase PSK signal, the phase taken by θ is 0. π/2. π, 3π/2 radians.

Therefore, if it is 40, 0, 2π, 4π respectively
, 6π radians, and the modulation component can be removed. sum calculator 1
5 and the output of multiplier 7, respectively.
'l), cos (4θ-40) signals are obtained,
At this point, the modulation components of the 4-phase PSK signal have been removed, π
Two phase difference signals having a phase shift of /2 radian are obtained. Therefore, the subsequent operations are also as shown in Figure 1(a).
By doing the same as in the case of , it is possible to realize a carrier wave regeneration circuit for a 4-phase PSK signal without a hang-up phenomenon.

(Effects of the Invention) According to the carrier wave reproducing circuit according to the present invention, it is possible to directly reproduce a reference signal from a modulated signal without a hang-up phenomenon without requiring any means for removing modulated components. Furthermore, as is clear from the embodiment shown in FIG. 1, 5.6
The subsequent signals are baseband signals, and the subsequent circuits can be easily digitized, making it possible to make the carrier regeneration circuit smaller, lighter, and with lower power consumption.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams showing an embodiment of the present invention, FIG. 2 is a diagram showing a conventional Costas loop circuit, FIG. 3 is a diagram showing the phase comparison characteristics of FIG. 2, and FIG. FIG. 4 is a diagram showing a phase locked circuit in which the phase comparison characteristic has bisteresis characteristics, and FIG. 5 is an explanatory diagram of the operation of FIG. 4.

Claims (1)

[Claims] Multiplication means for obtaining two baseband signals by individually multiplying input signals by output signals of voltage controlled oscillators having a phase difference of π/2, and modulation component removal means for removing modulation components from the baseband signals. and a phase comparison means having a hysteresis characteristic that outputs a phase comparison output of 1 or -1 according to the history of changes in the phase of two phase difference signals having a mutual phase difference of π/2 of the modulation component removal means. and has
A carrier wave regeneration circuit characterized in that the oscillation frequency of the voltage controlled oscillator is controlled by the output of the phase comparison means, and the oscillation frequency is synchronized with the input signal.