JPS6330049A - Msk demodulation circuit - Google Patents

Abstract

PURPOSE:To stably demodulate a carrier suppression both side band signal by applying synchronization detection to an input modulation signal converted into an intermediate frequency, multiplying an in-phase component output with an orthogonal component output, multiplying the result with a 1/2 frequency division signal in the timing clock and using a filter so as to extract the DC component of the multiplication signal. CONSTITUTION:A signal given to an input terminal 1 and the output of a local oscillator 2 are subjected to beat down, and waveform equalization is applied by a BPF 6. Its output is subjected to synchronization detection by using a signal shifted by pi/2 phase shifter 10 to form the base band signals of 0-phase and pi/2 phase respectively by using LPFs 11, 12. The signals are decided to be 1 or -1 by deciding circuits 11, 12 and inputted to a digital signal processing circuit 16 as a binary digital signal. further, the outputs of the BPFs 11, 12 are fed to a 3rd multiplier 18, its outputs are used as the input to a 4th multiplier 19 and multiplied with a clock signal being subjected to 1/2 frequency division of a recovered data transmission frequency by a clock recovery circuit 21. Then the output of the 4th multiplier 19 is fed back to a 2nd local oscillator 4 via a loop filter 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MSK demodulation circuit that stably generates an intermediate frequency when demodulating a carrier-suppressed double-sided band signal.

[Conventional technology]

The phase-continuous FSX signal has a constant envelope of the modulated wave, and the main spectrum is not affected by suppression due to output amplifier saturation, etc., so it is an advantageous modulation method for transmission lines including these nonlinear systems.

In particular, a phase continuous FSK signal with a modulation index of 0.5 is M S K
(Minin+um 5hift Keying
) is called a signal.

It is attracting attention as an efficient modulation method with a narrow occupied bandwidth.

For conventional demodulation circuits that use a synchronous detection method to demodulate received MSK signals, the method of regenerating the carrier wave, which is the reference signal, is important. A Costas loop is used to extract a carrier wave phase error signal and control a voltage controlled oscillator to obtain a carrier wave. However, if the frequency fluctuation of the carrier wave is large, demodulation cannot be achieved in the best condition.
The drawback was that performance deteriorated.

[Problem that the invention seeks to solve]

The above conventional technology uses a voltage controlled oscillator (V
The carrier wave can be regenerated and the modulated wave can be demodulated by designing the carrier wave (CO) etc. in accordance with the magnitude of the fluctuation. However, with respect to the intermediate frequency drift caused by the drift of the local oscillator as in the case of a hetrodyne receiver, consideration must be given to the excess or deficiency of sidebands caused by the fixed bandpass filter for passing the intermediate frequency, and the phase shift of the T phase shifter of the carrier wave. However, there was a problem in that the error rate of the reproduced signal deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a demodulation circuit for a hetrodyne receiver that stably demodulates carrier-suppressed double-side band signals such as MSK.

[Means for solving problems]

The above object is achieved by configuring the demodulation circuit as follows. That is, an in-phase carrier wave is obtained using a fixed crystal oscillator for reference carrier wave oscillation, and the phase of this in-phase carrier wave is shifted by an f phase shifter to obtain an orthogonal carrier wave.

The input modulation signal converted to an intermediate frequency is synchronously detected using an in-phase carrier wave and a quadrature carrier wave, and the output of the in-phase component and the quadrature component are multiplied, and further multiplied by a half-divided signal of the timing clock, which is the data transmission frequency. The DC component of the multiplied signal is extracted as a carrier phase error signal using a loop filter. This carrier wave phase error signal controls a local oscillator in a frequency conversion circuit that converts to an intermediate frequency to form a type of PLL, thereby absorbing frequency fluctuations of a modulated signal input to one frequency conversion circuit.

[Effect]

With the above configuration, a modulated wave with one frequency fluctuation is converted by the frequency conversion circuit into a stable intermediate frequency without frequency fluctuation. As a result, demodulation can be performed without excess or deficiency of sidebands due to the fixed intermediate frequency band pass filter, and without phase shift of the T phase shifter of the carrier wave, so the demodulation circuit operates in the best condition and reproduces. The signal error rate does not deteriorate.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and this figure shows an embodiment in which the carrier frequency is lowered by a double heterodyne system having two intermediate frequencies and an MSK signal is demodulated. .

In FIG. 1, 1 is an input terminal, 2 is a first local oscillator, 3 is a first mixer, 4 is a second local oscillator, and 5 is a second local oscillator.
6 is a band pass filter (BPF), 7 is a first multiplier, 8 is a second multiplier LPF, 13 is a first judgment circuit, 14 is a second judgment circuit, 15 is a an inverting circuit; 16 is a digital signal processing circuit;
17 is a reproduction signal output terminal, 18 is a third multiplier, 19 is a fourth multiplier, 20 is a loop filter, and 21 is a clock recovery circuit.

In the figure, a signal applied to an input terminal 1 and the output of a first local oscillator 2 are beat down using a first mixer 3 to produce a first intermediate frequency.

The first intermediate frequency and the output of the second local oscillator 4 are beat down using a second mixer 5 to become a second intermediate frequency. Next, the BPF 6 eliminates unnecessary out-of-band noise. Waveform equalization is performed to remove interference and optimize the characteristics of the transmission path. The output is sent to the first multiplier 7 and the second
In addition to the multiplier 8, synchronous detection is performed by multiplying the phase of the reference oscillator 9 and its output by a signal with a 7-phase shift through the T phase shifter 1o, and using the first LPF II and the second LPF 12. The unnecessary high-frequency components are removed by the process, each of which is determined based on the so-called 0 phase and 7 phase, so-called mechanical and Q bases, and each is sent to the digital signal processing circuit 1 as a binary digital signal.
6 is input. On the other hand, the output of the first BPFII and the output of the second BPFII
The output of the BPF 12 is added to the third multiplier 18, the output is input to the fourth multiplier 19, and the clock recovery circuit 2
The data transmission frequency reproduced by 1 is multiplied by a clock signal obtained by dividing the frequency by 2. The output of the fourth multiplier 19 is then fed back to the second local oscillator 4 via the loop filter 2o. That is, the third multiplier 18, the fourth multiplier 19.
Detecting the phase difference between the second intermediate frequency, which is the input of the first multiplier 7 and the second multiplier 8, and the output of the reference oscillator 9 using the clock signal regenerated by the loop filter 2o and the clock regeneration circuit 21, controlling the second local oscillator 4,
This constitutes a negative feedback loop that makes the phase difference between the second intermediate frequency and the output of the reference oscillator 9 a certain constant value. The phase difference detection operation is described in detail in the above-mentioned Japanese Patent Laid-Open Publication No. 55-73164, so a description thereof will be omitted here. According to this embodiment, since an oscillator with good frequency stability such as a crystal oscillator is used as the reference oscillator 9, the frequency of the second intermediate frequency becomes a stable value in the negative feedback loop, and the frequency of the first local oscillator 2 becomes a stable value. Even if it drifts due to temperature fluctuations, the frequency of the second intermediate frequency remains constant.

There is no deviation from the center frequency of the BPF 6, and stable characteristics can be obtained.

FIG. 2 is a block diagram showing a second embodiment of the present invention, and this diagram is a block diagram showing a second embodiment of the present invention, and this diagram is an addition of countermeasures when the negative feedback loop in the circuit of FIG. 1 becomes pseudo-locked. Components with the same symbols as 2 and 2 have the same functions, 22 is a bit error rate measuring circuit, 23 is a low frequency signal generating circuit, and 24 is an adding circuit.

In the figure, when the frequency of the second local oscillator 4 is not stable, such as when the power is turned on, in the circuit of FIG. 1, a negative feedback loop is applied at a frequency different from the frequency of the reference oscillator 9. A pseudo-lock condition may occur. In this case, the output of the loop filter 2o outputs a voltage different from the normal value Ov. Let this be the pseudo lock voltage Ve.

In the pseudo-lock state, normal data cannot be demodulated, so a signal with almost all errors is obtained at the reproduced signal output terminal 17.

The code error rate measuring circuit measures this state and sends a signal to the low frequency signal generating circuit 23. The low frequency signal generation circuit 23 receives this and generates a low frequency signal whose amplitude is larger than the pseudo lock voltage Ve. The adder circuit 24 adds the low frequency signal and the output of the loop filter 2o and inputs the result to the second local oscillator 4. This releases the negative feedback loop from the pseudo-lock state,
The lock becomes normal. In a normal lock state, the output of the reproduced signal output terminal has a low bit error rate, so the bit error rate measuring circuit 22 receives this and sends a signal to the low frequency generation circuit 23 to stop generating low frequencies. At this time, the low frequency generation circuit 23 outputs Qv. It is assumed that the second local oscillator 4 oscillates at the same intermediate frequency as the reference oscillator 9 when the input voltage is ov, and operates with positive and negative voltages centered on the control voltage Ov.

According to this embodiment, since the frequency of the local oscillator can be changed by detecting a pseudo lock state, stable demodulation can be obtained.

FIG. 3 is a block diagram showing a third embodiment of the present invention, and this figure also shows a circuit for countermeasures against false locks, in which the false lock state is checked using the output of the loop filter 20. The same reference numerals as in FIG. 2 indicate the same parts, 25 is a reference voltage generator, 26 is a comparator, and 27 is an adder circuit.

In the same figure, loop filter 2 when pseudo-locked
Since the pseudo-lock voltage Ve, which is the output of 0, has a fixed value centered on the normal voltage OM unless the constants of the demodulation circuit are changed, pseudo-lock can be detected. Comparator 26
The input/output characteristics of is configured as shown in Fig. 4, and lVcoM
l<lVe l, O<l VOIJT I
If an appropriate value satisfying I V e I <V (OM l is taken), the output of the adder 27 will always be around Ov, resulting in a normal lock state.

Note that the comparator 26 may have a characteristic of ±V CON as a window comparator and may be used as an input to the low frequency generation circuit 23 shown in FIG.

FIG. 5 is a block diagram illustrating the fourth embodiment of the present invention, and this figure is also an example of countermeasures against false locks, and the same reference numerals as in the above-mentioned embodiments indicate the same parts, and 27 is a voltage limiter. Yes, it has input/output characteristics as shown in Figure 6.

In this case, the output of the voltage limiter 27 is the pseudo lock voltage Ve.
Since it does not reach this point, a pseudo-lock state does not occur. Also,
Similar effects can be obtained even if the characteristics of the second local oscillator 4 in the configuration shown in FIG. 1 are changed to the input/output characteristics shown in FIG. However, Δchie is the output frequency deviation when the input of the second local oscillator is shifted by the pseudo lock voltage Ve.

FIG. 8 is a block diagram showing a fifth embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.

28 is an Aac (auto gain control) circuit. In the same figure, the envelope of the output of BPF6 is A
By keeping it constant with the GC circuit 28, the first multiplier 7 and the second
The operations of the multiplier 8, the third multiplier 18, and the fourth multiplier 19 are free from saturation and can be used with good linearity.

Further, according to this embodiment, the loop gain of the negative feedback loop can be made constant, and stable operation can be performed.

〔Effect of the invention〕

As explained above, according to the present invention, the frequency of the intermediate frequency of the heterodyne receiver can be stabilized, so that there is no excess or deficiency of sidebands caused by the fixed bandpass filter for passing the intermediate frequency, and the carrier wave is It is possible to perform stable demodulation operation without phase shift with respect to frequency changes of the T phase shifter, and it is possible to provide an MSK demodulation circuit with excellent functions by eliminating the drawbacks of the above-mentioned prior art.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, and FIG. 4 is an explanatory diagram of FIG. 3, FIG. 5 is a block diagram showing a fourth embodiment of the present invention, FIG. 6 is an explanatory diagram of FIG. 5, and FIG. 7 is an explanatory diagram of FIG. FIG. 8 is a block diagram showing a fifth embodiment of the present invention. 2... First local oscillator, 3... First mixer, 4
...Second local oscillator, 5...Second mixer, 6...
-Band pass filter, 7...first multiplier, 8...
・Second multiplier, 9...Reference oscillator, 10...π/
2 phase shifter. DESCRIPTION OF SYMBOLS 11... First low-pass filter, 12-mount second low-pass filter, 13... First determination circuit, 14...
Second determination circuit, 15... Inverting circuit, 16... Digital signal processing circuit, 18... Third multiplier, 19...
...Fourth multiplier, 20...Loop filter, 21.
...Tarotsuk playback circuit.

Claims (1)

[Claims] 1. In an MSK demodulation circuit for a heterodyne receiver consisting of a mixer and a local oscillator, a reference oscillator corresponding to an intermediate frequency, a π/2 phase shifter, first and second phase detectors, a second 1
, a second multiplier, and a loop filter, which applies the reference oscillator output to the first phase detector and the π/
2 to the second phase detector via a phase shifter, the first and second phase detector outputs are added to the first multiplier, and the first
The output of the multiplier and a signal divided by two of the transmission frequency timing clock are applied to the second multiplier, and the output of the second multiplier is applied to the local oscillator via the loop filter. MSK demodulation circuit. 2. In the MSK demodulation circuit according to claim 1, a code error rate measuring circuit, an oscillator, and an adder are provided, the code error rate measuring circuit detects a pseudo lock and controls the oscillator, and the oscillator An MSK demodulation circuit characterized in that the output and the output of the loop filter are applied to the adder, and the adder output is applied to the local oscillator. 3. In the MSK demodulation circuit according to claim 1, a reference voltage generator, a comparator, and an adder are provided, and the voltage of the loop filter is checked using the reference voltage generator and the comparator to obtain a pseudo lock. MSK demodulation circuit, characterized in that it is configured to detect the comparator output and the output of the loop filter to the adder, and add the adder output to the local oscillator. 4. In the MSK demodulation circuit according to claim 1, a voltage limiter is provided, the output of the loop filter is input to the voltage limiter, and the output of the voltage limiter is applied to the local oscillator. An MSK demodulation circuit characterized by comprising: 5. The MSK demodulation circuit according to claim 1, characterized in that the output frequency range of the local oscillator is limited. 6. The MSK demodulation circuit according to claim 1, wherein an automatic voltage gain controller is provided, and input signal levels of the first and second multipliers are constant inputs.