JPH0723037A - Clock synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent the deterioration of an equalization characteristic caused by clock step-out in a demodulating equipment provided with a decision feedback type equalizer. CONSTITUTION:In a pre-stage of a phase comparator 5, an automatic gain control amplifier 4 is provided. Therefore, deterioration of a clock component level in an output of a band pass filter 2 at the time of selective fading is corrected, and it becomes the same level as that of a stationary time. Also, at the stationary time, deterioration of a signal caused by an increase of the clock component level is prevented, and at the time of selective fading, step-out caused by deterioration of the clock component level is prevented. As a result, the equalizing capacity of a decision feedback type equalizer can be displayed enough.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit, and more particularly to a clock synchronizing circuit used in a digital radio system and used in a demodulator having a decision feedback equalizer.

[0002]

2. Description of the Related Art A block diagram of a demodulation system using a feedback decision type equalizer is shown in FIG.

The illustrated demodulator is a combination of a decision feedback equalizer and the output of a demodulator generally used in a digital radio communication device.

The structure of the demodulator used in the digital radio communication device is known (for example, Digital Micro Communication Page 111-114 Moriji Kuwahara, Planning Center Co., Ltd.).

The intermediate frequency (I
The modulated wave in the (F) band is branched into two by the distributor 10 and the multiplier (M
IX) 11 and 12. The MIX 11 multiplies the regenerated carrier wave from the regenerated carrier wave generator 13 and the above-mentioned modulated wave to generate a first multiplication signal. Playback carrier is π /
The 2-shifter 14 converts the reproduced carrier wave into a shifted carrier wave having a phase difference of π / 2, and gives it to the MIX 12. MI
At X12, the above modulated wave and the shifted carrier wave are multiplied to generate a second multiplication signal.

The first and second multiplication signals are respectively passed through the low-pass filters (low-pass filters) 15 and 16 to the amplifier 1
7 and 18. Then, here, it is amplified to a prescribed amplitude level and becomes first and second amplified signals (demodulated baseband signals). The first and second demodulated baseband signals are converted into analog-digital converter 19 respectively.
And 20 are sample-quantized into the first and second digital signals. The first and second digital signals are applied to a decision feedback equalizer 21 of the all-digital processing type, where intersymbol interference is removed and output as first and second data (DATAPout, DATAQout). ).

Here, the sampling timing in the analog-digital converters 19 and 20 will be outlined. The first and second demodulated baseband signals are provided to the clock synchronization circuit 22, and the clock synchronization circuit 22 receives the first and second demodulation baseband signals.
And sampling timing is extracted from the second demodulated baseband signal.

The operation of the clock synchronization circuit 22 will be described with reference to FIG. PIN and QIN are provided with the first and second demodulated baseband signals, respectively. Clock components are extracted from the first and second demodulated baseband signals by the non-linear circuits 1 and 1'and the bandpass filter 2 having the sampling timing period (clock frequency) fc as the center frequency. This clock component is amplified by the amplifier 3 and then compared with the oscillation frequency fvco of the voltage controlled oscillator 6 by the phase comparator 5. And
The phase comparator 5 outputs a comparison result voltage as a comparison result.
As a result, the voltage controlled oscillator 6 controls so that the oscillation frequency becomes fvco = fc.

From the voltage controlled oscillator 6, the oscillation frequency fvc
The o clock signal is applied to the analog-digital converters 19 and 20 as sampling timing via the terminals CLKP and CLKQ. As described above, since the oscillation frequency fvco is controlled to fvco = fc, analog-digital conversion (demodulation) is performed at the timing synchronized with the sampling timing at the time of modulation.

The operation of extracting the clock frequency component fc from the demodulated baseband signal will be described with reference to FIG.

At points a and b shown in FIG. 1, only the ½ component of the clock frequency is included as shown in FIG. 4 (a). A clock frequency (fc) component is generated as shown in (b). Then, the clock frequency component is passed through the bandpass filter 2 having the center frequency of fc, and
Only the clock frequency fc can be extracted as shown in (c). The configuration of the decision feedback equalizer is described in, for example, Japanese Patent Application Laid-Open No. 4-181802, so its explanation is omitted here.

FIG. 6 shows the equalization characteristic (signature curve) of the decision feedback equalizer. In FIG. 6, the vertical axis represents ρ = amplitude of reflected wave / amplitude of main wave, and when ρ = 1, the notch becomes the deepest. Further, the horizontal axis represents Δf, which is the shift of the notch position (frequency) from the center of the band. In FIG. 6, the shaded area is the non-equalizable area, and the smaller the area, the higher the performance of the equalizer.

[0013]

By the way, in the above-described sampling timing generation, that is, in the clock synchronization, the fading notch frequency is ± f from the carrier frequency f _0.
As the depth of the notch becomes deeper at a position separated by c / 2 (Hz), the frequency component level of 1/2 of the clock signal in the modulated wave decreases. As a result, the level of the clock component extracted from the baseband signal decreases even though it is in the equalizable region of the decision feedback equalizer. Therefore, the phase comparator cannot perform the comparison and the synchronization loss occurs.

In order to prevent such a problem, the amplification degree of the amplifier in the preceding stage of the phase comparator is increased to cause the loss of synchronization due to the decrease of the clock component level in the equalizable region of the decision feedback equalizer. If this is not done, there is a problem in that signal degradation occurs due to interference with other circuits in the demodulator as a result of an excessive clock component being output from the amplifier during steady state (no fading) or shallow fading.

An object of the present invention is to provide a clock synchronization circuit which does not cause signal deterioration and does not cause loss of synchronization.

[0016]

According to the present invention, a demodulator having analog-digital conversion means for receiving a baseband signal and converting the baseband signal into a digital signal, and the digital signal are equalized and equalized. Used in a demodulator having a decision feedback equalizer for generating a signal, extracting means for extracting a clock component from the baseband signal, and automatic control for automatically controlling the gain of the clock component and outputting an amplified clock component. A clock synchronization circuit is obtained which has gain control amplification means and generation means for generating a sampling timing clock of the analog-digital conversion means based on an amplified clock component.

[0017]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated clock synchronization circuit 23 is partially different in configuration from the clock synchronization circuit shown in FIG. 2, and the same components as those of the clock synchronization circuit shown in FIG. 2 are the same. Give a reference number. Further, the clock synchronization circuit shown in FIG. 1 is used in the demodulation device shown in FIG. 3 similarly to the clock synchronization circuit shown in FIG.

In the illustrated clock synchronization circuit 23, an automatic gain control amplifier 4 is provided in front of the phase comparator 5.

As described above, the clock components are extracted from the first and second demodulated baseband signals by the non-linear circuits 1 and 1'and the band-pass filter 2 having the sampling timing period (clock frequency) fc as the center frequency. It This clock component is amplified by the automatic gain control amplifier 4. That is, the phase comparator 5 amplifies the signal to a prescribed level required for phase comparison. Then, this clock component is given to the phase comparator 5. As a result, as described above, the clock signal synchronized with the clock frequency fc is obtained from the voltage controlled oscillator 6 and is given to the analog-digital converters 19 and 20 as a sampling timing signal.

At the time of selective fading, the level of the clock component output from the bandpass filter 2 differs depending on the notch frequency and the notch depth, but the automatic gain control amplifier 4 determines from the steady state to the decision feedback equalizer. The gain is controlled so that the specified output level is maintained up to the notch depth at which the equalization becomes impossible. The output level here is defined as a level at which phase comparison can be performed normally in the phase comparator and signal deterioration due to interference with other circuits does not occur. Therefore, in the steady state, the level of the clock component of the bandpass filter output is higher than that in the selective fading, but the automatic gain control amplifier suppresses the level to a specified level, so that no interference with other circuits is caused.

Here, as shown in FIG. 5A, the notch frequency of the selective fading is (carrier frequency-fc / fc
2) The case of occurrence at Hz will be described.

In the spectrum of the demodulated baseband signal at this time, the frequency component near fc / 2 is lowered as shown in FIG. 5 (b). Therefore, the nonlinear circuit output is shown in FIG.
As shown in (c), the component of the clock frequency (fc) is also reduced, which also reduces the clock component at the output of the bandpass filter shown in FIG. 5 (d). When the band-pass filter output is given to the automatic gain control amplifier 4, the clock component is input to the phase comparator at the same level as the clock component in the steady state (no fading) as shown by the broken line in FIG. 5 (e). become.

If the automatic gain control amplifier does not lose the clock synchronization at the notch depth at which the decision feedback equalizer cannot equalize, the equalization capability of the decision feedback equalizer is affected by the clock synchronization loss. Will be obtained without receiving. FIG. 7 shows the equalization / equalization characteristics at this time. In FIG. 7, equalization deterioration at both ends of the band ± fc / 2 (Hz) is eliminated, and the non-equalizable region (the hatched portion in FIG. 7) is smaller than the non-equalizable region shown in FIG. You can see that it has become.

[0025]

As described above, according to the present invention, since the automatic gain control circuit is provided in the preceding stage of the phase comparator, the clock frequency component extracted from the demodulated baseband signal at the required level for phase comparison regardless of the presence or absence of fading. Can be input to the phase comparator, and as a result, the signal deterioration during steady state (without fading) can be prevented, and the equalization capability of the decision feedback equalizer during selective fading is sufficient without causing characteristic deterioration due to clock synchronization loss. There is an effect that it can be demonstrated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock synchronization circuit according to the present invention.

FIG. 2 is a block diagram showing a conventional clock synchronization circuit.

FIG. 3 is a block diagram showing a demodulation device including a decision feedback equalizer.

FIG. 4 is a diagram for explaining a clock extraction operation in the clock synchronization circuit shown in FIG.

5 is a diagram for explaining a clock extraction operation in the clock synchronization circuit shown in FIG.

6 is a diagram showing equalization characteristics of a decision feedback equalizer when the clock synchronization circuit shown in FIG. 2 is used.

7 is a diagram showing equalization characteristics of a decision feedback equalizer when the clock synchronization circuit shown in FIG. 1 is used.

[Explanation of symbols]

 1,1 'Non-linear circuit 2 Band pass filter 3 Amplifier 4 Automatic gain control amplifier 5 Phase comparator (COMP) 6 Voltage controlled oscillator (VCO) 10 Distributor (hybrid) 11, 12 Multiplier (MIX) 13 Regenerated carrier oscillator 14 π / 2 shifter 15, 16 low-pass filter 17, 18 amplifier 19, 20 analog-digital converter (A / D) 21 decision feedback type equalizer 22, 23 clock synchronization circuit

Claims (2)

[Claims] 1. A demodulator having an analog-digital conversion means for receiving a baseband signal and converting the baseband signal into a digital signal, and a decision feedback equalizer for equalizing the digital signal to generate an equalized signal. And a extracting unit for extracting a clock component from the baseband signal, an automatic gain control amplifying unit for automatically controlling a gain of the clock component and outputting an amplified clock component, and an amplifying clock component. Based on the analog-
A clock synchronization circuit, comprising: a generation means for generating a sampling timing clock of the digital conversion means. 2. The clock synchronizing circuit according to claim 1, wherein the generating means compares a voltage controlled oscillator with an output from the voltage controlled oscillator and the amplified clock component and responds to the phase difference. A phase comparator for giving a voltage signal to the voltage controlled oscillator, and the output oscillation frequency from the voltage controlled oscillator is synchronously controlled to the amplified clock component frequency by the voltage signal to output the output from the voltage controlled oscillator. A clock synchronization circuit characterized by being used as a sampling timing signal.