JP3315723B2 - Data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulator used on the receiving side of a communication system employing a PSK modulation method, and more particularly to a data demodulator having a function of judging the suitability of demodulated data.

[0002]

2. Description of the Related Art A PSK modulator is constructed, for example, as shown in FIG. 3, the data generator 31 outputs the signals S ₁ shown in FIG. 3, for example as a serving modulated signal data (b). Signal generator 32 outputs a signal S ₂ shown in FIG example as a signal of a predetermined modulation frequency 3 (b). As a result, a signal S shown in FIG. 3B, that is, a PSK-modulated signal S is obtained at the output of the multiplier 33 that multiplies both signals.

[0003] The conventional data demodulator for demodulating the signals S ₁ from the received input PSK signal S, for example, FIG. 4
It is configured as shown in FIG.

In FIG. 4, a PSK-modulated signal S
Is multiplied by the (first) multiplier 1 with the output I of the (first) signal generator 3, and the multiplication result signal A is filtered by the (first) low-pass filter 2. (C), is output outside the figure as demodulated data, and is also provided to the control circuit 7.

[0005] The PSK-modulated signal S is (second
) Is multiplied by the output Q of the (second) signal generator 6. The multiplication result signal B is filtered (D) by the (second) low-pass filter 5 (D), and is supplied to the control circuit 7.

Here, the signal generator 3 is controlled by a control circuit 7 so as to generate a signal I (first timing) substantially equal to and in phase with the modulation frequency of the signal S. The signal generator 6 is controlled by the control circuit 7 so as to generate a signal Q having the same frequency as the signal I and a phase different by 90 ° (second timing).

The low-pass filter 2 which receives the output A of the multiplier 1 as an input has a frequency band lower than the output frequency of the signal generator 3 and a frequency lower than the output frequency of the signal generator 3.
The filtering band of the low-pass filter 5 which receives the output B of
The frequency band is lower than the frequency sufficiently lower than the output frequency of the signal generator 6.

First, in a synchronous state in which the output frequency and the phase of both signal generators are controlled to match the signal S,
The operation is as shown in FIG. FIG. 5A is an operation time chart of the series of the multiplier 1, and FIG. 5B is an operation time chart of the series of the multiplier 4.

In FIG. 5A, since the signal I is synchronized with the signal S, the output A of the multiplier 1 has a signal waveform substantially equal to the transmission data (S _{1 in} FIG. 3B). The output C of the low-pass filter 2 for filtering this signal becomes a signal having substantially the same shape as the output A, and correct demodulated data can be obtained.

In FIG. 5B, since the signal Q has the same frequency as the signal I and a phase difference of 90 °, the output B of the multiplier 4 is a signal having a higher frequency than the signal Q. Accordingly, since the signal B is almost filtered by the low-pass filter 5, the filtered output D is a signal of substantially "0" level.

As described above, when the signal S and the output signals of the two signal generators are synchronized, the signal C indicates correct demodulated data, and the signal D becomes substantially "0" level.

Next, when the signal S and the output signals of both signal generators are not synchronized, for example, when the frequency of the signal S is slightly higher than the signals I and Q, as shown in FIG. Operation.

That is, the output signal A of the multiplier 1 is a signal which has been subjected to pulse width modulation such that the pulse width is gradually narrowed.
Although the level is “1”, the level gradually decreases from this point to “0”, and further decreases to “−1” level.

The output signal B of the multiplier 4 is a signal which has been subjected to pulse width modulation such that the pulse width is gradually narrowed and gradually widened.
Is approximately "0" level at first, but gradually decreases from this level to the maximum "-1" level, and then gradually increases to change to "0" level again.

In short, the frequency of the signal S is
When the output frequency is shifted from the output frequency of the signal generator 6, and when the phase of the signal S is shifted from the output phase of the signal generator 3 even if the frequencies match, the signal D is in a non-zero state.

The control circuit 7 controls the frequency and phase of the signal generator 3 based on the signals C and D,
Control is performed so that the state where the signal D is substantially at the “0” level and the signal C indicates correctly demodulated data (synchronous state) is continued.

[0017]

As described above, the conventional data demodulator is configured to perform only the data demodulation operation, and outputs a signal indicating the suitability of the obtained demodulated data. Absent. Therefore, conventionally, the data processing system at the next stage uses the parity information included in the data to check whether or not the obtained demodulated data is correct.

[0018] However, when the generated data error exceeds the range in which the parity check can be performed, as in the case of a transmission line with a low CN ratio, there is a problem that the possibility of erroneous determination in the appropriateness determination by the parity check increases.

In order to solve this problem, the received signal strength is also measured, and if the signal strength is weak and errors are likely to occur, the data is not demodulated. There is a problem that data demodulation cannot be performed even when demodulation can be performed.

It is an object of the present invention to provide a data demodulator capable of outputting a signal indicating whether the demodulated data is appropriate or not together with the demodulated data.

[0021]

In order to achieve the above object, a data demodulator according to the present invention has the following configuration. That is, the data demodulator according to the present invention includes a first signal generator controlled to generate a first timing signal substantially equal to and in phase with the modulation frequency of the received and input PSK signal;
The same frequency as the first timing signal and the phase 90
A second signal generator controlled to generate a different second timing signal; a first multiplier for multiplying a received and input PSK signal by the first timing signal; A first low-pass filter for filtering the output of the multiplier and outputting demodulated data; and a second multiplication for multiplying the received and input PSK signal by the second timing signal. A second low-pass filter for filtering the output of the second multiplier; the first and second filters
And a control circuit for controlling the first and second signal generators to generate respective required timing signals in response to an output of the low-pass filter of the first and second data demodulators. A calculator for receiving an output of the low-pass filter of No. 2 and calculating a demodulation degree index indicating whether the demodulated data is appropriate or not.

[0022]

Next, the operation of the data demodulator of the present invention configured as described above will be described. According to the present invention, there is provided an arithmetic unit for calculating a demodulation degree index indicating whether the demodulated data is appropriate based on the outputs of the first and second low-pass filters, and the demodulated data is provided together with the demodulated data in a data processing system at the next stage. And outputs a demodulation index indicating the suitability of.

Therefore, the data processing system at the next stage can judge whether the input demodulated data is appropriate or not based on the demodulation index input together with the demodulated data. I can do it.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a data demodulator according to one embodiment of the present invention. This data demodulator is obtained by adding an arithmetic unit 8 to the conventional circuit (FIG. 4). Hereinafter, a portion according to the present invention will be described.

As described above, the signal C is demodulated data. When the signal C is out of synchronization, the level (absolute value) of the signal C becomes smaller than the true value (FIG. 6). The signal D is a signal of "0" level when synchronized (see FIG. 5).
(B)), when the signal deviates from the synchronization, if the level is "0", a deviated portion occurs (FIG. 6).

Then, the arithmetic unit 8 calculates the demodulation degree index F defined by the following equation 1 based on the signals C and D.

[0027]

F = 1 / (1+ | D | / | C |)

The significance of the demodulation index F will be described with reference to FIG. 2, from time T ₄ to the same T ₅ shows a synchronous state, the period in the signal D is almost "0" level. Therefore, F = 1.

On the other hand, although from time T ₅ to the same T ₆ shows an asynchronous state, the signal C is the level in this period is reduced from the true value ( "1"), and the signal D is "0" level Disappears. Therefore, F <1.

In short, if F = 1, it indicates that the signal C is correct demodulated data, and if F <1, it indicates that the signal C is incorrect demodulated data. In the data processing system at the next stage, only the signal C with F = 1 needs to be fetched, and the processing efficiency in the data processing system can be improved.

[0031]

As described above, according to the data demodulator of the present invention, the operation for calculating the demodulation degree index indicating the propriety of the demodulated data based on the outputs of the first and second low-pass filters. A demodulator is provided to output a demodulation index indicating the propriety of the demodulated data together with the demodulated data to the next data processing system. Judgment can be made based on the demodulation index input together with the data, and only the correctly demodulated data needs to be used, which has the effect of improving the processing efficiency.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a data demodulator according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of a computing unit according to the present invention.

3A and 3B are explanatory diagrams of a PSK signal. FIG. 3A is a configuration block diagram of a PSK modulator, and FIG. 3B is a signal waveform diagram of each unit.

FIG. 4 is a configuration block diagram of a conventional data demodulator.

5A and 5B are explanatory diagrams of an operation in a synchronized state, wherein FIG. 5A is an operation time chart of the multiplier 1 side, and FIG. 5B is an operation time chart of the multiplier 4 side.

FIG. 6 is an explanatory diagram of an operation in an asynchronous state.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Low-pass filter 3 Signal generator 4 Multiplier 5 Low-pass filter 6 Signal generator 7 Control circuit 8 Arithmetic unit

Claims (1)

(57) [Claims] A first signal generator which is controlled to generate a first timing signal substantially equal to and in phase with a modulation frequency of a PSK signal received and input; and a same frequency as the first timing signal. A second signal generator controlled so as to generate a second timing signal having a phase difference of 90 °; a first multiplier for multiplying a received and input PSK signal by the first timing signal; The first;
A first low-pass filter for filtering the output of the multiplier and outputting demodulated data; and a second multiplication for multiplying the received and input PSK signal by the second timing signal. A second filter for filtering an output of the second multiplier.
And a control for receiving the outputs of the first and second low-pass filters and controlling the first and second signal generators to generate required timing signals, respectively. A data demodulator comprising: a first circuit;
And a computing unit that receives an output of the second low-pass filter and calculates a demodulation index indicating whether the demodulated data is appropriate or not.