JPH0621986A - Data demodulator - Google Patents

Abstract

PURPOSE:To provide the data demodulator equipped with a function judging the right or wrong of demodulation data. CONSTITUTION:The output C of a low-pass filter 2 is demodulation data. When the synchronizing stepout is occured, the level (absolute value) of the signal C becomes lower than the real value. The output D of a low-pass filter 5 is a '0' level signal when it is being synchronized, but in the case of the synchronizing stepout, it is a signal generating a part beyond the level '0'. An arithmetic unit 8 computes a demodulation index E defined by F=1/(1+¦D¦/¦C¦) based on signals C and D. If F=1, the signal C is proved to be the correct demodulation data. If F<1, the signal C is proved to be the wrong demodulation data. The data processing system of the next stage accepting this simply takes in the only signal C where F=1, and the processing efficiency of the data processing system can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulator used on the receiving side of a communication system adopting a PSK modulation method, and more particularly to a data demodulator having a function of judging whether demodulated data is appropriate.

[0002]

2. Description of the Related Art A PSK modulator is constructed, for example, as shown in FIG. In FIG. 3, the data generator 31 outputs, for example, the signal S ₁ shown in FIG. 3B as the data to be modulated. The signal generator 32 outputs, for example, a signal S ₂ shown in FIG. 3B as a signal having a predetermined modulation frequency. As a result, at the output of the multiplier 33 that multiplies both signals, the signal S shown in FIG. 3B, that is, the PSK-modulated signal S is obtained.

A conventional data demodulator for demodulating the signal S ₁ from the PSK signal S received and input is shown in FIG.
It is configured as shown in.

In FIG. 4, the PSK-modulated signal S
Is multiplied by the output I of the (first) signal generator 3 in the (first) multiplier 1, and the multiplication result signal A is filtered by the (first) low-pass filter 2. (C), the demodulated data is output to the outside of the drawing, and is also given to the control circuit 7.

The PSK-modulated signal S is (second
In the multiplier 4, the output Q of the (second) signal generator 6 is multiplied. The multiplication result signal B is filtered by the (second) low-pass filter 5 (D) and given to the control circuit 7.

Here, the signal generator 3 is controlled by the control circuit 7 so as to generate the signal I which is substantially equal to and in phase with the modulation frequency of the signal S (first timing). Further, the signal generator 6 is controlled by the control circuit 7 so as to generate a signal Q having the same frequency as the signal I but having a phase difference of 90 ° (second timing).

The filtering band of the low-pass filter 2 to which the output A of the multiplier 1 is input is a band sufficiently lower than the output frequency of the signal generator 3, and the multiplier 4
The filtering band of the low-pass filter 5 having the output B of
It is a band below a frequency sufficiently lower than the output frequency of the signal generator 6.

First, in the synchronous state in which the output frequency and phase of both signal generators are controlled so as to match the signal S,
The operation is as shown in FIG. FIG. 5A is an operation time chart of the series of the multiplier 1, and FIG. 5B is an operation time chart of the series of the multiplier 4.

In FIG. 5A, since the signal I is synchronized with the signal S, the output A of the multiplier 1 has a signal waveform almost equal to the transmission data (S _{1 in} FIG. 3B). The output C of the low-pass filter 2 that filters this becomes a signal having substantially the same shape as the output A, and correct demodulated data can be obtained.

In FIG. 5B, since the signal Q has the same frequency as the signal I and a phase difference of 90 °, the output B of the multiplier 4 has a higher frequency than the signal Q. Therefore, since the signal B is almost filtered by the low pass filter 5, the filtered output D becomes a signal of almost "0" level.

As described above, when the signal S and the output signals of both signal generators are synchronized, the signal C shows correct demodulated data, and the signal D becomes almost "0" level.

Next, when the signal S and the output signals of both signal generators are not synchronized, for example, when the frequency of the signal S becomes slightly higher than the signals I and Q, as shown in FIG. It will be a behavior.

That is, since the output signal A of the multiplier 1 is a signal which has been subjected to pulse width modulation such that the pulse width is gradually narrowed, the signal C obtained by filtering this is almost "+" at the beginning.
The level is "1", but gradually decreases from here to 0, and further decreases to "-1" level.

Further, the output signal B of the multiplier 4 is a signal which has been subjected to pulse width modulation in which the pulse width is gradually narrowed and gradually widened.
Is approximately "0" level at first, but gradually decreases from here to the maximum "-1" level, then gradually increases and changes to "0" level again.

In short, the frequency of the signal S is the signal generator 3
When the output frequency of the signal S is deviated from that of the signal generator 6, or when the phase of the signal S deviates from the output phase of the signal generator 3 even if the frequencies match, the signal D is not 0.

Therefore, the control circuit 7 controls the frequency and phase of the signal generators 3 and 6 based on the signals C and D,
The control is performed so that the state where the signal D is substantially "0" level and the signal C indicates the correctly demodulated data (synchronized state) continues.

[0017]

As described above, the conventional data demodulator is configured to perform only the data demodulation operation and outputs the signal indicating the suitability of the obtained demodulated data. Absent. Therefore, conventionally, the next-stage data processing system uses the parity information included in the data to check whether or not the obtained demodulated data is correct.

However, when the data error that occurs exceeds the range in which the parity check is possible, such as in the case of a transmission line with a low CN ratio, there is a problem in that the possibility of making an incorrect decision in the propriety judgment by the parity check increases.

In order to solve this problem, the received signal strength is also measured, and there is a method in which the data is not demodulated when the signal strength is weak and an error is likely to occur. However, there is a problem that the data cannot be demodulated even when can be demodulated.

An object of the present invention is to provide a data demodulator capable of outputting demodulated data and a signal indicating the suitability of the demodulated data.

[0021]

In order to achieve the above object, the data demodulator of the present invention has the following configuration. That is, the data demodulator of the present invention includes a first signal generator which is controlled so as to generate a first timing signal which is substantially equal to and in phase with the modulation frequency of the PSK signal received and input;
The phase is 90 at the same frequency as the first timing signal.
A second signal generator controlled to generate different second timing signals; a first multiplier for multiplying the received and inputted PSK signal by the first timing signal; and the first A first low-pass filter that filters the output of the multiplier and outputs demodulated data; a second multiplication that multiplies the PSK signal received and input by the second timing signal. A second low-pass filter for filtering the output of the second multiplier; and the first and second
A control circuit for controlling the first and second signal generators to generate respective required timing signals in response to the output of the low-pass filter, and a data demodulator; An arithmetic unit for receiving the output of the low-pass filter 2 and calculating a demodulation index indicating the suitability of the demodulated data.

[0022]

Next, the operation of the data demodulator of the present invention constructed as above will be described. According to the present invention, an arithmetic unit for calculating a demodulation index indicating the suitability of demodulated data based on the outputs of the first and second low-pass filters is provided, and the demodulated data together with the demodulated data are provided to the data processing system of the next stage. The demodulation index indicating the suitability of is output.

Therefore, in the data processing system of the next stage, the adequacy of the input demodulated data can be judged by the demodulation index which is input together with the demodulated data, and it is sufficient to use only the correctly demodulated data, which improves the processing efficiency. Can be achieved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a data demodulator according to an embodiment of the present invention. In this data demodulator, a calculator 8 is added to the conventional circuit (FIG. 4). Hereinafter, a part according to the present invention will be described.

As described above, the signal C is demodulated data, and when out of synchronization, the level (absolute value) of the signal C becomes smaller than the true value (FIG. 6). Further, the signal D is a signal of “0” level when synchronized (see FIG. 5).
(B)), when it is out of synchronization, if it is a "0" level, a part is removed (Fig. 6).

Therefore, the calculator 8 calculates the demodulation index F defined by the following equation 1 based on the signals C and D.

[0027]

## EQU1 ## F = 1 / (1+ | D | / | C |)

The significance of the demodulation index F will be described with reference to FIG. In FIG. 2, the synchronization state is shown from time T ₄ to time T _5, but the signal D within this period is almost "0" level. Therefore, F = 1.

On the other hand, from time T ₅ to time T ₆ the asynchronous state is shown. In this period, the level of the signal C drops from the true value ("1"), and the signal D is at "0" level. Disappear. Therefore, F <1.

In short, if F = 1, it means that the signal C is correct demodulated data, and if F <1, it means that the signal C is incorrect demodulated data. Further, in the data processing system at the next stage, only the signal C with F = 1 needs to be fetched, and the processing efficiency in the data processing system can be improved.

[0031]

As described above, according to the data demodulator of the present invention, the calculation for calculating the demodulation index indicating the suitability of demodulated data based on the outputs of the first and second low pass filters. Since the demodulation index indicating the suitability of the demodulated data is output to the next-stage data processing system together with the demodulated data, the next-stage data processing system determines whether the input demodulated data is suitable or not. It is possible to judge by the demodulation index input together with the data, and it is sufficient to use only the correctly demodulated data, which has the effect of improving the processing efficiency.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a data demodulator according to an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the arithmetic unit of the present invention.

3A and 3B are explanatory diagrams of a PSK signal, in which FIG. 3A is a block diagram illustrating the configuration of a PSK modulator, and FIG. 3B is a signal waveform diagram of each part.

FIG. 4 is a configuration block diagram of a conventional data demodulator.

5A and 5B are operation explanatory diagrams in a synchronized state, in which FIG. 5A is an operation time chart on the multiplier 1 side, and FIG. 5B is an operation time chart on the multiplier 4 side.

FIG. 6 is an operation explanatory diagram in an asynchronous state.

[Explanation of symbols] 1 multiplier 2 low-pass filter 3 signal generator 4 multiplier 5 low-pass filter 6 signal generator 7 control circuit 8 arithmetic unit

Claims (1)

[Claims] 1. A first signal generator controlled to generate a first timing signal substantially equal to and in phase with the modulation frequency of the received and input PSK signal; and the same frequency as the first timing signal. A second signal generator which is controlled to generate a second timing signal whose phase is different by 90 °; and a first multiplier which multiplies the PSK signal received and input by the first timing signal. The first
A first low-pass filter that filters the output of the multiplier and outputs demodulated data; a second multiplication that multiplies the PSK signal received and input by the second timing signal. A second filter for filtering the output of the second multiplier
A low-pass filter; and control for receiving the outputs of the first and second low-pass filters and controlling the first and second signal generators to generate required timing signals, respectively. A data demodulator comprising: a circuit;
And a calculator that receives the output of the second low-pass filter and calculates a demodulation index indicating the suitability of the demodulated data; a data demodulator.