GB2213663A - Data demodulator carrier phase locking - Google Patents

Abstract

An arrangement in a data demodulator for locking the phase of a locally generated carrier signal to the phase of a received phase-modulated signal comprises multiplier and measuring means (4) for producing two quadrature-phase bi-level channel signals (I) and (Q) and for measuring the durations of the two levels of each channel signal over a given period to determine the predominant level, logic means (5) for producing, from signals received from the means (4) and representing the difference (x, y) in durations of the two levels of each channel signal and the sign of the difference, an error signal (z) representing the carrier phase-error, and phase-adjusting means (6) for adjusting the carrier phase, preferably in dependence only on the sign of the error signal and not its magnitude. <IMAGE>

Description

DESCRIPTION DATA DEMODULATOR CARRIER PHASE LOCKING This invention relates to coherent data demodulators for the demodulation of shift keyed signals which are phase-modulated to represent multi-bit data symbols.

The invention relates more particularly to such coherent data demodulators of a type in which in the demodulation process two quadrature phased channel signals are produced by separately multiplying together an incoming shift keyed signal of a given carrier frequency and each of two quadrature phased versions of a locally generated carrier signal of notionally the same frequency as said carrier frequency, digital data being thereafter detected from either the incoming shift keyed signal or from either one of the two channel signals by determining the occurrence of data transitions.

In order to achieve reliable data detection, both the locally generated carrier signal and a locally generated baud rate clock are required to be continuously adjusted into coherent phase relationship with the incoming shift keyed signal and this adjustment can be accomplished by using digital phase-locked loops (DPLL). A single DPLL can be used for both those adjustments, or they can be carried'out using separate DPLL's in a carrier recovery circuit and a data recovery circuit, respectively.

The article "A survey of Digital Phase-Locked Loops", published in Proceedings of the IEEE, Vol. 69, No. 4, April 1981, gives useful information on the state of the art.

A problem encountered in the implementation of coherent data demodulators of the above type is to be able to make a phase detection, which is used in the adjustment of the phase of the locally generated carrier signal, insensitive to variation of phase due to phase-modulated data superimposed on the carrier signal. This problem was found to occur even when a separate DPLL is used for recovery the phase of the carrier signal from the incoming shift keyed signal.

It is an object of the present invention to provide an improved method of, and/or an arrangement for, locking the phase of a locally generated carrier signal to the phase of an incoming shift keyed signal in a data demodulator of the type set forth above in order to mitigate this problem.

According to the invention a method of phase-locking the carrier signal in a coherent data demodulator of the type set forth above comprises: - separately multiplying together a received shift keyed signal of a given carrier frequency and each of two quadrature phased versions of a locally generated carrier signal of said given frequency to produce two bi-level channel signals; - determining in respect of each channel signal in each period thereof occurring in each successive half cycle of one of the channel signals a first signal representing the difference, if any, in the durations of the two levels of the channel signal in the period and a second signal representing which is the predominant level;; - producing an error signal representing the algebraic sum of said first signals for both channel signals by subtracting the first signal for one channel signal from the first signal for the other channel signal when the second signals for both channel signals represent the same predominant level, or subtracting the first signal for the other channel signal from the first signal for said one channel signal when the second signal for both channel signal represent opposite predominant levels; and - advancing the phase of said locally generated carrier signal when the error signal has a value of one sign and the retarding the phase of said locally generated carrier signal when said error signal has a value of the opposite sign.

By using the second signals for the channel signals to determine which of the first signals becomes the minuend and which becomes the subtrahend for the subtraction process in respect of each of said periods, the production of the error signal is not affected by the variation of phase due to phase-modulated data superimposed on the carrier signal.

Therefore, the data which are present in both the channel signals do not contribute to the value of the error signal.

In carrying out the invention, it is preferable for the rate of change of adjustment of the phase of the locally generated carrier signal to be made independent of the instantaneous magnitude of the error signal and only take account of its sign.

This affords the advantage that sudden large "jumps" in the phase error of the received shift keyed signal due to data phase changes are ignored and only the direction of the error is pertinent.

Also, according to the invention in a coherent data demodulator of the type set forth above, an arrangement for phase-locking a locally generated carrier signal of said given frequency comprises: - input means for receiving a phase-modulated shift keyed signal of said given carrier frequency; - reference signal generator means for producing two quadrature phased versions of said locally generated carrier signal; - multiplier means connected to receive said shift keyed signal and said two locally generated carrier signal versions and operable to multiply separately the shift keyed signal with each said version to produce two bi-level channel signals;; - measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each successive half cycle of one of the channel signals a first signal representing the difference, if any, in the durations of the two levels of the channel signal in the period and a second signal representing which is the predominant level;; - logic means connected to receive both said first signals and both said second signals and operable to produce an error signal representing the algebraic sum of said first signals by subtracting the first signal for one channel signal from the first signal for the other channel signal when the second signals for both channel signals represent the same predominant level, or subtracting the first signal for the other channel signal from the first signal for said one channel signal when the second signals for both channel signals represent opposite levels; and - phase adjusting means connected to receive said error signal and operable to cause the reference signal generator means to advance the phase of said locally generated carrier signal when said error signal has a value of one sign and to retard the phase of said locally generated carrier signal when said error signal has a value of the opposite sign.

The two versions of the locally generated carrier signal can be produced at the outputs of two stages of an m-stage Johnson counter which is fed with drive pulses from an associated drive circuit which is connected to a drive pulse clock source and also to the output of said algebraic summing means to receive as said error signal an enabling signal when said algebraic sum is not zero together with a sign signal which signifies the sign of a non-zero algebriac sum and to which the drive circuit is responsive according to that sign to add or to delete drive pulses as applied by it from the drive pulse clock source to the counter.

The invention also extends to a coherent data demodulator embodying such a phase-locking arrangement.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings of which: Figure 1 shows a block diagram of a coherent data demodulator embodying the present invention; Figures 2 and 3 show explanatory waveform diagrams; and Figure 4 shows an error signal vector diagram.

Referring to the drawings, the coherent data demodulator shown in Figure 1 has an input terminal 1 to which an incoming phase shift keyed signal is applied. For the purposes of the present description it is assumed that this incoming signal is a DQPSK signal, that is a quadrature phase shift keyed signal which has been produced by differential encoding of data bits of a data stream. The encoding employed is suitably in accordance with the CCITT Recommendation V22 which specifies inter alia that for a data stream of 1200 bits per second the data stream to be transmitted shall be divided into symbols S of 2 consecutive bits (dibits). Each symbol shall be encoded as a phase change relative to the phase of the preceding symbol as set forth in the Table 1 below.

TABLE I Symbol(S) values (1200 bits/s) Phase Change 00 +900 01 Go 11 +2700 10 +1800 The incoming DQPSK signal at the input terminal 1 is applied to a receive filter 2 which subjects this incoming signal to equivalent baseband pulse shaping and delay equalization. This receive filter 2 can be a high order active filter of known form. The output signal from the filter 2 is hard limited by a limiter 3 which produces a resultant phase shift keyed signal q(t) which can be approximated by the equation: q(t) = ssq(wct + ;) (1) where ssq signifies a square wave and Oi = 8+n Ng/2, with each value of n being equally likely in the case of random DQPSK, where n = 0, 1, 2, 3.

The resultant signal q(t) is applied to first and second signal inputs (i)1 and (i)2 of a multiplying and measuring arrangement 4 and two reference signals s(t) and c(t) are applied respectively to first and second reference inputs (r)1 and (r)2 of this arrangement 4. These two reference signals are generated by a reference signal generator, as will be described, and can be represented by the equations: s(t) = ssq(wct) (2) c(t) = csq(wct) (3) where ssq and csq signify square wave sine and cosine phased versions, respectively, of a locally generated carrier signal.

The instantaneous resultant signal q(t) from the limiter 3 can have any one of four different phases dependent on the dibit value which it represents at any time. Waveform diagrams (a), (b), (c) and (d) in Figure 2 represent these four possible phases, respectively, and the two reference signals s(t) and c(t) are represented by the waveform diagrams (e) and (f).

Within the arrangement 4, the signal q(t) is multiplied by each of the reference signals s(t) and c(t) to produce respective channel signals (I) and (Q) which, ignoring the double frequency components produced by the multiplications, can be represented by the equations: (I) = ssq (by+6) (4) (Q) = csq (8i+B) (5) where e is an arbitrary carrier phase error.

In Figure 2, waveform diagrams (g), (h), (i) and (j) represent the four possible bi-level forms of the channel signal (I) and waveform diagrams (k), (I), (m) and (n) represent the four possible bi-level forms of the channel signal (Q).

One level of a channel signal corresponds to a positive phase difference of the signal q(t) relative to the reference signal s(t) or c(t), as the case may be, and the other level corresponds to a negative phase difference. These channel signals (I) and (Q) thus contain phase error information and are further processed within the arrangement 4 to produce at outputs (0)1 and (0)2 signals (x), sgn(x) and (y), sgn(y), respectively.

The signals (x) and (y) represent the difference in the durations of the two levels of the relevant channel signal (I) or (Q) during successive predetermined periods and the signals sgn(x) and sgn(y) represent which level is the predominant level.

An incoming DQPSK signal will result in the signal q(t) having a random succession of the four different phases represented by the waveform diagrams (a), (b), (c) and (d) of Figure 2, depending on the dibit values used to modulate the DQPSK signal. The values at any time of the signals (x) and (y) are due not only to the phase (frequency) difference of the signal q(t) relative to the reference signals s(t) and c(t), but also to the quad-phased data in the DQPSK signal. Therefore, it is not feasible to use these (x) and (y) signal values directly as a measure of the instantaneous phase difference between the signal q(t) and the reference signals s(t) and c(t), in order to carry out a phase correction for locking the phase of the reference signal generator from which the reference signals are derived to the phase of the incoming DQPSK signal.

Further processing of these (x) and (y) signal values is carried out by a logic arrangement 5 in accordance with an algorithm as represented in the following Table II to produce a resultant phase error signal (z).

TABLE II (x) (y) sgn(x) sgn(y) (z) 1 1 +1 +1 |x|-|Y| 0 1 -1 +1 0 0 -1 -1 IxI-lyl 1 0 +1 -1 |Y|-|x| In the above table, it is assumed that the values 1 and 0 represent the two channel levels. When level 1 predominates to give a positive error signal the sign signal has the value +1, and when level 0 predominates to give a negative error signal the sign signal has the value -1. Depending on the relative values (+1 or -1) of sgn(x) and sgn (y), the modulus of x if subtracted from the modulus of y, or vice versa. By using this algorithm the resultant error signal (z) is made quadrature insensitive in that it takes no account of the quad-phase data in the received signal.This is illustrated diagrammatically in Figure 4 which shows that for an arbitrary phase error B, the error signal (z) can be produced in respect of any one of four different phase quadrants. The effect of this is that the locally generated carrier signal can be locked relative to the received signal at any one of four different locking points.

The error signal (z) is applied to a digital reference signal generator 6 which produces the reference signals s(t) and c(t) from a locally generated carrier signal.

This reference signal generator 6 comprises a decision circuit 7, a drive circuit 8 which is connected to receive clock pulses M from a drive pulse clock source (not shown), which pulses are applied to a clock input CKM, and an m-stage Johnson Counter 9 which is driven by the circuit 8. The decision circuit 7 is responsive to the signal (z) to provide a first output signal(z * 0) when the value of the signal (z) is not zero, and a second output signal sgn (z) representing the sign (+ or -) of the signal (z) is produced directly from the logic arrangement 5. These first and second output signals are applied to the drive circuit 8.When the signal (z) is zero, neither of these two output signals is produced and the drive circuit 8 drives the counter 9 directly with drive pulses corresponding to the clock pulses M and applied to a drive input DI, so that the phase of the reference signals s(t) and c(t) remains unchanged. When the signal (z) is not zero, the output signal (z * O) is applied to an "enable" input EN and the output signal sgn (z) is applied to an "add/delete" input A/D of the circuit 8. The result is that the drive circuit 8 will add drivepulses to (when sgn (z) = +) or delete drive pulses from (when sgn (z) = -) those applied to the counter 9 to alter the rate of the drive pulses applied to the counter 9 and thereby advance or retard the phase of the reference signals s(t) and c(t).

The control of the phase adjustment of the locally generated carrier signal using only the sign signal sgn(z) ensures that sudden and momentary large phase changes in the received shift keyed signal DQPSK due to data phase changes are ignored. This effect is illustrated in Figures 3(a) and 3(b). The waveform shown in Figure 3(a) represents the phase 0 of the signal DQPSK against time t. Each symbol period T = 1/S, where S is a symbol or dibt and eight symbols S1 to S8 are shown. Assuming that the symbol S1 has the dibit value (1,1) from the preceding dibit coding, then the symbol S2 has the dibit value (0,0) because it is represented by a 900 phase change relative to symbol S1.

Similarly, the symbol S3 has the dibit value (1,0) because it is represented by a 1800 phase change relative to symbol S2, and so on. See Table I given earlier in the specification and the following Table III which shows the differential decoding as can be provided by read-only memory in response to present dibit symbols S and previous dibit symbols S-1.

TABLE III

S 00 01 11 10 GO 01 11 10 00 01 01 01 11 10 S-l 11 10 00 01 11 10 1 11 10 00 01 The waveform shown in Figure 3 (b) represents the carrier frequency c of the received shift keyed signal DQPSK.Because frequency equals rate of change of phase, it can be seen that at each phase change in Figure 3 (b), there is a proportional and momentary change is the carrier frequency fc. However, because no account is taken in the reference signal generator 6 of the magnitude of any phase error but only the sign thereof, the locally generated carrier signal fl, as shown in dotted line, cannot follow these frequency impulses due to the rate of tracking the phase errors being limited by using only the sign of the phase error.

It is mentioned that the invention has a particularly advantageous application in a coherent data demodulator where the carrier frequency is low relative to the data baud rate, so that each dibit symbol is represented by only a few cycles of the carrier signal. This applies for instance where the carrier frequency is only 2400 Hz and is modulated at a symbol rate of 600 bauds.

The sign signals sgn (x) and sgn (y) each contain information as to each phase change in the signal q(t), which information is the baseband data used to modulate the incoming signal DQPSK.

Also, the baud rate of this baseband data is represented by the transitions in the signals sgn (x) and sgn (y). A circuit arrangement represented by the rectangle 10 is connected to receive the signals sgn (x) and sgn (y) and is operable to detect the data transitions in these signals and to provide a resultant data output signal (DS). The circuit arrangement 10 comprises a differential decoder and bit serialiser and is driven by data clock pulses D which are applied to a clock pulse input CKD thereof from a data clock pulse generator 11. The pulse generator 11 includes a baud rate recovery circuit for phase-locking the data clock pulses D with the incoming data symbols.

The multiplying and measuring arrangement 4 and the logic arrangement 5 can be implemented in the manner set forth in Applicants co-pending patent application GB 8729016. The circuit arrangement 10 and the data clock pulse generator 11 can be implemented in the manner set forth in Applicants co-pending patent application GB 8729018.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation or modification thereof which would be apparent to persons skilled in the art, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived thereform.

Claims (7)

CLAIM(S):

1. A method of phase-locking the carrier signal in a coherent data demodulator for demodulating shift keyed signals which are phase-modulated to represent digital data, said method comprising: - separately multiplying together a received shift keyed signal of a given carrier frequency and each of two quadrature phased versions of a locally generated carrier signal of said given frequency to produce two bi-level channel signals; - determining in respect of each channel signal in each period thereof occurring in each successive half cycle of one of the channel signals a first signal representing the difference, if any, in the durations of the two levels of the channel signal in the period and a second signal representing which is the predominant level;; - producing an error signal representing the algebraic sum of said first signals for both channel signals by subtracting the first signal for one channel signal from the first signal for the other channel signal when the second signal for both channel signals represent the same level, or subtracting the first signal for the other channel signal from the first signal for said one channel signal when the second signals for both channel signals represent opposite predominant Levels; and - advancing the phase of said locally generated carrier signal when the error signal has a value of one sign and retarding the phase of said locally generated carrier signal when said error signal has a value of the opposite sign.

2. A method as claimed in Claim 1, characterised in that the rate of change of adjustment of the phase of the locally generated carrier signal is made independent of the instantaneous magnitude of the error signal and only takes account of its sign.

3. In a coherent data demodulator for demodulating shift keyed signals of a given frequency which are phase-modulated to represent digital data, an arrangement for phase-locking a locally generated carrier signal of said given frequency comprises: - input means for receiving a phase-modulated shift keyed signal of said given carrier frequency; - reference signal generator means for producing two quadrature phased versions of said locally generated carrier signal; - multiplier means connected to receive said shift keyed signal and said two locally generated carrier signal versions and operable to multiply separately the shift keyed signal with each said version to produce two bi-level channel signals;; - measuring means connected to receive said two channel signals and operable in respect of each to produce for each period thereof occurring in each successive half cycle of one of the channel signals a first signal representing the difference, if any, in the durations of the two levels of the channel signal in the period and a second signal representing which is the predominent level;; - logic means connected to receive both said first signals and both said second signals and operable to produce an error signal representing the algebraic sum of said first signals by subtracting the first signal for one channel signal from the first signal for the other channel signal when the second signal for both channel signals represent the same predominant level, or subtracting the first signal for the other channel signal from the first signal for said one channel signal when the second signals for both channel signals represent opposite predominant levels; and - phase adjusting means connected to receive said error signal and operable to cause the reference signal generator means to advance the phase of said locally generated carrier signal when said error signal has a value of one sign and to retard the phase of said locally generated carrier signal when said error signal has a value of the opposite sign.

4. A phase-locking arrangement as claimed in Claim 3, characterised in that said two versions of the locally generated carrier signal are produced at the outputs of two stages of an m-stage Johnson counter which is fed with drive pulses from an associated drive circuit which is connected to a drive pulse clock source and also to the output of said algebraic summing means to receive as said error signal an enabling signal when the error signal produced thereby is not zero and a sign signal which signifies the sign of the error signal and to which the drive circuit is responsive according to that sign to add or to delete drive pulses as applied by it from the drive pulse clock source to the counter.

5. A method of phase-locking a locally-generated the carrier signal in a coherent data demodulator, substantially as hereinbefore described.

6. An arrangement for phase-locking a locally generated carrier signal in a coherent data demodulator, substantially as hereinbefore described with reference to the accompanying drawings.

7. A coherent data demodulator embodying a phase-locking arrangement as claimed in any one of Claims 3, 4 or 6.