JPS58701B2 - Sadowisou Fukuchiyousouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator used in a communication system for transmitting digital information, and particularly to a high-order differential phase modulation communication system that performs phase modulation using a double summation-converted code string. The present invention relates to a differential phase demodulator used in demodulating a received signal.

One of the modulation methods for transmitting digital information is the so-called differential phase modulation method, in which information corresponds to the phase difference between two sample points.As a demodulation method corresponding to this, two There is a differential detection method that detects the phase difference between sample points.

Furthermore, as a more complex high-order differential phase modulation method, for example, in the case of second order, a method in which information is made to correspond to the phase difference between two sample points in a time series consisting of a phase difference between two sample points. There is.

This high-order differential phase modulation is used in relay transmission using a repeater that includes a delay detector and does not perform summation conversion.

The delay detection circuits used in these communication systems include a delay circuit that delays the input signal, a phase difference detection circuit that detects the phase difference between the input signal and the output signal of the delay circuit, and a transmission code that determines the transmitted code from the output of the phase difference detection circuit. It consists of an identification circuit.

Further, as the delay circuit, a delay line, a resonator, etc. are used, and if the input signal is A/D converted, a digital memory etc. are also used.

Although this delayed detection method is inferior to the synchronous detection method in terms of bit error rate characteristics against noise, it has an extremely simple circuit configuration, does not require time for synchronization, and is highly efficient when used for burst communication. Because it has characteristics such as being resistant to phase fluctuations, it has a wide range of applications, including communications using unstable lines and simple communication devices.

However, the delayed detection method has a major drawback in that it is susceptible to carrier wave frequency fluctuations or delay circuit delay time fluctuations.

This drawback is particularly noticeable when the carrier frequency is too high compared to the transmitted symbol rate.

For example, consider the case where 9.6 Kb/s data is transmitted by applying 4-phase differential phase modulation to a 400 MHz carrier wave.
The symbol rate is 4.8 KHz, and the delay time of the delay circuit that matches the symbol period is 1/4.8×10 3 seconds.

On the other hand, if the frequency stability of the 400 MHz carrier wave oscillator and the local oscillator of the receiver is ±10-6, the frequency change width of the signal applied to the delay detector is ±400 Hz.

Therefore, the phase difference between the input and output signals of the delay circuit is ±4×102×360°/4.8×103=
Changes by ±30°.

A similar change occurs when the delay time of the delay circuit changes by ±10-6.

In this way, if the phase difference between the input and output of the delay circuit changes greatly with frequency fluctuations, the 0
°, 90°.

Phase changes of 180° and 270° are detected with large deviations, and normal detection cannot be performed.

An object of the present invention is to provide a demodulator that is simple in configuration, resistant to line fluctuations, and requires almost no setup time when transmitting low-rate digital information using a high-frequency carrier wave.

According to the present invention, it is possible to obtain a differential phase demodulator in which the detection characteristics hardly deteriorate even when there are variations in the carrier frequency, variations in the receiving local oscillation frequency, and variations in the delay time of the delay circuit.

This invention will be explained in detail below using the drawings.

FIG. 1 shows a 4-channel system with a carrier frequency of 400 MHz and a transmission rate of 9.6 Kb/s, which is the object of the embodiment of the present invention shown in FIG.
FIG. 2 is a block diagram of a transmitting device that generates high-order differential phase modulation signals of different phases.

Further, FIG. 2 is a waveform diagram for explaining the operation of the transmitting device of FIG. 1 and the device of FIG. 3.

First, high-order differential phase modulation will be explained using the block diagram of FIG. 1 and the waveform diagram of FIG. 2.

Terminal 1 in FIG. 1 is an input terminal for a transmission code an.

Here a. is a code that takes four values of 0, 1, and 2.3,
The subscript n indicates that the time is the value at nT, where T is the code period, and n is an integer.

In this example, the symbol rate is 4°8 baud, so T
is 1/4.8×103 seconds.

Further, when the code a11 having four values is processed by a binary logic circuit, it is represented by two series of binary codes.

This input code a is added to a code obtained by delaying the output code bn of the adder circuit 2 by one code period T in a delay circuit 3 in an adder circuit 2 which performs modulo-4 addition.

MOD, 4 That is, bn is expressed as bn-an■:bo-14
It is a code that takes a value.

Here ■ indicates modulo 4 addition.

An example of this calculation result is shown in FIG. Waveforms 9 and 10 indicate an and bn, respectively.

Next, the code bn is processed by an adder circuit 4 that performs modulo-4 addition.
It is added to code Cn-2 delayed by T.

That is, cn is a code that takes four values expressed as Cn=bn*Cn-2.

The relationship between this Cn and the input code an is Cn=an■bn-
1■Cn-2.

An example of the calculation result is also shown by waveform 11 in FIG.

Next, the code cn is applied to the quadrature phase modulator 6 and the 400MH
Four-phase phase modulation is applied to the output of the carrier wave oscillator 7 of z.

At this time, the modulator output phase θ1 is C11 of 0.1 and 2.3.
0° and 90°, respectively.

It takes values of 180° and 270°.

A 400 MHz transmission signal having such a phase is transmitted via the output terminal 8.

The phase θ1 modulated in this way can be calculated by taking the amount of change in the phase difference between two sample points separated by T in a sequence consisting of the phase difference between two sample points separated by time T. Amount of change in phase difference O', 90°, 180°, 27
It can be seen that 0.1 and 2.3 of the transmission code an correspond to 0°, respectively.

For example, the difference in θ1 between n = 6 and 4 in Figure 2 is 180°, and the difference in θ1 between n = 7 and 5 is 90°, but these 18
A difference of 90° between 0° and 90° corresponds to a=1.

This a. That is 1 is also shown from the fact that the value of n=7 in waveform a is 1.

The operation of the transmitter that generates the signal targeted by the embodiment of the present invention shown in FIG. 3 has been described above.

It is easily understood from the above explanation that general high-order differential phase modulation, which is the object of the present invention, can be performed by the following code conversion.

That is, in the case of N-phase phase modulation, log2N-bit code transmission is possible with a - code, so an, bn, and Cn are all codes that take values of O, 1, 2, ..., N-1, and an
=bn■an-,cn=bn=bn■Cn=1 and Cn
is expressed as 0°1.2 of cn. ..., 0.360°/N corresponding to N-1.

720°/N,..., 360°(N-1)/N.

Here, k and l may be integers of 1 or more.

FIG. 1 corresponds to the case where k and l are 1 and 2, respectively.

It is generally desirable that k and l are not equal, as in this example.

The reason is that if ≠ 7, four different sample values will be used for the demodulation of one code, and the magnitude of the noise included in each sample value is independent, so the effect will be on the power cost. It only works.

On the other hand, if = 7, three different sample values will be used for the demodulation of one code, the center sample value will be used twice, and the influence of noise superimposed on this sample value will be reduced by the voltage sum. The effect is greater than when it is effective due to electricity charges.

Furthermore, increasing the values of k and l not only requires a long delay time, but also increases the number of extra bits at the beginning of which information cannot be transmitted in the case of burst communication, which is not a good idea.

In other words, as shown in Figure 1, = 1. l=2 or ni=2. l
= 1 seems to be the preferred implementation method.

FIG. 3 is a block diagram of an embodiment of the differential phase demodulation device according to the present invention, which has a carrier frequency of 400 MHz, a transmission rate of 9.6 kb/S, and a receiving device for a four-phase phase modulation signal.

The 400 MHz received signal applied to the terminal 19 is converted by the frequency conversion circuit 20 into a 24 KHz intermediate frequency signal.

Here, assuming that the frequency stability of the input carrier wave and the local oscillator included in the frequency conversion circuit is ±1×10 −6 , this intermediate frequency fluctuates within a range of approximately ±400 Hz around 24 KHz.

The intermediate frequency signal is subjected to noise limitation and waveform equalization using a 24 KHz bandpass filter, and then guided to a slicer 22 and a timing signal extraction circuit.The signal converted into a square wave by the slicer 22 is sent to an input terminal of a differential phase demodulator 200. 3
The phase θ2 of this input signal applied to 9 is shown by waveform 13 in FIG.

This value has only a relative meaning since the frequency is different from the value of θ1 of waveform 12 in the figure.

Therefore, the value of 01 is shown as an example of the value of θ2 plus 30°.

The input signal at this terminal 39 is applied to a differentiating circuit 26 and a 640-bit shift register 24.

This shift register 24 sequentially shifts the input signal according to clock pulses from a 3.072 MHz clock signal source 25 L640/3.072×106 seconds or 2.0
Outputs a signal delayed by 833 x 10-4 seconds.

This 2.0833×10 −4 seconds corresponds to the code period T.

In other words, this shift register 24 corresponds to a first delay circuit. In this embodiment, the delay time of the first delay circuit is set to match the delay time of the delay circuit 3 in the transmitter shown in FIG. .

Now suppose that the intermediate frequency and clock frequency are both exactly 2.
If 4KHz and 3.072MHz, shift register 2
The output waveform 4 is exactly the waveform 13 in FIG. 2 delayed by T.

However, if we consider a case where the intermediate frequency is shifted by 400 Hz, the phase will shift by 30° in 2.0833×10 −4 seconds.

Waveform 14 in FIG. 2 shows the output phase θ3 of shift register 24 in such a case.

The output of the shift register 24 is applied to a differentiating circuit 27.

The differentiating circuits 26 and 27 both generate pulses at the points where the input square wave changes from negative to positive.

Pulses corresponding to this change point are respectively applied to the set terminal and reset terminal of the flip-flop 28, and the output Q remains at a high potential from the time when the output pulse of the differentiating circuit 26 is applied until the time when the output pulse of the differentiating circuit 27 is applied. .

This output Q is added to the AND gate 29 and is 3.072MH
z clock pulse is added to the 7-bit counter 32.

Further, the output of the differentiating circuit 26 is also connected to clear the counter 32.

If the phase difference between θ2 and θ3 is O, the pulse applied to the counter 32 is 0, and when the phase difference between θ2 and 03 is 360°, the number of pulses is 3.072MHz/24KHz=128
becomes.

In other words, the number of pulses is proportional to the phase difference between θ2 and 03.

The contents of this counter 32 are written into a 7-bit memory 33 in synchronization with the first output pulse of the differentiating circuit 27 within the sample interval of the code set by the output pulse of the timing extraction circuit 23.

In this case, the intermediate wave number enters 5 cycles during the code period T, and 5 pulses are output from the differentiating circuit 2γ, but since this T and the intermediate frequency are asynchronous, the sample time of the code is not always at the optimal point. It is not limited to this, but changes within a range of 10T/10 before and after the optimum point.

To solve this problem, an interpolation method can be used.

The difference Δθ1 between θ2 and θ3 at the sampling time point stored in the memory 33 is read out from the output terminal 40.

Here, a circuit block 100 consisting of a shift register 24, differentiating circuits 26, 27, flip-flops 28, 30, AND gates 29, 31, a counter 32, and a memory 33 is a conventional phase difference detection circuit, and is the first phase difference detection circuit in the present invention. constitutes a phase difference detection means.

The change in Δθ1 is shown by waveform 15 in FIG.

This Δθ1 is applied from a terminal 40 to a 7-bit subtraction circuit 36, which is a two-symbol period delay circuit consisting of 7-bit memories 34 and 35.

The memories 34 and 35 operate to write input signals in accordance with the output pulses of the timing extraction circuit 23, and function as delay circuits of two code periods.

In this embodiment, the delay time of the second delay circuit composed of the memories 34 and 35 is set to match the delay time of the delay circuit 5 in the transmitter shown in FIG.

The output Δθ2 of the memory 35 is Δθ1 delayed by 2T, and this change is shown by waveform 16 in FIG.

Δθ2 and Δθ1 are subtracted by Δθ2−Δθ1 in a subtraction circuit 36, and Δθ3 is obtained as an output.

Here, the subtraction circuit 36 has a 7-bit configuration and performs subtraction modulo 128 since the full scale is 128.

In terms of phase, this means that subtraction is performed modulo 360°.

A circuit block including these memo IJs 34 and 35 and the subtraction circuit 36 constitutes second phase difference detection means in the present invention.

A waveform 17 in FIG. 2 shows how the phase difference change amount Δθ3 changes.

This Δθ3 is applied to the identification circuit 37.

The identification circuit has a value of △θ3 of [0~45°, 315°~36
00), (45°~135°), [135°~225°
), [225° to 315°], that is, the output of the subtraction circuit 36 is [0 to 16, 112 to 128].

When the range is [16-48), [48-80), (80-112], the output code dn is 0, 1, 2, respectively.
．． 3 and outputs it to the decoding output terminal 38.

In FIG. 3, a block 200 with 39 as an input terminal and 38 as an output terminal is a differential phase demodulator.The change in dn is shown by waveform 18 in FIG.

As is clear from the figure, d matches an.

This shows that the 30° phase error caused in the delay circuit due to the 400 Hz shift in the intermediate frequency has no effect on the discrimination in the discrimination circuit.

Although the case where the frequency deviation is 400 Hz is shown here, there is no essential limit to the magnitude of this deviation in the demodulation process.

It suffices if it is less than a certain extent compared to the bandwidth of the band-limiting filter 21.

In the embodiment shown in FIG. 3, the delay time of the first delay circuit and the delay time of the second delay circuit are made to correspond to the delay circuit 3 and the delay circuit 5 of the transmitter shown in FIG.
are selected.

Even if this correspondence relationship is reversed, the demodulation operation will still be performed normally.

In addition, the high-order differential phase modulation method that can obtain the effects of the present invention is not limited to the case where l and k are 1 and 2, respectively, as described above, but in general, it is sufficient that l and k are integers of 1 or more. The delay times of the delay circuit and the second delay circuit may be selected as kT and AT, respectively, or as lT and kT, respectively.

The reason for this will be explained next using a formula.

Below, symbol a is used for simplicity. Addition and subtraction of the modulus N regarding b+e and addition and subtraction of the modulus 360° regarding the symbol θ are both abbreviated as + and -, respectively.

The code conversion on the transmitting side uses the above-mentioned symbols, where A is an integer greater than or equal to 1, and p=3600/N.

Let us now assume that the delay time of the first delay circuit is kT and the delay time of the second delay circuit is lT, and furthermore, the steady phase error occurring in the transmission path and the phase error occurring in the first delay circuit are α and β, respectively. Then θ2°θ3. △θ1. △θ2. △θ
3 time series θ2. n, θ3. n.

△θ△θ△θ are respectively as follows Ln'2+n'3+n is expressed in

Solving this equation sequentially, we get is obtained.

What can be solved from equation (1) is that the phase error α and β are both canceled and are not included in Δθs and H, and that the value of Δθ3+n does not change even if k and l are replaced.

In other words, this demodulation method enables demodulation that is not affected by steady phase errors that occur in the transmission path and phase errors that occur in the first delay circuit due to changes in the delay time of the first delay circuit or changes in the input frequency. It is.

Furthermore, the delay times of the first and second delay circuits are kT, respectively.
It can be seen that it is possible to choose , AT, or lT and kT.

△θ3. Demodulation from H is performed as follows. Formula (1
), (2), and (3) with respect to an, we get the following.

Substituting equation (12) into the above equation, we get So, △θ3. .

You can get transmission information from . At this time, the sending information an
are discrete values, and Δθ3 and 11 are generally continuous values due to superimposition of noise, so it is necessary to identify an from the range of values of ΔθLn.

The identification circuit performs this function.

In the above explanation, only the phase error occurring in the first delay circuit was considered as a problem, and it was shown that this can be removed.

The reason is that a high frequency signal passes through the first delay circuit.
This is because even a slight variation in delay time has a large influence on the phase difference and cannot be ignored.

On the other hand, since the second delay circuit passes a baseband signal indicating the phase value, variations in delay time have little effect on the phase value.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention, in which 40 is a signal input terminal, 41 is a delay line with a code period T, 42 and 43 are multiplier circuits, and 45° and 46 are low-pass filters. The multiplication circuit and the low-pass filter constitute a multiplication type phase difference detector.

Block 44 is a 90° phase shifter. If the phase of the signal corresponding to the n-th sign at the matching terminal 40 is expressed as θ(n), then C05(θ(n)−θ(n−1)) from the filter 45
) is 5 inches from the filter 46 (θ(n)-θ(n-1
)) is obtained.

A multiplication type phase comparator can determine the phase difference only when it has both a cosine output and a sine output.

Block 300 constitutes the first phase difference detection means in the present invention.

The cosine output from the filter 45 and the sine output from the filter 46 are each divided into two, and one side is sent to multipliers 49 and 52 via delay lines 47 and 48 with a delay time of 2T.
0.51 and the other is directly added to the multiplier 49.
51 and 50.52.

The output of multiplier 49.50 is added to adder 53, which output is cos(θ(n)-θ(n-1))Xcos(θ(n-
2)-θ(n-3))-+5in(θ(n)-θ(n-
1))xsin(θ(n-2)-θ(n3))-cos
((θ(n)-θ(n-1))-(θ(n-2)-θ(
, , -3)): ].

This represents the cosine of the amount of change in phase difference at a time point separated by 7 sample periods of the sequence consisting of the phase difference between adjacent symbols of the input signal phase sequence θ(n), and the output of the subtractor 54 is the same. and 5in((θ(n)-θ(n-1))-(θ
(n2)-θ(n-3))), which represents the sine of the amount of change in the phase difference.

In other words, from the outputs of the adder 53 and the subtracter 54, (θ(n)−
θ(n-1))-(θ(n-2)-θ(n-3)) can be known.

As explained in connection with the previous embodiment, it is possible to decode a transmission code unaffected by carrier frequency changes and delay time fluctuations from such a phase difference change amount.

This block 400 constitutes the second phase difference detection means in the present invention.

The phase difference of the output of this block 400 is applied to an identification circuit 55 where the transmitted code is decoded and the output code is obtained at a terminal 56.

FIG. 5 is a block diagram showing the structure of a part of the embodiment shown in FIG. 4, and the components 42, 43, 44, 45, 46 are exactly the same as those in FIG.

57, 58 is a multiplicative modulator, 59 is a 90° phase shifter 60
is an oscillator with a frequency not too high compared to the code period, and 61 is an addition/synthesis circuit.

The operation of block 300' is to generate a signal having a phase equal to the phase difference of the signals at input terminals 62, 63 and whose frequency is the new carrier frequency, ie the oscillation frequency of oscillator 60.

This can be seen as a type of phase difference detection circuit that outputs the phase difference between two input signals in the form of a new carrier wave phase.

A part of the output of this block 300' is connected to a delay line 400'.
, the other part directly becomes the input of block 500'.

The delay line 400' has a delay time of 2T.

In this case, if the frequency of the oscillator 60 is selected to be not much larger than 1/2T, the frequency fluctuation of the oscillator 60 and the delay fluctuation of the delay line 400' will not have a large effect on the phase error.

Block 500' is an in-phase-quadrature detection circuit including a product detector 64, a 65.90° phase shifter 66, and a reduced pass filter 67.68.

This block serves to output the cosine of the phase difference between the two input signals at terminals 71, 72 to terminal 69 and the sine to terminal TO; this output signal is transmitted to block 50 of the embodiment of FIG.
Equivalent to an output signal of 0.

In other words, this block 500' and delay line 400' constitute the second phase difference detection means in the present invention.

FIG. 6 is a block diagram showing still another embodiment of the present invention, in which 73 is a signal input terminal, 74 is an oscillator (which may be asynchronous) with a frequency approximately equal to the carrier frequency of the signal, and 75 is a block diagram showing the phase of the oscillator 74. A phase detector 76 detects the input signal phase as a reference, a delay circuit 76 with a code period T, and a subtraction circuit that obtains the difference between two input signals.The block 600 composed of these elements is the first aspect of the present invention. It constitutes phase difference detection means.

Further, 78 is a 2T delay circuit, and 79 is a subtraction circuit that obtains the difference between two input signals, and a block 700 composed of these elements constitutes the second phase difference detection means of the present invention.

The amount of change in phase difference obtained from block 700 is decoded into the original code by identification circuit 80, and the result is obtained from output terminal 31.

The operation of this embodiment is easily understood from the description of the embodiment above.

Further, as the phase detector 75 in this embodiment, a phase difference detection circuit constituted by the elements 26 to 33 of the embodiment in FIG. Circuits 76 and 78 are memory,
A digital subtracter can be used for the subtraction circuits 77 and 79.

FIG. 7 is a block diagram showing the configuration of still another embodiment of the present invention.

The components 73, 74, 75, 80, 81 are exactly the same as those in FIG.

Reference numerals 82, 83, and 84 are delay circuits for time T, and in this embodiment, the amount of change in phase difference is collectively calculated by the addition/subtraction circuit 35 from the phases of the input signals at four points in time.

In the addition/subtraction circuit 85, (output of phase detector 75) - (
By performing the calculation of (output of delay circuit 82) - (output of delay circuit 83) + (output of delay circuit 84), the output of addition/subtraction circuit 85 will completely correspond to the output of subtraction circuit 79 in the embodiment shown in FIG. it is obvious.

In this example, block 800 includes the first and second
It can be thought of as having both functions of the phase difference detection means.

Although the embodiments have been described above, the embodiments here are based on codes of 0.1, 2, . …….

0°36 of the second-order difference in the phase of the transmitted signal with respect to N-1
0°/N, 720'/N,..., 360°×(N-1)
/N respectively, but this is not limited to this case, and applies to 0.1.2... of the code of the N value.
..., N-1 is 360° of the second-order difference in the phase of the transmitted signal
(1/2N), 360°×(3/2N), 360°×(
-5/2N), . . . , 360°×(2n-1/2N).

As described above, according to the present invention, it is possible to obtain a differential phase demodulator that is resistant to carrier frequency fluctuations and delay circuit stability, and is suitable for transmitting slow rate information using phase modulation at a high carrier frequency. It is effective when used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transmitting device that generates a high-order differential phase modulation signal, which is the object of the device of the present invention, and FIG. 2 is a waveform diagram showing the operation of the device in FIG. 1 and the device in FIG. 3. 3 is a block diagram of an embodiment of a receiving device to which the present invention is applied. FIG. 4 is a block diagram of another embodiment of the present invention, FIG. 5 is a block diagram showing another embodiment of some of the components of the embodiment of FIG. 4, and FIGS. 6 and 7 are also in accordance with the present invention. FIG. 3 is a block diagram of each embodiment of FIG. In addition, in FIG. 3, 200 is a differential phase demodulator, 100
is a first phase difference detection circuit, memories 34, 35 and subtracter 36 are a second phase difference detection circuit, and 37 is an identification circuit.

Claims (1)

[Claims] 1, when l is an integer greater than or equal to 1, a pair of codes to be transmitted is expressed as a discrete phase difference between symbols separated by l symbols in a time series consisting of a phase difference between two symbols separated by l symbols of the transmitted signal. a first phase difference detection means for detecting a phase difference between two points of time corresponding to a symbol period of l or 1 of an input signal, which is targeted at a high-order differential phase modulation signal that has been phase-modulated so as to correspond to each other; The present invention is characterized by comprising a second phase difference detection means for detecting the amount of change in phase difference between two points in time when the phase difference has k or l symbol periods, and identification means for decoding the original code from this amount of change in phase difference. differential phase demodulator.