JP2748727B2 - Carrier synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital carrier synchronizing circuit used in a multilevel quadrature amplitude modulation type demodulator and, more particularly, to a carrier wave for switching a signal point for obtaining phase information when a carrier phase error increases. Related to a synchronous circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional digitized carrier synchronization circuit in a 16-level quadrature amplitude demodulator. In FIG. 2, the input modulated wave a is branched into two and becomes one input of each of the multiplier 1 and the multiplier 2. In addition, a voltage controlled oscillator (VC
O) The output (reproduced carrier signal) j1 of 15 is directly input to the other input of the multiplier 1 and is also input to the π / 2 phase shifter 17 for 90
Phase-shifted to form a quadrature reproduced carrier signal j2 and a multiplier 2
Is the other input. As a result, the multiplier 1 (2) outputs the demodulated baseband signal b1 (b2) synchronously detected to the A / D converter 3 (4) and the clock recovery circuit (CLK) 16.

The A / D converter 3 (4) converts the demodulated baseband signal b1 (b2) to a clock recovery circuit (CLK) 16
The digital signals (c1 to c4, d1 to d4) are identified by the reproduced clocks h1 (h2) from
Is output.

Here, output digital signals (c1 to c
4, d1 to d4) represent the first bit (MSB), the second represents the second bit, the third represents the third bit, and the fourth represents the fourth bit, but c1 and c2 on the in-phase side (quadrature side). D1 and d2)
Is the identification result of the quaternary demodulated baseband signal b1 (b2), which is an output v to a demodulation system (not shown).

In the digitized carrier synchronization circuit, the carrier synchronization detection signal u generated by the VCO 15 is output.
(“0” during “synchronous” and “1” during “asynchronous”) according to the first bit c1 (d
1) and the synchronization maintaining control using the amplitude error signal c3 (d3), and the output digital signals (c1 to c4, d1 to d).
Synchronous pull-in control at the time of asynchronous using all of 4) is performed.

First, in the synchronization maintaining control, the exclusive OR of the first bit c1 (d1) of the in-phase component (quadrature component) and the amplitude error signal d3 (c3) of the quadrature component (in-phase component) is calculated. The circuit 6 (7) takes the difference between the outputs of the two exclusive OR circuits, and the subtracter 8 obtains the difference between the outputs to obtain the phase control signal g. This becomes input data of the flip-flop (F / F) 11. The clock of the F / F 11 is the output e3 of the OR circuit 10, but at the time of synchronization, an AND circuit (AND)
9 is at the “0” level, the logical sum circuit 1
0 output e3 is CLK16 output (reproduced clock) h3
It is. That is, the F / F 11 captures the phase control signal g by the reproduction clock h3 and outputs the retimed phase control signal i1. This phase control signal i1 has its noise component removed by a loop filter (LPF) 14,
The phase control signal i2 is input to the VCO 15,
15 outputs a reproduced carrier signal j1.

Next, in the asynchronous state, in order to secure a sufficiently wide synchronization pull-in range, only the phase control information obtained from the desired signal point is fed back to the VCO 15, and the phase control information obtained from other than the desired signal point is immediately before. It works to replace it with valid information. That is, all of the output digital signals (c1 to c4, d1 to d4) of the A / D converter 3 (4) are input to the logic circuit 5, and a desired signal point is detected. The output e1 of the logic circuit 5 is at the "0" level at the time of detection, and at the "1" level at the time of non-detection. Therefore, during the asynchronous operation, the output e2 of the AND circuit 9 is output.
Is "0" according to the signal level of the output e1 of the logic circuit 5.
Or "1". As a result, the AND circuit 9
The output e3 of the OR circuit 10 which takes the logical sum of the output e2 of the clock signal and the reproduction clock h3 outputs the reproduction clock h3 only when a desired signal point is detected, and is fixed at "1" level in the case of no detection. .

In short, when a carrier signal is asynchronous, when a desired signal point is detected, a phase control signal g obtained from the signal point is obtained.
Is taken into the F / F11, retimed and the VCO
On the other hand, when a desired signal point cannot be detected, the phase control signal g immediately before the non-detection is stored in the F / F 11, and the VCO 15 operates based on the stored signal.

[0009]

In the above-described conventional digital carrier synchronization circuit, the phase control information is obtained from all signal points at the time of carrier synchronization. However, when the error rate increases, the loop gain increases. And the synchronization pull-in range is reduced. Further, when the carrier wave is not synchronized, phase control information is obtained only from a desired signal point to expand the synchronization pull-in range. However, this causes a problem of increasing a noise level.

For example, in the case of 16QAM, if the desired signal points for performing phase control are eight points on a diagonal line, the phase control signal is held with a probability of about 1/2, so that the equivalent clock cycle is doubled. And the noise level increases by about 3 dB as compared with the normal state. For this reason, if noise or the like is added to the input of the demodulator, the S / N deteriorates greatly and the synchronization may not be obtained.

An object of the present invention is to provide a carrier synchronizing circuit which can obtain a sufficiently wide synchronization pull-in range even when the error rate increases and can reduce the noise level.

[0012]

In order to achieve the above object, a carrier synchronization circuit according to the present invention has the following configuration. That is, the carrier synchronization circuit of the present invention is a digitized carrier synchronization circuit used in a multi-level quadrature amplitude modulation type demodulator; an error rate measurement circuit for receiving an amplitude error signal and observing an error rate; The signal points for generating the phase control signal to the voltage-controlled oscillator in response to the output of the measurement circuit are all signal points when the error rate is equal to or less than a specified value, and are desired when the error rate is equal to or more than a specified value. And a switching circuit that controls so as to repeat at a predetermined interval between the case where the signal point is set and the case where all the signal points are set.

[0013]

Next, the operation of the carrier synchronization circuit of the present invention having the above-described configuration will be described. In the present invention, the phase control signal to the voltage-controlled oscillator is generated from all signal points when the error rate is equal to or less than a specified value, and when the error rate is equal to or larger than a specified value (including both synchronous and asynchronous times). ) Repeats at a predetermined interval between the case of creating from desired signal points and the case of creating from all signal points. As a result, a sufficiently wide synchronization pull-in range can be secured, and the noise level can be reduced.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a carrier synchronization circuit according to one embodiment of the present invention. The demodulator is 1 like the conventional circuit (FIG. 2).
It is a six-level quadrature amplitude demodulator. Therefore, in FIG. 1, the same components as those of the conventional circuit are denoted by the same reference numerals. In the present invention, the error rate measurement circuit 12 and the switching circuit 13 are provided, and the output f2 of the switching circuit 13 is supplied to the AND circuit 9 so that the operation is performed without distinction between the synchronous time and the asynchronous time.
Hereinafter, a description will be given mainly of a portion according to the present invention.

In the error rate measuring circuit 12, the A / D converter 3
Upon receiving the first bit c1 (d1) of the in-phase component (quadrature component), which is the output of (4), and the amplitude error signal d3 (c3),
The error rate characteristic is measured. When the error rate characteristic is equal to or more than a specified value, the output f1 is set to, for example, “1” level (including the time of synchronization and asynchronous time). "0" level.

The switching circuit 13 receives the output f1 of the error rate measuring circuit 12, and when f1 = "0", always sets the output f2 to "0" level. As a result, the output e2 of the AND circuit 9 becomes “0” level irrespective of the signal level of the output e1 of the logic circuit 5 as in the related art, so that the output e3 of the OR circuit 10 becomes the reproduction clock h3, F / F11
Receives phase control information g for all signal points,
Is output.

On the other hand, the switching circuit 13 receives the output f1 of the error rate measuring circuit 12, and when f1 = "1", the output f2 is a signal that repeats the "1" level and the "0" level at predetermined intervals. To As a result, in the signal section where f2 = “0”, the phase control information g for all signal points is captured and output to the F / F 11 in the same manner as described above.
In the signal section of "1", when the signal level of the output e1 of the logic circuit 5 is "0", that is, when a desired signal point is detected, the phase control information g for the desired signal point is F / F.
F11 captures and outputs.

[0018]

As described above, according to the carrier synchronization circuit of the present invention, the phase control signal to the voltage controlled oscillator is
When the error rate is equal to or less than a specified value, the signal is created from all signal points. On the other hand, when the error rate is equal to or more than a specified value (including both synchronous and asynchronous), the signal is created from a desired signal point and all signals are generated. Since the creation from the point is repeated at a predetermined interval, a sufficiently wide synchronization pull-in range can be secured, and the noise level can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a carrier synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional carrier wave synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Multiplier 3 A / D converter 4 A / D converter 5 Logic circuit 6 Exclusive OR circuit 7 Exclusive OR circuit 8 Subtractor 9 Logical product circuit 10 Logical OR circuit 11 Flip-flop (F / F) 12 error rate measurement circuit 13 switching circuit 14 low-pass filter (LPF) 15 voltage-controlled oscillator (VCO) 16 clock recovery circuit (CLK) 17 π / 2 phase shifter

Claims (1)

(57) [Claims] 1. A digitized carrier synchronization circuit used in a multi-level quadrature amplitude modulation type demodulator; an error rate measurement circuit for receiving an amplitude error signal and observing an error rate;
Upon receiving the output of the error rate measurement circuit, signal points for generating a phase control signal to the voltage controlled oscillator are all signal points when the error rate is equal to or less than a specified value, while the error rate is equal to or greater than a specified value. A switching circuit for controlling so as to repeat a case where a desired signal point is set and a case where all signal points are set at predetermined intervals.