JPH0583320A - Carrier synchronization circuit - Google Patents

Abstract

PURPOSE:To reduce the synchronization pull-in time regardless of provision of a wide synchronization pull-in range. CONSTITUTION:A phase error signal (g) of a voltage controlled oscillator 15 generating a carrier is obtained by applying logic control to output data e1, f1 and error signals e3, f3 obtained by applying demodulation and recovering a 16-value orthogonal amplitude modulation wave (a). A logic circuit 7 outputs a negative logic signal point detection signal (k) only when an input signal (a) is at a specific signal point. Furthermore, the voltage controlled oscillator 15 outputs a negative logic carrier synchronization detection signal l. Only the phase error signal (g) at a specific signal point at carrier asynchronization is fed back to the voltage controlled oscillator 15 by applying retiming to the signal (g) at a flip-flop 13 receiving a signal obtained through logic operation of the signals k, l and a recovered clock (h) as clock inputs. An error rate discrimination circuit 18 monitors an error rate in the carrier synchronization process and changes signal points detected by the logic circuit 7 to all signal points when the error rate reaches a prescribed value or below.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digitized carrier synchronizing circuit used in a multilevel quadrature amplitude modulation system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a 16-value quadrature amplitude demodulation circuit using a conventional digitized carrier synchronizing circuit.

This demodulation circuit receives the modulated wave a as an input, and multiplies the input signal a by a carrier wave having a π / 2 radian phase difference, which is formed by the voltage controlled oscillator 15 and the π / 2 phase shifter 17. , 2 for synchronous detection to obtain demodulated baseband signals b1 and b2. These baseband signals b
1, 1 and 2 are input to A / D converters 3 and 4, and digital signals c1 to c4 and d1 to d4 are obtained. These digital signals c1 to c4 and d1 to d4 are input to the transversal equalizers 5 and 6 and equalized, and then the digital signal e1.
~ E4, f1 to f4 are obtained. e1, e2, e3, and e4 are the first bit (MSB) of the in-phase component (Pch),
The second bit, the third bit, and the fourth bit are set to f1, f2,
f3 and f4 are the first bit (MS) of the orthogonal component (Qch)
B), second bit, third bit, fourth bit, e
1, e2 are identification results of the four-valued baseband signal b1, f
1 and f2 are identification results of the four-valued baseband signal b2 and are output respectively. e3 represents an in-phase component (Pch) amplitude error signal, and f3 represents a quadrature component (Qch) amplitude error signal.

In the digitized carrier wave synchronizing circuit, the first bit e1 of the in-phase component (Pch) and the quadrature component (Qch) are used.
Error signal f3, the first bit f1 of the quadrature component (Qch)
And the in-phase component (Pch) error signal e3 are subjected to exclusive OR operation by the exclusive OR circuits 8 and 9, respectively, and the subtracter 1
The phase control signal g is obtained by taking the respective differences by 0. The phase control signal g is further input to the clock input ma.
It becomes the signal i re-timed by the flip-flop 13 and then becomes the phase control signal j from which the noise component is removed by the low pass filter 14 to control the voltage controlled oscillator 15. Furthermore, digital signals e1 to e4 and f1 to f4
Is input to the logic circuit 7a to obtain a negative logic signal ka by detecting only a desired signal point. l is a negative logic carrier wave synchronization detection signal, and the signal point detection signal kb is input to the logical sum circuit 12 to which the reproduction clock h is input by the AND circuit 11 when the carrier wave is not synchronized. Then, as the clock input ma of the flip-flop 13 that is retiming the phase control signal g, the reproduction clock h is output when a desired signal point is detected when the carrier wave is asynchronous. That is, when the carrier wave is asynchronous, only the phase control information obtained from the desired signal point is fed back to the voltage controlled oscillator 15, and the phase control information obtained from other than the desired signal point is replaced with the immediately preceding valid information. Further, the phase control information obtained from all the signal points is input to the voltage controlled oscillator 15 when the carrier wave is synchronized.

[0005]

The quadrature amplitude demodulation circuit using the above-described conventional digitized carrier wave synchronizing circuit only outputs the phase control information from a certain specific signal point at the time of non-synchronization in order to expand the synchronization pull-in range. Since it is used, there is a drawback that it takes time to pull in when synchronization is lost.

[0006]

A carrier synchronizing circuit of the present invention is a digitized carrier synchronizing circuit used in a multi-valued quadrature amplitude modulation system, which comprises a logic circuit for detecting only predetermined signal points and a carrier. A detection circuit that detects that the phase error has increased, a carrier phase control circuit that uses only the phase information of the predetermined signal point when the carrier phase error increases based on the detection result of this detection circuit, and an error An error rate determination circuit for switching the signal points detected by the logic circuit to all the signal points when the error rate falls below a predetermined value while monitoring the rate.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a 16-value quadrature amplitude demodulation circuit using an embodiment of a digitized carrier synchronizing circuit of the present invention.

This demodulation circuit receives the modulated wave a as an input, and multiplies the input signal a by a carrier wave which is formed by the voltage controlled oscillator 15 and the π / 2 phase shifter 17 and has a π / 2 radian phase difference. Synchronous detection is performed at 1 and 2 to obtain demodulated baseband signals b1 and b2. These baseband signals b
1, 1 and 2 are input to A / D converters 3 and 4, and digital signals c1 to c4 and d1 to d4 are obtained. These digital signals c1 to c4 and d1 to d4 are input to the transversal equalizers 5 and 6, and after being equalized, the digital signals e1 to e1.
e4 and f1 to f4 are obtained. e1, e2, e3, and e4 are the first bit (MSB), second bit, third bit, and fourth bit of the in-phase component (Pch), respectively, f1, f2, and f.
3 and f4 are the first bit (MS) of the quadrature component (Qch)
B), second bit, third bit, fourth bit, e
1, e2 are identification results of the four-valued baseband signal b1, f
1 and f2 are identification results of the four-valued baseband signal b2 and are output respectively. e3 represents an in-phase component (Pch) amplitude error signal, and f3 represents a quadrature component (Qch) amplitude error signal.

In the digitized carrier wave synchronizing circuit, the first bit e1 of the in-phase component (Pch) and the quadrature component (Qch) are used.
Error signal f3, the first bit f1 of the quadrature component (Qch)
And the in-phase component (Pch) error signal e3 are subjected to exclusive OR operation by the exclusive OR circuits 8 and 9, respectively, and the subtracter 1
The phase control signal g is obtained by taking the respective differences by 0. The phase control signal g becomes a signal i re-timed by the flip-flop 13 by the clock input m, and then becomes a phase control signal j from which the noise component is removed by the low pass filter 14 to control the voltage controlled oscillator 15. .. Further, the digital signals e1 to e4 and f1 to f4 are input to the logic circuit 7 to obtain a negative logic signal k in which only desired signal points are detected. Reference numeral l is a negative logic carrier wave synchronization detection signal, and the signal point detection signal k is input to the logical sum circuit 12 to which the reproduction clock h is input by the AND circuit 11 when the carrier wave is asynchronous. The clock input m of the flip-flop retiming the phase control signal g
As a result, the reproduction clock h is output when a desired signal point is detected when the carrier wave is asynchronous. That is, when the carrier wave is asynchronous, only the phase control information obtained from the desired signal point is fed back to the voltage controlled oscillator, and the phase control information obtained from other than the desired signal point is replaced with the immediately preceding effective information. In addition, the phase control information obtained from all the signal points is input to the voltage controlled oscillator during carrier wave synchronization.

A feature of the present invention is that the signal points for obtaining the phase control information are switched in the synchronization process in order to shorten the synchronization time after the carrier synchronization is lost.

In the embodiment of FIG. 1, when carrier synchronization is lost, the transversal equalizers 5 and 6 are once reset to prevent divergence of control. At this time, the error of the digital output signal becomes large, the loop gain decreases, and the sync pull-in range decreases. Therefore, only the phase control signal at a certain signal point is used to prevent the reduction of the sync pull-in range. Up to this point, it is the same as in the conventional example of FIG.

On the other hand, since the transversal equalizers 5 and 6 operate so as to reduce the error signals of their output signals, the use of all the signal points as the control information has the characteristic of focusing faster. ing. Therefore, immediately after the synchronization for resetting the transversal equalizers 5 and 6 is lost, a selection control method using only a certain signal point is used to prevent the decrease of the synchronization pull-in range, and the error rate determination circuit 18 sets While monitoring, when the error rate is below a certain fixed value, the logic circuit 7 is controlled to set the signal point detection signal k to "0", thereby switching to all-point control using all signal points.

As a result, the baseband signals b1 and b2
It is possible to prevent the reduction of the synchronization pull-in range and to shorten the synchronization pull-in time in the initial stage of the synchronization pull-in in which the error of the identification result is large.

[0015]

As described above, according to the present invention, a carrier point having a necessary and sufficient sync pull-in range and an excellent sync pull-in time is obtained by switching signal points for obtaining phase information in a digitized carrier synchronizing circuit in the synchronizing process. A synchronous circuit can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a demodulation circuit using an embodiment of a carrier synchronization circuit of the present invention.

FIG. 2 is a block diagram showing an example of a conventional demodulation circuit.

[Explanation of symbols]

 1, 2 Multiplier 3, 4 A / D converter 5, 6 Transversal equalizer 7 Logic circuit 8, 9 Exclusive OR circuit 10 Subtractor 11 Logical product circuit 12 Logical sum circuit 13 Flip-flop 14 Low-pass filter Wave device 15 Voltage controlled oscillator 16 Clock signal recovery circuit 17 π / 2 phase shifter 18 Error rate determination circuit

Claims (1)

[Claims] 1. A digitized carrier synchronizing circuit used in a multi-valued quadrature amplitude modulation system, which is a logic circuit for detecting only predetermined signal points and a detecting circuit for detecting that a carrier phase error has increased. And when the carrier phase error becomes large based on the detection result of the detection circuit, a carrier phase control circuit that uses only the phase information of the predetermined signal point, and the error rate is a predetermined value while monitoring the error rate. A carrier synchronization circuit, comprising: an error rate determination circuit for switching the signal points detected by the logic circuit to all the signal points when: