JPH06291791A - Demodulator for phase modulation wave signal - Google Patents

Abstract

PURPOSE:To provide the demodulator for a phase modulation wave signal provided with a clock reproduction function in which clock phase locking is possible even in an asynchronization state of a carrier at the time of demodulation of an OQPSK signal. CONSTITUTION:An input QPSK modulation wave is distributed to a synchronization detection circuit 12 and an orthogonal detection circuit 13, digitized in-phase and orthogonal detection outputs are fed to a complex multiplier circuit 19, and the spectrum is shaped and the result is inputted to a complex multiplier circuit 22. An output of the complex multiplier circuit 22 is fed to a clock phase error detection circuit 23, a data recovery circuit 24 and a symbol phase selection circuit 37. The clock phase error detection circuit 23 extracts a clock phase error component by the zero crossing system and provides an output of the symbol phase for phase detection and the data recovery circuit 24 discriminates QPSK data based on the supplied I, Q signals to provide an output of demodulation data.

Description

Detailed Description of the Invention

[0001]

This invention relates to an offset QPSK.
The present invention relates to a demodulator for a phase-modulated wave signal with improved clock phase synchronization means used in a (Quadrature Phase Shift Keying) demodulator circuit.

[0002]

2. Description of the Related Art As is well known, in the OQPSK signal, the change points of symbols on two axes orthogonal to each other occur at the same timing in a normal QPSK signal, but the change points are the symbol length (T). Is configured to be offset by ½ of, and the change point is offset to suppress the phase change at the code change point to 90 ° or less,
It is characterized in that the amplitude change at the time of band limitation can be made smaller than that of the conventional QPSK signal.

As a demodulation system for such an OQPSK signal, since it is a signal that can take four-valued phase states, demodulation is performed by a carrier recovery circuit and a clock recovery circuit similar to those of the conventional QPSK signal, and this is reproduced. A method is generally used in which the code is reproduced based on the clock.

First, a demodulation system for a QPSK signal will be described. FIG. 8 shows a conventional digital demodulation circuit for a QPSK signal.
The modulated wave is distributed and supplied to the in-phase detection circuit 12 and the quadrature detection circuit 13. A fixed frequency signal from a first local oscillator 14 is supplied to these detection circuits 12 and 13, and a local oscillation (hereinafter abbreviated as local oscillation) signal from this oscillator 14 is distributed by a distributor 15. Then, the 0 degree phase local oscillation signal and the 90 degree phase local oscillation signal shifted by the 90 degree phase shifter 16 are supplied to the detection circuits 12 and 13, respectively. The output signals from the detection circuits 12 and 13 are converted into digital values by the A / D converters 17 and 18.

The in-phase and quadrature detection outputs digitized by the A / D converters 17 and 18, respectively, are input to a complex multiplication circuit 19 which realizes frequency conversion. Local output from the AFC loop to be described later as a carrier (second local oscillator output)
Is supplied.

The output from the complex multiplication circuit 19 is input to the digital low-pass filters 20 and 21 having the same frequency transfer characteristic, and the spectrum is shaped respectively. These digital filters 20 and 21 are filters for forming a transfer characteristic required for preventing intersymbol interference in digital data transmission, and generally, when combined with a filter on the transmission side, a so-called roll-off characteristic. Is designed to be obtained. Therefore, in the outputs of the digital filters 20 and 21, each detection output is spectrally shaped so that the eye opening ratio becomes sufficiently large.

The outputs from the digital filters 20 and 21 are input to the complex multiplication circuit 22. The complex multiplication circuit 22 can realize exactly the same operation as the frequency converter in the intermediate frequency band, that is, the mixer in the baseband. Here, a multiplier of a real number type that does not use a complex number can perform a detection operation, but cannot express a negative frequency component, and therefore cannot be a general frequency converter. Therefore, a complex multiplication circuit that enables complex number expression is used. The output of the complex multiplication circuit 22 is the clock phase error detection circuit 2
3, the data reproducing circuit 24, and further the phase detection circuit 25 are distributed and supplied to three.

The clock phase error detection circuit 23 extracts the clock phase error component by the zero-crossing method. After smoothing by the low pass filter (LPF) 26, the voltage controlled oscillator 27 is controlled to obtain the phase synchronized clock. Are fed back to the clock inputs of A / D converters 17 and 18. The data reproduction circuit 24 determines the QPSK data by binarizing each of the I and Q signals supplied from the complex multiplication circuit 22, thereby outputting the demodulated data.

Further, the output from the complex multiplication circuit 22 is input to the phase detection circuit 25, and the input signal and the numerically controlled oscillator (N
The phase difference with the CO) 29 is detected, and this phase difference information from the phase detection circuit 25 is supplied to the frequency control terminal of the NCO 29 via the loop filter 28 for carrier regeneration. This NCO 29 is composed of a cumulative addition circuit that does not inhibit overflow, and because it performs an addition operation up to its dynamic range according to the value of the signal input to its frequency control terminal, it enters an oscillating state. The oscillation frequency changes according to the value of the control signal.

That is, the NCO 29 performs exactly the same operation as a voltage controlled oscillator (VCO) in an analog circuit, but the point different from a general VCO is that its oscillation frequency is very stable, and so-called. It has a stability higher than that of a VCXO using a crystal, and a wide frequency variable range that cannot be realized by VCOX.

The output from the NCO 29 is distributed and supplied to the data conversion circuits 30 and 31 having sine and cosine characteristics, respectively, and converted into carriers. The output carriers from the data conversion circuits 30 and 31 are supplied to the complex multiplication circuit 22 for detection,
This complex multiplication circuit 22, phase detection circuit 25, loop filter
The loop formed by 28, the NCO 29, and the data conversion circuits 30 and 31 is a digital PLL.

In this demodulation system, an AFC loop is formed. That is, the phase error signal output from the phase detection circuit 25 is the frequency error (Δf) detection circuit.
The Δf detection circuit 32 detects the frequency error between the input signal and the local oscillator (first local oscillator and second local oscillator). This frequency error component Δf is A
After being smoothed by the FC loop filter 33, it is supplied to the frequency control terminal of the NCO 34. Since the output of the NCO 34 is a sawtooth signal, it is input to the data converters 35 and 36 having the conversion characteristics of sine and cosine, and the outputs from the data converters 35 and 36 are complex as a second local oscillator. It is supplied to the multiplication circuit 19. And by this, AFC
A loop is formed.

When the AFC operation is performed and the frequency detuning of the predetermined relationship between the input signal and the local oscillation becomes sufficiently small, the frequency error detection output of the Δf detection circuit 32 changes, and the Δf detection circuit 32 loops. While the switching signal is output,
The AFC hold signal is output. This signal is substantially the same, and the loop switching signal switches the loop filter 28 in the PLL to the operating state. This switching starts the PLL operation, and the output of the AFC loop filter 33 becomes the state at that time. To be held. Then, the pull-in operation is started so that the PLL is synchronized with the carrier.

FIG. 9 shows a concrete configuration of the clock phase error detection circuit 23. This circuit 23 is constructed by a zero crossing system. That is, the phase error is detected in the phase error signal detection circuits 511 and 512 by the I signal and Q signal in the baseband output from the complex multiplication circuit 22.

FIG. 10 explains the method of detecting this phase error, and this figure shows a phase control method by zero crossing. In this figure, (A) shows a simplified eye pattern of a binary digital signal, and there is no problem on average.

Considering the case where the sampling timing is delayed by Te seconds as shown in FIG. 7B, the eye opening is narrowed from W0 to W1. on the other hand,
The value obtained by sampling the input signal at the timing shown in (C) also takes a larger value from the value near zero. When the transmission code changes from "-" to "+" before and after the zero cross point, the sample value takes a positive value of "e _(-+) ", and conversely from "+" to "-". If it changes, e
_(+-) Takes a negative value. By this, by knowing the sample values before and after the zero cross point, it is possible to detect the deviation of the sample timing. But,
The phase error can be detected only when the symbol code changes before and after the zero cross point (zero cross).

In the clock phase error detection circuit 23 shown in FIG. 9, the zero cross determination circuits 513 and 514 determine whether or not the symbol code has changed before and after the zero cross point. This zero-cross determination method may be, for example, to detect the change in the sign of the symbol before and after the zero-cross phase, but in order to improve the determination accuracy, if the amplitude of both symbols is 1/2 or more of the eye amplitude, for example. You may make it add the condition that exists.

The selection circuit 515 is a phase error signal detection circuit when only the I signal is zero-crossed according to the judgment results of the I and Q signal zero-cross judgment circuits 513 and 514.
Select the output of 511, and when only the Q signal is zero crossing, select the output from the phase error signal detection circuit 512,
I when both I and Q signals are zero-crossing
The output of the averaging circuit 516 for averaging the phase error signals from the signal and the Q signal is selected. When both the I signal and the Q signal do not cross zero, the output from the delay circuit 517 which is the clock phase error signal one symbol period before is selected and output as the clock phase error signal.

FIG. 11 shows a constellation and an eye pattern of the QPSK signal. The QPSK signal has a carrier in any phase as shown in FIG.
As shown in (B) and (C) of the figure, the I signal and the Q signal have the same eye opening phase. Therefore, even when the carrier is asynchronous, the phase for pulling in the clock (zero-cross phase) does not change as shown in (D), so that the phase of the clock can be synchronized.

Next, the OQPSK demodulation will be explained.
The demodulation circuit is as shown in FIG. This circuit shares the demodulation circuit for the QPSK signal shown in FIG. 8, and the increase in circuit scale is small. In FIG. 12, the same parts as those in FIG. 8 are shown by using the same reference numerals, but in this OQPSK signal demodulation circuit, the output of the complex multiplication circuit 22 is T /
Two delay circuits 41 are connected.

In such a demodulation circuit, the state in which the switch 40 is connected to the phase detection circuit 25 side is Q shown in FIG.
It has the same configuration as the PSK demodulation circuit and operates as a QPSK demodulation circuit. The switch 40 is a T / 2 delay circuit.
When connected to the 41 side, it operates as an OQPSK demodulation circuit.

In the OQPSK signal, the change points of the symbols of the I signal and the Q signal are deviated by T / 2. Therefore, the switch 40 is turned on to the T / 2 delay circuit side so that the phase detection circuit 25, the clock At the inputs of the phase error detection circuit 23 and the data reproduction circuit 24, the eye pattern phases of the I signal and the Q signal are aligned, and demodulation similar to that of the QPSK signal is performed.

However, the demodulation of such an OQPSK signal has the following problems. Figure 13 shows the OQPS
It shows the constellation and eye pattern of the K signal. (A) shows the case where the carrier phase is "0 °", (B) shows
Indicates the case where the carrier phase is “90 °”, and the phases of the eye patterns of the I signal and the Q signal are switched every time the carrier phase turns 90 °.

Therefore, when the clock phase control is performed by shifting the symbol phase of the Q signal, the clock control is performed so as to be phase-synchronized with the zero cross phase of the I signal. At this time, if the carrier rotates asynchronously, the zero cross phase of the I signal also changes by T / 2 following the change of the carrier, the clock pull-in phase changes, and the clock reproduction is not stabilized. . Therefore, in such a method, stable reproduction of the clock is possible only when the carrier reproduction approaches the established state.

However, as shown in FIG. 12, in a system that performs high-performance carrier reproduction and clock reproduction by digital control, carrier reproduction cannot be performed unless A / D conversion is performed at a timing synchronized with the symbol phase. The contradiction arises that clock recovery must be established first.

[0026]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and particularly, the QPSK demodulation method
When the QPSK demodulation method is used, the clock reproduction must be established even when the carriers are not synchronized, but the clock reproduction is not stable until after the carrier reproduction. Therefore, when the frequency detuning of the carrier is large. A phase-modulated wave signal having a clock recovery function that solves the problem that clock recovery and carrier recovery take a long time to become unstable and enables clock phase synchronization during demodulation of an OQPSK signal and during carrier asynchronization The demodulator of the present invention is intended to be provided.

[0027]

A phase-modulated wave signal demodulating device according to the present invention provides a predetermined phase from an in-phase axis detection output and a quadrature axis detection output in a quadrature detection output which is a band coded pulse code signal. Means for regenerating a clock in synchronization with the first and second phase errors respectively detected from the in-phase axis detection output and the quadrature axis detection output sampled at a predetermined timing of the clock.
The first and second zero-crosses for determining that the phase error detection means and the in-phase detection output or the quadrature detection output each have a specific change between at least two samples before and after the predetermined timing. The effective phase error determination means includes at least the first
The phase error signal effective for the clock phase control is determined from the output of the zero-cross determination means and the output of the second zero-cross determination means, and the phase error signal effective for the clock phase control is output according to the output from the effective phase error determination means. Is selected, and the clock phase is controlled according to the effective phase error signal.

[0028]

According to the demodulator of the phase-modulated wave signal configured as described above, the clock pull-in phase can be kept constant even in the asynchronous state of the carrier, and the clock recovery operation can be performed normally even when the carrier is asynchronous. Then, the demodulation of the OQPSK signal is stabilized.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit configuration of an OQPSK signal demodulation device. The basic configuration part is QPSK shown in FIG.
Since the demodulator is the same as the demodulator, the same reference numerals are given and the description thereof is omitted. In this demodulator, the O
A QPSK modulated wave signal is input, and this input signal is distributed and supplied to the in-phase detection circuit 12 and the quadrature detection circuit 13.

I output from the complex multiplication circuit 22
The signal and the Q signal are supplied to the clock phase error detection circuit 23 and the symbol phase selection circuit 37. The clock phase error detection circuit 23 determines the clock pull-in phase, supplies the clock phase error signal to the LPF 26, and supplies the symbol phase selection circuit 37 with the symbol phase for phase detection and data reproduction.

FIG. 2 shows an example of the configuration of the clock phase error detection circuit 23 and the symbol phase selection circuit 37, and I output from the complex multiplication circuit 22 as in the example shown in FIG.
The signal and the Q signal are the phase error signal detection circuit 511 and
And the zero cross decision circuit 513 and
This is distributed to the 514 and this zero-cross judgment circuit
I signal and Q output from 513 and 514, respectively
The zero-cross judgment signal of the signal is the effective phase error judgment circuit 518
Is supplied to. Then, this effective phase error determination circuit 518
Is supplied with a demodulation method switching signal for selecting one of the QPSK and OQPSK demodulation methods.

The effective phase error judgment circuit 518 supplies a control signal for selecting a phase error signal from the zero-cross judgment result according to the selected demodulation method to the selection circuit 515, and for phase detection and data reproduction. A control signal for selecting the phase is supplied to the symbol phase selection circuit 37.

The symbol phase control signal derived from the effective phase error determination circuit 518 controls the switches 521 and 522 which form the symbol phase selection circuit 37, respectively. The switches 521 and 522 have I and Q signals, respectively.
The signals are combined and these switches 521 and
One fixed terminal of 522 is connected to T / 2 delay circuits 523 and 524, respectively, and the other fixed terminal is connected to this T2.
The output signals of the T / 2 delay circuits 523 and 524 are connected to the output terminals of the / 2 delay circuits 523 and 524, respectively, and the output signals of the T / 2 delay circuits 523 and 524 are supplied to the data reproduction circuit 24 and the phase detection circuit 25, respectively.

FIG. 3 shows a concrete circuit example of the effective phase error discriminating circuit 518.
514 The output signals a and b from each are R
It is supplied to the set terminal and the reset terminal of the S flip-flop circuit 531. Further, these input signals a and b are supplied to the OR circuit 532, and the output from the OR circuit 532 is supplied to one terminal of the AND circuit 533. The output signal of the flip-flop circuit 531 is smoothed by the LPF 534, and the output signal from the LPF 534 is input to the other terminal of the AND circuit 533, and further, through the inverter 535, to the AND circuit 536 together with the output from the OR circuit 532. input.

Then, the input signal a is sent to the first of the switch 537.
This switch 537 is connected to the fixed terminal of
Supply the output signal from the AND circuit 533 to the fixed terminal of
Further, the input signal b is supplied to the first fixed terminal of the switch 538, and the AND circuit is supplied to the second fixed terminal of the switch 538.
Connect the output signal from 536. Then, signals A and B for phase selection from these switches 538 and 539.
Is output.

The output signal from the LPF 534 is connected to the second fixed terminals of the switches 539 and 540, respectively, and is fixedly fixed to the first fixed terminals of the switches 539 and 540, respectively. A high level “H” signal and a low level “L” signal are supplied. These switches 539 and 540 output signals C and D for symbol phase selection.

Then, these switches 537-540 have Q
It is controlled by a PSK or OQPSK demodulation method switching signal, and when the QPSK modulation method is selected, it is controlled so that the first fixed terminal side is selected as shown in the figure.

Table 1 below shows the relationship between the outputs of the switches 537 and 538 and the output of the selection circuit 515, and Table 2 below shows the relationship between the outputs of the switches 539 and 540 and the operation of the symbol phase selection circuit 37. ing.

[0039]

[Table 1]

[Table 2] Next, the operations of the clock phase error detection circuit 23 and the symbol phase selection circuit 37 will be described. First, when demodulating a QPSK modulated signal, the switches 537 to 540 are selected (on the state shown in the figure) on the first fixed terminal side. . switch
Since the first fixed terminals of 539 and 540 are fixedly set to the “H” and “L” levels, respectively, in the symbol phase selection circuit 37 shown in FIG. Connected and switch 522 is connected to the bottom.

Further, the switch 537 is a zero cross determination circuit.
The output from 513 is fed to the selection circuit 515 and the switch 538
Supplies the output from the zero-cross determination circuit 514 to the selection circuit 515, which detects the clock phase error for QPSK demodulation. The symbol phase selection circuit 37 outputs the input I signal and Q signal as they are, so that the phase detection circuit 25 and the data recovery circuit 24 operate at the symbol phase of QPSK, respectively.

The case of demodulating an OQPSK signal will be described with reference to FIG. 4, which shows the constellation and eye pattern of the OQPSK signal.
When demodulating a signal, the switches 537 to 540 are turned on to the second fixed terminal side on the lower side, contrary to the state shown in FIG. Therefore, the outputs from the AND circuits 533 and 536 are supplied to the selection circuit 515. The output from the LPF 534 is the switches 521 and 52 of the symbol phase selection circuit 37.
It comes to control 2.

First, when the carrier phase is in the state of "0 °" shown in FIG. 4A, the clock pull-in phase is I
The symbol phase is I
The eye convergence phase of the signal. In order to synchronize the phase of the clock with the clock pull-in phase, the phase error signal detected from the I signal which is zero-crossing at this phase may be used.

In order to perform clock control using the phase error signal detected from the I signal as described above, a zero cross determination circuit is used.
Since the Q signal is not zero-crossing when the I signal from which the determination output is obtained from 513 is zero-crossing, the zero-cross determination circuit 514 determines that it is not zero-crossing. Therefore, in this state, the output from the zero-cross determination circuit 513 causes the flip-flop circuit of FIG.
531 is set. Therefore, the flip-flop circuit 531 outputs an "H" level signal representing that the I signal is zero-crossing in the clock pull-in phase.

The LPF 534 eliminates the erroneous determination of the flip-flop circuit 531 due to noise or the like, and through the AND circuits 533 and 536,
A control signal for instructing the selection circuit 515 to select the phase error signal output from the phase error signal detection circuit 511 is supplied to the selection circuit 515.

In this case, since the eye convergence phase of the Q signal is shifted by T / 2 from the symbol phase, the switches 539 and 54
The switches 521 and 522 are controlled to be connected to the upper side via 0, respectively, and the symbol phase is selected so that only the Q signal is delayed by T / 2. By controlling in this way, the phase detection and the data reproduction are performed using the data of the eye convergence phase for both the I signal and the Q signal.

Next, description will be made regarding the case where the carrier phase turns 90 ° and becomes as shown in FIG. 4B. When the clock pull-in phase fluctuates, the clock cannot be reproduced, so that the clock pull-in phase is as shown in FIG. Indicated by 0
Must be in phase with °.

It is the zero-crossing Q signal that can detect the phase error signal that can pull in this phase. Therefore, if the phase error signal detected from the Q signal is used for clock control, clock reproduction can be performed. At this time, the I signal is not zero-crossed, so the zero-cross determination circuit 513 determines that it is not zero-crossed, but the zero-cross determination circuit 514 determines that it is zero-crossed, so the flip-flop circuit 531
Is set to reset, this flip-flop circuit 531
Outputs an "L" level signal representing that the Q signal is zero-crossing in the clock pull-in phase.

The output from the flip-flop circuit 531 is supplied to the phase error signal detection circuit 512 to the selection circuit 515 via the AND circuits 533 and 536 via the LPF 534.
This selection circuit 515 selects the detection signal from
To supply a control signal to the.

Further, since the eye convergence phase of the I signal is shifted by T / 2 from the symbol phase, the switches 521 and 521 of the symbol phase selection circuit 37 are switched through the switches 539 and 540.
522 is controlled to be connected to the lower side, and the symbol phase is controlled so that only the I signal is delayed by T / 2.
Therefore, by controlling in this way, it is possible to perform the phase detection and the data reproduction by using the data of the eye convergence phase for both the I signal and the Q signal.

In the above description, either the I signal or the Q signal is zero-crossed, but the I signal and the Q signal are not zero-crossed when the carrier phase is around 45 ° or depending on the symbol pattern. There are cases. In the effective error determination circuit 518 of FIG. 3, the OR circuit 532 detects a case where neither the I signal nor the Q signal is zero-crossed. The output from the OR circuit 532 controls the AND circuits 533 and 536 to control the control signal supplied to the selection circuit 515. The output of the T delay circuit 517, which is the phase error signal one symbol period before, is output. Selective output is enabled.

As described above, every time the carrier phase is rotated by 90 °, the phase error signal to be used can be switched from the zero-cross determination result, so that the clock pull-in phase can be kept constant and a stable clock can be obtained. Playback can be performed.

Next, an embodiment for automatically determining the modulation method will be described. FIG. 5 shows the configuration of the clock phase error detection circuit 23 in the case of automatically determining the modulation method, which is basically the same as the circuit shown in FIG. Is provided, and the output from the determination circuit 519 is supplied to the effective phase error determination circuit 518 as a modulation system switching signal.

The detection signals from the zero-cross determination circuits 513 and 514 are guided to the modulation system determination circuit 519, which is either a QPSK signal or an OQPSK signal based on the zero-cross determination result of the I signal and the Q signal. Determine if there is. Then, this determination result is supplied to the effective phase error determination circuit 518 as a demodulation method switching signal.

FIG. 6A shows this modulation system judgment circuit 51.
9 shows an example of the configuration of the AND circuit in which the output signals from the zero-cross determination circuits 513 and 514 are supplied.
The AND circuit 551 determines whether or not the I signal and the Q signal are zero-crossed at the same time. The output from the AND circuit 551 is supplied to the zero-cross occurrence frequency determination circuit 552, and the frequency at which the I signal and the Q signal simultaneously zero-cross is measured.

As shown in FIG. 11, the QPSK signal is I
The signal and the Q signal have the same zero-crossing phase. The probability that the I signal or the Q signal zero-crosses is "1/2" because it is the probability that the symbol changes. Therefore, the probability that the I signal and the Q signal zero-cross at the same time is "1/4".

On the other hand, in the OQPSK signal, the zero crossing positions of the I signal and the Q signal are different as shown in FIG. 13, so the probability that the I signal and the Q signal are zero crossed at the same time is "0". Therefore, in the zero-cross frequency determination circuit 552, the probability of zero-cross is "1 /
It is determined whether it is about 4 "or almost" 0 ", and it is possible to determine and output whether the input signal is a QPSK signal or an OQPSK signal.

For example, when the probability that the I signal and the Q signal simultaneously zero-cross is larger than "1/8", QPSK
If an output that is judged as a signal is obtained, and if it is smaller than "1/8", it is judged that the OQPSK signal is input.

FIG. 7 shows the configuration of the clock phase error detector of the apparatus according to another embodiment. In this embodiment, the case of the OQPSK signal is shown. In this embodiment, the first and second clock phase error detection circuits 231
And 232 for these phase error detection circuits
Both 231 and 232 have the same configuration as the clock phase error detection circuit 23 shown in FIG.

That is, the phase error signal detection circuits 5111 and 5121 and the zero-cross determination circuit 51 to which the I signal is respectively supplied.
31 and 5141 are provided, and phase error signal detection circuits 5112 and 5122 and zero cross determination circuits 5132 and 51 to which the Q signal is supplied are provided.
With 42. Further, selection circuits 5151 and 5152 are provided, and averaging circuits 5161 and 5162 and a delay circuit 51 are provided.
71 and 5172 are provided, and the phase error signal output is obtained from each of the selection circuits 5151 and 5152 and supplied to the selection circuit 45. Then, the zero-cross determination circuits 5131, 5132, 51
The output from each of 41 and 5142 is the effective phase error judgment circuit 46.
To control the selection circuit 45 based on the output.

Here, the phase error signal detection circuit 5122 and the zero-cross determination circuit 5142 pass the I signal to the T / 2 delay circuit.
The Q signal is supplied to the phase error signal detection circuit 5121 and the zero-cross determination circuit 5141 via the T / 2 delay circuit 48.
Supply through.

Assuming that the clock pull-in phase in FIG. 4A is the zero-cross phase of the I signal, the zero-cross determination and phase error detection in the clock phase error detection circuit 231 are the same as the zero-cross phase of the I signal and T.
This is the zero-cross phase of the Q signal before / 2 symbols, and the phase for performing the zero-cross determination and the phase error detection in the clock phase error detection circuit 232 is the eye convergence phase of the Q signal and the I convergence phase of the I signal before T / 2 symbols. Because
The clock phase error detection circuit 231 detects the phase error signal.

The phase error signal detected by the clock phase error detection circuit 231 is supplied to the selection circuit 45, and the zero-cross judgment result is supplied to the effective phase error judgment circuit 46. At this time, the effective phase error determination circuit 46 outputs a control signal so that the selection circuit 45 selects the phase error signal detected by the clock phase error detection circuit 231. This control signal is also supplied to the symbol phase selection circuit.

If the carrier is rotated by 90 ° and the clock pull-in phase is the zero-cross phase of the Q signal shown in FIG. 4B, the clock phase error detection circuit 231 carries out the zero-cross determination and the phase error detection. Phase is I
The eye-convergence phase of the signal and the eye-convergence phase of the Q signal before T / 2 symbols. The phase at which the clock phase error detection circuit 232 performs zero-cross determination and phase error detection are the zero-cross phase of the Q signal and the T / 2 symbol. The phase error signal is detected in the phase error detection circuit 232 because it is the zero-cross phase of the previous I signal.

The phase error signal detected by the clock phase error detection circuit 232 is supplied to the selection circuit 45, and the zero-cross judgment result is supplied to the effective phase error judgment circuit 46. At this time, the effective phase error determination circuit 46 outputs a control signal so that the selection circuit 45 selects the phase error signal detected by the clock phase error detection circuit 232.
Therefore, the phase error signal can be detected from both the I signal and the Q signal.

FIG. 6B shows a concrete configuration example of the effective phase error determination circuit 46. The OR circuit 461 includes the determination results of the zero cross determination circuits 5131 and 5141 of the clock phase error detection circuit 231. The RS flip-flop circuit 462 is set when the clock signal is supplied and the I-phase signal or the Q-signal crosses zero at the zero-cross determination phase in the clock phase error detection circuit 231.

Further, the OR circuit 463 is supplied with the judgment outputs from the zero-cross judgment circuits 5132 and 5142 of the clock phase error detection circuit 232.
The RS flip-flop circuit 462 is reset when either the I signal or the Q signal is zero-crossed in the zero-crossing determination phase in. The output signal from the flip-flop circuit 462 is smoothed by the LPF 464 and used as a control signal for the selection circuit 45 and the symbol phase selection circuit.

In the above description, the OQPSK signal is used, but the embodiment is still effective as long as it is a modulated signal in which the symbol change points of the I signal and the Q signal are offset by T / 2 symbols.

[0068]

As described above, according to the present invention, the OQP
When demodulating the SK signal, the clock pull-in phase can be kept constant even when the carrier is asynchronous.
Therefore, a demodulation circuit capable of clock phase synchronization at a high speed and in a stable state is provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating a demodulation device using a clock phase error detection circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a clock phase error detection circuit and a symbol phase selection circuit in the above embodiment.

FIG. 3 is a configuration diagram illustrating an effective phase error determination circuit that constitutes the clock phase error detection circuit.

FIG. 4 is a diagram showing an OQPSK signal constellation and an eye pattern for explaining the operation of the clock phase error detection circuit.

FIG. 5 is a configuration diagram illustrating another example of a clock phase error detection circuit.

FIG. 6A is a diagram illustrating a modulation system determination circuit,
FIG. 6B is a diagram showing an example of an effective phase error determination circuit.

FIG. 7 is a configuration diagram illustrating still another example of the clock phase error detection circuit.

FIG. 8 is a configuration diagram illustrating a conventional QPSK signal demodulation circuit.

FIG. 9 is a configuration diagram showing a clock phase error detection circuit in the QPSK demodulation circuit.

FIG. 10 is a diagram illustrating a clock phase error detection method by zero-cross control.

FIG. 11 is a diagram showing a constellation of a QPSK signal and an eye pattern.

FIG. 12 is a configuration diagram illustrating a conventional QPSK and OQPSK demodulation circuit.

FIG. 13 is a diagram showing a constellation and an eye pattern of an OQPSK signal for explaining the problems of the clock recovery circuit in the conventional OQPSK demodulation circuit.

[Explanation of symbols]

12 ... In-phase detection circuit, 13 ... Quadrature detection circuit, 14 ... First local oscillator, 15 ... Distributor, 16 ... Phase shifter, 17, 18 ... A / D converter, 19, 22 ... Complex multiplication circuit, 20 , 21 ... Digital filter, 23 ... Clock phase error detection circuit, 24 ... Data recovery circuit, 25 ... Phase detection circuit, 37 ... Symbol phase selection circuit, 51
1, 512 ... Phase error determination circuit, 513, 514 ... Zero cross determination circuit, 515 ... Selection circuit, 516 ... Average circuit, 517 ...
T delay circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Noboru 3-9 Shinbashi, Minato-ku, Tokyo 3-9 Toshiba Toshiba Abu E Co., Ltd.

Claims (4)

[Claims] 1. A means for regenerating a clock synchronized with a predetermined phase from an in-phase axis detection output and a quadrature axis detection output in a quadrature detection output which is a pulse code signal subjected to band limitation, at a predetermined timing of the clock. First phase error detection means for detecting a phase error from the sampled in-phase axis detection output, and second phase error detection for detecting a phase error from the quadrature axis detection output sampled at a predetermined timing of the clock. Means, first zero-cross determination means for determining that the in-phase detection output has a specific change between two samples before and after the predetermined timing, and the quadrature detection output has at least the predetermined timing. And a second zero-cross determination means for determining that the code has a specific change between two samples before and after At least an output of the first zero-cross determination means and an output of the second zero-cross determination means, an effective phase error determination means for determining a phase error signal effective for clock phase control, and an output from the effective phase error determination means. Therefore, the demodulator of the phase modulated wave signal, further comprising: selecting means for selecting a phase error signal effective for clock phase control, wherein the clock phase is controlled according to the effective phase error signal. . 2. The effective phase error determination means is the first
2. The demodulator for a phase-modulated wave signal according to claim 1, wherein the detection output from which the zero-cross determination output of the second zero-cross determination means is obtained is determined to be a valid phase error signal. 3. Modulation method determination means for determining the modulation method of the band-limited pulse code signal based on the output from the first zero-cross determination means and the output from the second zero-cross determination means. 2. The demodulator for phase-modulated wave signal according to claim 1, further comprising: a control means for controlling the effective phase error determination means according to a determination result of the modulation method determination means. 4. The modulation method determination means outputs the pulse-coded signal subjected to the band limitation by the probability that the output from the first zero-cross determination means and the output from the second zero-cross determination means become true at the same time. The demodulator of a phase modulated wave signal according to claim 3, wherein the modulation method is determined.