JPH06268699A - Clock phase controller - Google Patents

Abstract

PURPOSE:To speedily obtain a phase pull-in operation, to have stability in a phase pull-in state and to cope with the change of the kind of a modulated signal as well. CONSTITUTION:The digital modulated signal converted to a base band signal by a multiplier 12 is digitized by an A/D converter 16 and sent to a data reproducing part 26 but the phase control of a sampling clock used in the A/D converter 16 is performed as follows. A zero cross detection part 17 detects the zero cross point of a digital output and an error signal at the time is passed through a selecting circuit 18 and an adder 24 and turned to the control signal of a VCO 26. On the other hand, this error signal is integrated by an integrator 19, the integrated output is compared with a prescribed value by a comparator 20, the compared result is periodically latched by a latch circuit 21, and the latched output is passed through an integrator 22 and the adder 24 and turned to the control signal of this VCO 26. The output of the VCO 26 is passed through a frequency divider 27 and used as the sampling clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase control device used in a device for receiving and demodulating a digitally modulated signal.

[0002]

2. Description of the Related Art As a digital data transmission method in the field of microwave terrestrial communication or satellite communication, for example, phase modulation (P
SK), quadrature amplitude modulation (QAM), etc. The receiving device that demodulates the signal transmitted by digital data uses the synchronous detection method, which extracts the carrier wave component from the modulated wave itself and reproduces the carrier wave, and uses this to demodulate the modulated wave to a baseband signal. is doing. In addition, in order to reproduce data from the demodulated baseband signal, clock reproduction is performed using the characteristics of phase modulation (data exists at a specific phase position), and the baseband signal is sampled and digitized. ing.

In clock recovery, a phase synchronization circuit is used to perform clock recovery. However, if the clock phase shifts, accurate data sampling cannot be performed. Therefore, a system for artificially adjusting the phase of the clock or a system for automatically adjusting the phase has been considered (for example, Japanese Patent Publication No. 3-23021).

[0004]

However, the conventional system is a method of performing a predetermined logical operation on reproduced data to obtain phase correction data. For this,
Since it is a method of performing a system logical operation using reproduced data, there is a problem that it is not flexible depending on the type of modulation signal {multilevel (binary, quaternary, etc.) modulated signal}. Further, during the transition period of phase pull-in, the calculation result changes a lot and the clock phase is controlled by the phase shifter, so the adjustment range is narrow and it may take time to reach a stable state. . Furthermore, in the phase pull-in state,
When noise or the like is mixed, a large amount of phase correction data may be output suddenly and the phase pull-in state may become unstable. Moreover, the phase shift of the sampling clock may occur suddenly.

Therefore, according to the present invention, the phase pull-in operation can be quickly obtained, and there is stability in the phase pull-in state.
Moreover, it is an object of the present invention to provide a clock phase control device capable of coping with a change in the type of a modulation signal.

[0006]

SUMMARY OF THE INVENTION According to the present invention, demodulation means for demodulating a digitally modulated signal into a baseband signal, sampling means for sampling the baseband signal, and digital data using the output of the sampling means. In a receiving device including a data reproducing unit for reproducing the data, an error extracting unit that detects a zero-cross point of the sampling output of the sampling unit and extracts the sampling output at this time as an error signal, and a sampling clock of the sampling unit. And a variable voltage controlled oscillation means for controlling the frequency and phase of the sampling clock based on the output of the error extraction means.

[0007]

According to the above-mentioned means, only the zero-cross point is detected, and any multi-valued signal can detect an error. Further, since the variable voltage controlled oscillator is controlled by the error signal to control the phase of the sampling clock, the control range is wide and stable.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, the digital modulation signal is input to the input terminal 11 and is input to the multiplier 12 (synchronous detection unit). Multiplier 1
The carrier from the carrier reproducing unit 13 is supplied to the line 2, where the synchronous detection is performed. The baseband signal output from the multiplier 12 is a low pass filter (LP
F) 14 and a buffer amplifier 15 are input to an analog-digital (A / D) converter 16. The oscillation output of the voltage controlled oscillator (VCO) 26 is frequency-divided by the frequency divider 27 and supplied to the A / D converter 16 as a sampling clock. As a result, from the A / D converter 16,
A digital output obtained by digitizing the baseband signal is obtained. This digital output is input to the data reproduction circuit 26, where multi-valued data is reproduced.

Further, the output of the A / D converter 16 is introduced into a control loop for adjusting the phase of the sampling clock. That is, the output of the A / D converter 16 is input to the zero-cross detector 17, the integrator 19, and the selection circuit 18.

The zero-cross detection section 17 detects the zero-cross time point of the digital output, and the detection signal at this time is detected by the integrator 1.
9, the coefficient unit 23, and the control terminal of the selection circuit 18 are supplied. The integrator 19 outputs A / when the zero-cross detection signal is input.
The output (error component) of the D converter 16 is captured and integrated. When the zero-cross detection signal is input, the selection circuit 18 passes the output (error component) of the A / D converter 16 and gives it to the adder 24. Further, the coefficient unit 23 counts the zero-cross detection signal, and when it reaches a predetermined value, resets the integrator 19 and gives a latch pulse to the latch circuit 21.

The integrated output of the integrator 19 is input to the comparator 20 and compared with a predetermined value. The comparator 20 obtains the determination output when the integrated output becomes a predetermined value or more. This judgment output is latched and given to the integrator 22 in a constant cycle (every time the previous zero-cross detection signal reaches a predetermined value). This integrator 22 operates as a loop filter,
The output is input to the adder 24. Therefore adder 2
4 obtains the result of adding the output from the selection circuit 18 and the integrated output, and gives the result to the D / A converter 25. This D / A
The output of the converter 25 is used as the frequency and phase control signal of the voltage controlled oscillator 16.

As a result, when the sampling clock used in the A / D converter 16 has a phase error, this phase control is performed and the sampling clock is pulled into an appropriate sampling phase.

The operation of the above phase controller will be further described with reference to FIG. Now, the sampling clock is
As shown in (A), if it does not converge correctly, the zero-cross detection signal is obtained from the zero-cross detection unit 17. The zero-cross detector 17 has, for example, as shown in FIG. 3, a latch circuit that sequentially takes in two sampling data D1, D0, D2, and when the polarity of D1, D2 changes from + to − or − to +. It is determined that there was a zero cross. For example, in this embodiment, the fall (change from + to −) is detected. When the zero-cross detection signal is obtained, the timing-adjusted data D0 is fetched into the integrator 19 and the selection circuit 18 as an error signal. Further, the counter 23 counts up. As a result, the error signal is directly obtained from the selection circuit 18 and introduced into the adder 24. Therefore, when the phase of the sampling clock is greatly deviated, a large correction is performed at once. After that, the integrator 19, the comparator 20, the latch circuit 21, and the integrator 22 perform the correction by the fine adjustment loop. Selection circuit 1 in adder 24
In the case where the output holding function of 8 is not provided, this embodiment is sufficient, but when the holding function is provided, the switch 28 is controlled. The period during which the switch 28 is turned on is, for example, when the system is powered on or when the channel is switched. After the phase of the sampling clock is stabilized, the switch 28 is turned off so that only the fine adjustment loop operates. In this embodiment, when the value of the error signal is large, it operates so as to advance the phase of the sampling clock, and when the value of the error signal is small, it operates so as to delay the phase of the sampling clock. The sampling rate for sampling the sampling data D1, D0, D2 is an integral multiple of the symbol rate.

The phase of the sampling clock is controlled in this way, and when the sampling clock phase becomes an appropriate phase as shown in FIG. 2B, the zero-cross detector 1
Since 7 does not obtain the zero-cross detection signal, its control state is maintained. The zero-cross detector 17 always detects a zero-cross, but as long as the sampling clock has an appropriate phase, the error signal at this time is 0,
The value of the control signal to the voltage controlled oscillator 16 does not change.

According to the above-described embodiment, only the zero-cross point is detected, and error detection is possible with any multilevel signal. Further, since the variable voltage controlled oscillator is controlled by the error signal to control the phase of the sampling clock, the control range is wide and stable. Further, even if there is noise or the like in a stable operation state and an error signal is temporarily detected, the loop of the integrator 19, the comparator 20, the latch circuit 21, and the integrator 22 causes the phase control to be performed rapidly. It is highly stable. Further, in this system, even when the phase of the sampling clock is deviated due to aging or the like, the voltage controlled oscillator 1
Since 6 is controlled, the reliability in maintaining the performance is high.

The present invention is not limited to the above embodiment. For example, as shown in FIG. 4, a data converter 32 may be provided between the selection circuit 18 and the adder 24. Then, the data conversion operation is configured to be switched by the mode signal. By doing so, it is possible to switch the data conversion operation in accordance with, for example, a mode signal and to randomly control the sampling clock phase at the time of broadcasting such as pay broadcasting for a particular audience. Then, only the user who can obtain a normal mode signal can obtain normal data reproduction. That is, the scramble function can be obtained.

[0018]

As described above, according to the present invention,
It is possible to obtain a highly reliable clock phase control in which the phase pull-in operation can be quickly obtained, which is stable in the phase pull-in state, and which can respond even when the type of the modulation signal changes.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a sampling phase shown for explaining an operation example of the device of the present invention.

FIG. 3 is an explanatory diagram of sampling data shown for explaining an operation example of the zero-cross detection unit of FIG. 1.

FIG. 4 is a diagram showing an application example of the present invention.

[Explanation of symbols]

12 ... Multiplier, 13 ... Carrier recovery unit, 14 ... Low-pass filter, 15 ... Buffer amplifier, 16 ... A / D converter, 17 ... Zero cross detection unit, 18 ... Sorting circuit, 19 ...
Integrator, 20 ... comparator, 21 ... latch circuit, 22 ... integrator, 23 ... counter, 24 ... adder, 25 ... D / A converter, 26 ... voltage controlled oscillator, 27 ... frequency divider, 28 ... switch.

Claims (2)

[Claims] 1. Demodulating means for demodulating a digitally modulated signal into a baseband signal, sampling means for sampling the baseband signal, and data reproducing means for reproducing digital data using the output of the sampling means. In the receiving device comprising: detecting a zero-cross point of the sampling output of the sampling means, an error extracting means for extracting the sampling output at this time as an error signal, and generating a sampling clock used in the sampling means, A clock phase control device comprising: a variable voltage control oscillating means for controlling the frequency and phase of the sampling clock based on the output of the error extracting means. 2. The error extraction means integrates the sampling output at the time of detecting the zero-cross point a predetermined number of times, and derives the output as a first error signal when the integrated output is at a predetermined level or more, Means for directly deriving the sampling output at the time of detecting the zero-cross point to obtain a second error signal; and means for adding the first and second error signals to obtain a control signal for the variable voltage control oscillation means. The clock phase control device according to claim 1, further comprising: