JP3442655B2 - Carrier recovery circuit and carrier recovery method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit used for synchronous demodulation of digital modulated waves, and more particularly to a carrier recovery circuit having a frequency control loop and a phase locked loop and a carrier recovery method.

[0002]

2. Description of the Related Art In digital communication or digital broadcasting, when demodulating a digital modulated wave such as a QPSK (4-phase phase shift keying) modulated wave on the receiving side, when synchronous demodulation is performed, demodulated data is obtained more than in the case of asynchronous demodulation. It is known that the error rate of can be reduced. At the time of synchronous demodulation, it is necessary to recover a carrier wave synchronized with the input modulated wave.

FIG. 5 of JP-A-6-78009 discloses that
The basic structure of a carrier recovery circuit used for synchronous demodulation of such a digital modulated wave is shown. In this carrier recovery circuit, a frequency control loop (AFC loop)
AF using both the phase-locked loop (PLL loop)
After the frequency error is removed by the operation of the C loop so that the frequency of the reproduced carrier falls within the phase pull-in range of the PLL loop, the phase error of the reproduced carrier is removed by the PLL loop, and the reproduced carrier with respect to the input modulated wave. Synchronize the phases. This series of operations is carrier wave reproduction.

In this carrier recovery circuit, the frequency error of the reproduced carrier cannot be accurately detected in a situation where the reception condition is poor due to co-channel interference or the like, and the frequency error cannot be sufficiently removed by the operation of the AFC loop. ,
There is a problem that the carrier wave reproduction cannot be performed correctly.

That is, for example, when FM interference due to co-channel interference occurs, the data symbols are not fixed at one point in the constellation of the demodulated data of the digital modulation wave, and the data symbols rotate around a relatively large circumference as a locus. Therefore, the frequency error of the reproduced carrier signal cannot be detected correctly. As a result, the AFC loop cannot suppress the frequency error to the extent that it falls within the pull-in range of the PLL, making phase synchronization by the PLL difficult.
It becomes impossible to obtain a reproduced carrier wave that is synchronized with the input digital modulated wave.

[0006]

As mentioned above, the AFC
In the conventional carrier recovery circuit that removes the frequency error of the reproduced carrier by the operation until the frequency of the reproduced carrier falls within the pull-in range of the PLL loop, and then the phase error of the reproduced carrier is removed by the PLL loop, due to co-channel interference, etc. When the reception condition is poor, the frequency error of the reproduced carrier cannot be correctly detected, and the frequency error cannot be sufficiently removed by the AFC operation, which makes it difficult to reproduce the carrier.

The present invention solves these problems and provides a carrier wave reproducing circuit and a carrier wave reproducing method that enable good carrier wave reproduction even in a situation where the input digital modulated wave is poorly received. To aim.

[0008]

[Means for Solving the Problems ]
Therefore, the present invention reproduces and carries an input digital modulated wave.
Frequency conversion signal by converting the frequency using the wave signal.
Frequency conversion means for generating a signal, and the frequency conversion signal
Low-frequency suppressing means for suppressing low-frequency components, and the low-frequency suppressing means
Phase error of the frequency converted signal after suppression of low frequency components
The phase error detecting means for outputting and the phase error detecting means.
Frequency of the frequency converted signal from the detected phase error
Frequency error detecting means for detecting an error, and the frequency error
Control the frequency of the reproduced carrier signal so that
Frequency control means and the phase error detection means
Of the reproduced carrier signal so that the phase error generated is reduced.
Control the phase to synchronize the phase with the digital modulated wave.
Carrier wave reproduction characterized by comprising phase synchronization means
It is characterized by being a circuit. When the low-frequency component of the frequency-converted signal obtained by frequency-converting the digital modulated wave is suppressed in this way, interference such as co-channel interference received by the digital modulated wave, for example, FM interference components concentrated in the low frequency region is suppressed. To be done. Therefore, if the frequency error is detected from the frequency-converted signal after suppressing the low-frequency component, the frequency error of the reproduced carrier signal can be detected without being affected by such interference.

As a result, by the frequency control (AFC) operation based on the frequency error detection signal, the frequency error can be suppressed to such an extent that it falls within the pull-in range of the PLL loop for the phase synchronization control, and the reproduced carrier signal is surely obtained. It becomes possible to synchronize the phase with the digital modulation wave.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the configuration of a digital demodulating apparatus including a carrier recovery circuit according to a first embodiment of the present invention.

In FIG. 1, a QPSK modulated wave is input to the input terminal 1 as a digital modulated wave. This QPS
The K modulated wave is input to the in-phase detector 2 and the quadrature detector 3, and the output of the local oscillator 5 having a fixed frequency is passed through a distributor 4 including a 90 ° phase shifter to obtain a 0 ° phase and a 90 ° phase. Each is multiplied with the local oscillator signal.

The outputs of the in-phase detector 2 and the quadrature detector 3 are digitized by A / D converters 6 and 7, respectively. The outputs of the A / D converters 6 and 7 are input to the first complex multiplier 8 and are multiplied by the first reproduction carrier signal having the sine and cosine characteristics generated by the AFC loop described later to obtain the I signal. And a first frequency converted signal composed of the Q signal.

The first frequency conversion signal output from the first complex multiplier 8 is input to the digital low pass filters 9 and 10. The digital low-pass filters 9 and 10 have a transfer characteristic for preventing intersymbol interference in digital data transmission, and are generally designed to obtain a so-called roll-off characteristic when combined with a filter characteristic on the transmission side. There is. As a result, the first
The first frequency-converted signal from the complex multiplier 8 is subjected to spectrum shaping by the digital low-pass filters 9 and 10 so that the eye aperture ratio becomes sufficiently large.

Digital low-pass filters 9 and 10
Is output to the second complex multiplier 11 and is multiplied by the second reproduction carrier signal having the sine and cosine characteristics generated by the PLL loop described later to obtain a first signal composed of the I signal and the Q signal. 2 becomes the frequency converted signal. The second complex multiplier 11 realizes the same operation as the frequency converter in the intermediate frequency band in the baseband. That is, since the real number type multiplier cannot realize a negative frequency component and does not function as a frequency converter, a complex multiplier is used in this embodiment.

The second output from the second complex multiplier 11
The frequency converted signal is input to the clock recovery circuit 12, the data recovery circuit 13, the low frequency band suppression filters 16 and 17, and the amplitude distribution detection circuit 28. The clock reproduction circuit 12 reproduces the clock signal by extracting the symbol timing component in the second frequency conversion signal.

The reproduced clock signal is fed back to the A / D converters 9 and 10 as a conversion clock. The data reproduction circuit 13 discriminates and reproduces the second frequency-converted signal, binarizes it into I and Q signals, and outputs it to the output terminals 14 and 15 as I and Q demodulated data.

The low-pass suppression filters 16 and 17 have a second
Is a filter that suppresses the low-frequency component of the frequency-converted signal, and its output signal is input to the phase detector 18. The low pass suppression filters 16 and 17 will be described in detail later. The phase detector 18 performs phase detection of the second frequency-converted signal to detect its phase error, in other words, the phase error of the second reproduced carrier signal from the PLL loop described later.

The phase error signal output from the phase detector 18 is further input to the frequency detector 19, where the first
The frequency error of the first frequency-converted signal output from the complex multiplier 8 is detected, in other words, the frequency error of the first reproduced carrier signal from the AFC loop described later.

The frequency error signal output from the frequency detector 19 is input to the AFC loop filter 21 composed of a digital filter via the AFC loop opening / closing switch 20, where it is smoothed and then the numerically controlled oscillator 22.
Is supplied to the frequency control terminal of. Numerically controlled oscillator 22
Is a circuit whose output frequency is changed by a digital signal supplied to the frequency control terminal. That is, the numerically controlled oscillator 22 is composed of a cumulative addition circuit that does not prohibit overflow, and becomes an oscillating state by performing an adding operation up to its dynamic range according to the value of the control signal input to the frequency control terminal. Changes in accordance with the value of the control signal, V in the analog circuit
It operates like a CO (voltage controlled oscillator). Since the output of the numerically controlled oscillator 22 is a sawtooth signal, it is converted into a sine and cosine characteristic signal by the data converter 23 and becomes a first reproduction carrier signal. The data converter 23 is realized by, for example, a ROM.

Here, the first complex multiplier 8 to the digital low-pass filter 9 and the tenth second complex multiplier 11 are provided.
-Low-pass suppression filters 16 and 17-Phase detector 18-
Frequency detector 19-AFC loop open / close switch 20-A
The loop of the FC loop filter 21 to the numerical control oscillator 22 to the data converter 23 to the first complex multiplier 8 is AFC.
It constitutes a loop.

On the other hand, the phase error signal output from the phase detector 18 is passed through the PLL loop open / close switch 24 and a loop filter 25 for PLL which is a digital filter.
To the numerically controlled oscillator 2 after being smoothed here.
6 frequency control terminals. Numerically controlled oscillator 26
Is a circuit whose output frequency is changed by a digital signal supplied to the frequency control terminal, like the numerical controller 22 of the AFC loop. Since the output of the numerically controlled oscillator 26 is also a sawtooth signal, it is converted into a sine and cosine characteristic signal by the data converter 27 realized by, for example, a ROM, and becomes a second reproduced carrier wave signal.

Here, the second complex multiplier 11 to the low band suppression filters 16 and 17 to the phase detector 18 to the PLL loop open / close switch 24 to the PLL loop filter 25 to the numerically controlled oscillator 26 to the data converter 27 to the second. The loop of the complex multiplier 11 of 2 constitutes a PLL loop.

The amplitude distribution detection circuit 28 is a circuit that detects the amplitude distribution of the eye pattern of the second frequency conversion signal output from the second complex multiplier 11, and this detection signal is input to the synchronization determination circuit 29. To be done. The synchronization determination circuit 29
From the detection signal output from the amplitude distribution detection circuit 28, it is determined whether or not the carrier recovery circuit is in the synchronization established state. If it is in the synchronization established state, the synchronization state determination signal, if not in the synchronization established state, the asynchronous state determination signal. Each signal is supplied to the loop control circuit 30.

The loop control circuit 30 includes a synchronization determination circuit 29.
Is a circuit for controlling the AFC loop open / close switch 20 and the PLL loop open / close switch 24 in accordance with the synchronous state / asynchronous state determination signal supplied from the AFC loop open / close switch 20 and the PLL loop open / close switch 24. The PLL loops are sequentially operated, and when the synchronization state determination signal is supplied, the switch 20 is opened and the AF is performed.
It is configured to stop the operation of the C loop and leave the switch 24 closed to continue the operation of the PLL loop.

Next, the low band suppression filters 16 and 17 will be described. FIG. 2 shows the low-pass suppression filter 16 (1
It is a figure which shows the specific structural example of 7). This low-pass suppression filter is a 3-tap FIR filter. The input terminal 101 has a second output from the second complex multiplier 11 of FIG.
The frequency converted signal of is input. The second frequency-converted signal is input to the subtractor 106 via the delay element 102 as a center tap signal. The second frequency-converted signal input to the input terminal 101 and the signal obtained by further passing the output signal of the delay element 102 through the delay element 103 are added by the adder 1
It is added at 04. The output signal of the adder 104 is passed through the amplitude attenuator 105 having the attenuation rate of 1/8 and the subtractor 106, for example.
Is input as a correction signal to the center tap signal, and is subtracted from the center tap signal, and the output terminal 107 outputs a frequency signal in which the low-frequency component is suppressed. The frequency converted signal after suppression of the low frequency component is input to the phase detector 18 of FIG. A variable gain amplifier may be used as the amplitude attenuator 105.

FIG. 3 shows low-pass suppression filters 16 and 17.
FIG. 4 is a diagram for explaining the operation of, and shows the input / output frequency characteristics of the filters 16 and 17. When the second frequency multiplier signal shown in FIG. 3A is output from the second complex multiplier 11, the low-frequency suppression filters 16 and 17 output the low-frequency signals as shown in FIG. 3B or 3C. The component is suppressed.

FIG. 4 shows a constellation of I and Q demodulated data. FIG. 4A shows a case where the reception state is good, and the demodulated data symbols are located at one point in each quadrant. However, co-channel interference may occur in the digital modulated wave depending on the reception situation, and for example, in digital broadcasting, the FM modulated wave may be disturbed (this is called FM interference). In FM interference, the interference wave is concentrated in the low frequency range as shown by the broken line in FIG. When the interfering wave concentrated in the low frequency is mixed with the digital modulated wave, the constellation of the I and Q demodulated data is as shown in FIG.
The data symbols are not fixed at one point in each quadrant and rotate on a relatively large circumference.

When the digitally modulated wave receives such a large FM interference, the frequency error cannot be correctly detected by the frequency detector 17, and the frequency error cannot be sufficiently removed by the AFC loop. This point will be described with reference to FIG.

FIG. 5 is an enlarged view showing the rotation locus of the data symbol in one quadrant of FIG. 4B.
Increasing direction of the angle θ (counterclockwise) of the data symbol with the tangent line drawn from the origin 0 of the IQ plane toward the circumference of the rotation locus and the circumference as the reference angle with the data axis as the reference. The relationship between the time t ₊ when rotating to and the time t ₋ when rotating in the decreasing direction (clockwise) of θ is t ₊ > t ₋ .

That is, when there is no FM interference, the data symbols in each quadrant are located at one point, and the circumference of the rotation trajectory corresponds to an infinitesimal small value, so t ₊ = t ₋ , but when there is FM interference, t ₊ > T ₋ , which is the detection error of the frequency error in the frequency detector 17. When such a detection error of the frequency error occurs, the AFC loop cannot sufficiently suppress the frequency error. P in this state
Even if the LL loop is operated, the frequency error exceeds the pull-in range of the PLL loop, so that the phase locked state cannot be obtained.

On the other hand, the low-frequency components of the second frequency-converted signal are reduced by the low-frequency suppression filters 16 and 17 as shown in FIG.
When suppressed as in (b) or FIG. 3 (c), the constellation of the I and Q demodulated data becomes as shown in FIG. 4 (c), and the low frequency component of the interfering wave is generated together with the low frequency component of the modulated wave. Oppressed. That is, in FIG. 4C, the data symbol in each quadrant rotates along the rotation locus of the circumference smaller than that in the case of FIG. 4B, and comes closer to the state of t ₊ = t ₋ .

In FIG. 4 (c), the data symbols rotate on a plurality of circles in each quadrant, but this is caused by the low-pass suppression filters 16 and 17 in FIG. 3 (b) or FIG. 3 (c). By the suppression effect of low frequency components as shown in
This is because the same result as if the digitally modulated wave was subjected to ghost interference. However, if the degree of low-frequency suppression is small, there will be no problem in demodulation.

As described above, in the present embodiment, the low frequency components are suppressed by the low frequency suppression filters 16 and 17 with respect to the second frequency converted signal, and the reproduced carrier signal is converted from the frequency converted signal after the low frequency component suppression. The frequency error and the phase error are detected. As a result, the frequency error of the reproduced carrier signal can be accurately and easily detected even when the reception condition of the digital modulated wave is poor and co-channel interference, particularly FM interference occurs, and the reproduced carrier signal is reproduced by the AFC loop. The frequency error can be sufficiently suppressed to the extent that it falls within the pull-in range of the PLL loop. Therefore,
Even in a situation where there is such interference, phase synchronization by the PLL loop is possible, and the reproduced carrier signal can be reliably synchronized with the digital modulated wave.

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention.
3 is a block diagram showing a configuration of a digital demodulation device including a carrier wave recovery circuit according to the embodiment of FIG. The same parts as those in FIG. 1 are designated by the same reference numerals and the difference from the first embodiment will be described. In the present embodiment, instead of the low-pass suppression filters 16 and 17 in the first embodiment, filter characteristics (low It differs from the first embodiment in that low-pass suppression filters 31 and 32 having variable band suppression characteristics) are used, and switching control of the filter characteristics is performed based on a signal from an interference detection circuit 33.

FIG. 7 is a block diagram showing a specific structure of the low-frequency suppression filter 31 (32) in this embodiment. The input terminal 201 has the second complex multiplier 11 of FIG. The frequency converted signal of is input. The second frequency-converted signal is input to the subtractor 208 as a center tap signal via the delay element 202. The second frequency converted signal input to the input terminal 201 and the signal obtained by passing the output signal of the delay element 202 through the delay element 203 are added by the adder 204.

The output signal of the adder 204 is input to a plurality of amplitude attenuators having different attenuation ratios, for example, an amplitude attenuator 205 having an attenuation ratio of 1/8 and an amplitude attenuator 206 having an attenuation ratio of 1/4. . The filter characteristic switching signal from the interference detection circuit 33 of FIG. 6 is input to the other input terminal 209, and the selector 207 selects one of the outputs of the amplitude attenuators 205 and 206 according to the filter characteristic switching signal. Is output. The signal selected by the selector 207 is input to the subtractor 208 as a correction signal, and is subtracted from the signal of the center tap, and the output terminal 210 outputs a frequency signal in which low-frequency components are suppressed. The frequency converted signal after suppression of the low frequency component is input to the phase detector 18 of FIG.

Next, the interference detection circuit 33 will be described. The interference detection circuit 33 shown in FIG.
M interference is a circuit for detecting the interference state including the degree of interference. For example, by monitoring the fluctuation of the frequency error signal output from the frequency detector 19 of FIG. To detect.

The FM interference, which is a problem here, is concentrated in the low frequency component as described with reference to FIG. 3, but the FM modulated wave which is the interference wave is in the low frequency range due to its information content, for example, the picture pattern of the image. The concentrated component fluctuates, and this fluctuation directly appears as a fluctuation of the frequency error signal output from the frequency detector 19. Therefore, by monitoring the fluctuation of the frequency error signal by the interference detection circuit 33, it is possible to detect the FM interference state, that is, the presence or absence of the interference, and further the degree of the interference.

In the low-pass suppression filters 31 and 32, the selector 207 is controlled by the filter characteristic switching signal from the interference detection circuit 33, and when the FM interference is large, the output signal of the amplitude attenuator 206 having the larger attenuation ratio is selected. By doing so, the low-frequency suppression characteristic is strengthened, and when the FM interference is small, the output signal of the amplitude attenuator 205 having the smaller attenuation ratio is selected to weaken the low-frequency suppression characteristic. Here, the selector 208 is the amplitude attenuator 205.
The filter characteristics when selecting the output signal of FIG.
If it is (b), the filter characteristic when the output signal of the amplitude attenuator 206 is selected is, for example, FIG. 3 (c).

As described above, according to this embodiment, the filter characteristics (low-frequency suppression characteristics) of the low-frequency suppression filters 31 and 32 are adaptively switched according to the interference state (size), and low-frequency suppression is performed when the interference is large. The characteristics can be strengthened to facilitate the detection of frequency errors, and when the interference is small, the low-frequency suppression characteristics can be weakened to avoid the adverse effects of excessive suppression of low-frequency components.

Further, as shown by the broken line in FIG.
A path for directly inputting the output signal of No. 4 to the selector 208 is added, and when the interference is not detected by the interference detection circuit 33, that is, there is no interference or there is no problem even if there is any interference. In this case, the output signal of the adder 204 may be selected by the selector 208 so that the low-frequency component is not suppressed, whereby the adverse effect of the unnecessary suppression operation of the low-frequency component can be suppressed more effectively. be able to.

Further, in the present embodiment, the characteristics of the low-frequency suppression filters 31 and 32 are switched to two levels (three levels including the suppression of low-frequency components), but the characteristics may be switched to multiple levels. Of course, it is also good.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
3 is a block diagram showing a configuration of a digital demodulation device including a carrier wave recovery circuit according to the embodiment of FIG. The same parts as those in FIG. 6 are designated by the same reference numerals, and the difference from the second embodiment will be described. In the present embodiment, the function of the disturbance detection circuit 33 in FIG. 6 is included in the loop control circuit 30. The interference state is detected from the operating states of the AFC route and the PLL loop by 30 and the filter characteristics (low frequency suppression characteristics) of the low-frequency suppression filters 31 and 32 are switched based on the detected interference condition. The specific configurations of the low-pass suppression filters 31 and 32 are similar to those of the second embodiment, and are as shown in FIG. 7, for example.

That is, in the present embodiment, the AF is first performed with the loop control circuit 30 setting the characteristics of the low-pass suppression filters 31 and 32 to the characteristics shown in FIG. 3B, for example.
The C open / close switch 20 and the PLL loop open / close switch 24 are sequentially closed, and the AFC loop and the PLL loop are sequentially operated. When the synchronization determination circuit 29 determines that the phase synchronization has been established by this operation, the loop control circuit 30 holds the characteristics of the low-frequency suppression filters 31 and 32 as they are.

On the other hand, as a result of the AFC loop and the PLL loop operating in sequence, when the synchronization determination circuit 29 determines that the phase synchronization is not established, the loop control circuit 30 determines the characteristics of the low-frequency suppression filters 31 and 32, for example. Figure 3
After switching to the characteristic of (c), the AFC open / close switch 20 and the PLL loop open / close switch 24 are sequentially closed again, and the AFC loop and the PLL loop operate.

As described above, instead of detecting the occurrence of interference such as FM interference as in the second embodiment, when the AFC loop and the PLL loop are operated, for example, when both loops are not operated, the synchronization is not established. Even if it is determined that interference such as FM interference is occurring and the filter characteristics of the low-frequency suppression filters 31 and 32 are controlled, the same effect as in the second embodiment can be obtained.

The present invention is not limited to the above-described embodiment, and various modifications can be carried out without departing from the scope of the invention. For example, the above-mentioned first to first
In the third embodiment, the DS related processing, that is, at least the low-pass suppression filter processing,
It can also be realized by software such as P or CPU.

[0048]

As described above, according to the present invention, the signal in which the low frequency component of the frequency conversion signal is suppressed even when the reception condition of the digital modulated wave is bad and the FM interference due to the co-channel interference occurs. The frequency error can be correctly detected by detecting the frequency error of the reproduced carrier signal based on the above, and the frequency error can be sufficiently suppressed by the AFC loop to the extent that it falls within the pull-in range of the PLL loop. Therefore, even under such a bad reception condition in which interference occurs, phase synchronization by the PLL loop is possible, and the reproduced carrier signal can be reliably synchronized with the digital modulated wave.

Further, the characteristic of the low-frequency suppression filter for suppressing the low-frequency component is made variable, and the characteristic is controlled according to the state of the interference of the digital modulation wave, so that the low-frequency suppression characteristic is improved when the interference is large. By strengthening, it is possible to easily detect the frequency error, and when the disturbance is small, weaken the low-frequency suppression characteristic to avoid the adverse effect of excessive suppression of the low-frequency component, and further, the interference is not detected by the interference detection circuit, There is no interference,
Alternatively, when it is small enough not to cause a problem, it is possible to avoid the adverse effect of the unnecessary suppression operation of the low frequency component by prohibiting the suppression operation of the low frequency component.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital demodulation device including a carrier recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a low-pass suppression filter according to the same embodiment.

FIG. 3 is a diagram showing frequency characteristics for explaining the operation of the low-pass suppression filter according to the first embodiment.

FIG. 4 is a diagram showing a constellation of I and Q demodulated data for explaining the operation of the low-frequency suppression filter in the same embodiment.

FIG. 5 is an enlarged view showing a part of a constellation of I and Q demodulated data when a digital modulated wave receives FM interference.

FIG. 6 is a block diagram showing the configuration of a digital demodulation device including a carrier recovery circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a low-pass suppression filter in the same embodiment.

FIG. 8 is a block diagram showing a configuration of a digital demodulation device including a carrier recovery circuit according to a third embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Modulation wave input terminal, 2 ... In-phase detector, 3 ... Quadrature detector, 4 ... Distributor, 5 ... Local oscillator, 6, 7 ... A / D converter, 8 ... First complex multiplier, 9, Reference numeral 10 ... Digital low-pass filter, 11 ... Second complex multiplier, 12 ... Clock recovery circuit, 13 ... Data recovery circuit, 14, 15 ... Demodulated data output terminal, 16, 17 ... Low band suppression filter, 18
... phase detector, 19 ... frequency detector, 20 ... AFC loop opening / closing switch, 21 ... AFC loop filter, 22
… Numerically controlled oscillator, 23… Data converter, 24… PLL
Loop open / close switch, 25 ... Loop filter for PLL,
26 ... Numerically controlled oscillator, 27 ... Data converter, 28 ... Amplitude distribution detection circuit, 29 ... Synchronization determination circuit, 30 ... Loop control circuit, 31, 32 ... Low-pass suppression filter, 33 ... Interference detection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masaki Nishikawa, 8 Shinsita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture, Multimedia Research Laboratory, Toshiba Corp. (72) Yasushi Sugita, 8 Shinsita-cho, Isogo-ku, Yokohama, Kanagawa (56) Reference JP-A-6-78009 (JP, A) JP-A-9-275427 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) H04L 27/22 H04L 7/00

Claims (4)

(57) [Claims] 1. A frequency conversion means for generating a frequency conversion signal by frequency-converting an input digital modulated wave using a reproduced carrier signal, and a low frequency component of the frequency conversion signal generated by the frequency conversion means. Low-pass suppressing means for suppressing low-pass suppression characteristics, low-pass suppressing means for detecting low-frequency suppressing characteristics of the low-frequency suppressing means based on the low-frequency suppressing means for detecting a state of interference generated in the digital modulated wave, and Phase error detecting means for detecting a phase error of the frequency converted signal after the low frequency component is suppressed by the low frequency suppressing means, and frequency error of the frequency converted signal from the phase error detected by the phase error detecting means Frequency error detecting means, frequency controlling means for controlling the frequency of the reproduced carrier signal so as to reduce the frequency error, and the phase error detecting means. A carrier wave regenerating circuit comprising: a phase synchronizing means for controlling the phase of the regenerated carrier wave signal so as to reduce the phase error detected by the stage, and synchronizing the phase with the digital modulated wave. Wherein said when the disturbance by interference detection means is not detected, the carrier reproduction circuit according to claim 1, wherein the prohibiting low-frequency component suppressing operation by the low-frequency suppressing means. Wherein the interference detection means, carrier recovery circuit according to claim 1 or 2, wherein the detecting the state of the disturbance by monitoring the variation of the frequency conversion signal. Wherein said interference detection means, said frequency control means and the carrier recovery circuit according to claim 1 or 2, wherein the detecting the state from the operating state of the interference the phase synchronization means.