JP4886490B2 - Signal control apparatus, receiver, and signal control method - Google Patents

Description

  The present invention relates to a signal control device that adjusts the frequency and phase of a received signal obtained by receiving a phase-modulated signal having a predetermined frequency, a receiver having the signal control device, and a signal control method.

  In a receiver in a communication device used when data is transmitted using a telephone line or a dedicated line, a phase error may occur in a received signal. In particular, when a modulation scheme such as 64QAM is employed to realize high-speed communication, the density of symbol points on the vector plane is high and the distance between the symbol points is short. For this reason, highly accurate phase correction is required.

As a countermeasure against such a problem, the receiver is provided with a carrier phase control circuit. With this carrier phase control circuit, it is possible to remove the phase error generated in the received signal and improve the communication quality (see, for example, Patent Document 1).
JP-A-8-172464

  By the way, a large frequency offset may occur in the received signal. In such a case, the receiver can remove the phase error using the method described above, but has a tracking limit for a large frequency offset. For this reason, when a frequency offset occurs, it is required to appropriately remove the frequency offset together with the removal of the phase error.

  Therefore, an object of the present invention is to provide a signal control apparatus and a signal control method capable of appropriately removing both a frequency offset and a phase error.

The present invention is a signal control apparatus for adjusting the frequency and phase of a received signal obtained by receiving a phase-modulated signal having a predetermined frequency, the frequency correcting means for correcting the frequency of the received signal, and the frequency correction A phase error detecting means for detecting an error between a phase of the received signal whose frequency is corrected by the means and a phase determined by the phase modulation; a phase correcting means for correcting the phase error detected by the phase error detecting means; A phase control information generating unit configured to generate phase control information corresponding to the phase error detected by the phase error detecting unit; and a frequency offset of the received signal based on the phase control information generated by the phase control information generating unit. Frequency control information generating means corresponding to the frequency control means, the frequency correcting means is a frequency generated by the frequency control information generating means Based on the control information, and corrects the frequency of the received signal, said frequency control information generating means, each time the phase control information is generated by the phase control information generating unit, and the phase control information of the received signal Comparing means for comparing a first threshold value determined according to a condition for correcting the frequency and a second threshold value smaller than the first threshold value; It decreases when it is determined that it is greater than the threshold value of 1, and increases when the phase control information is determined to be smaller than the second threshold value by the comparison means, and the phase control information is increased by the comparison means. Phase frequency conversion information generating means for generating phase frequency conversion information that does not change when it is determined to be equal to or less than the first threshold and equal to or greater than the second threshold. A correction amount of frequency determined according to the phase frequency conversion information generated by the generation means, characterized that you generated as the frequency control information.

According to this configuration, in the configuration in which the frequency of the reception signal is corrected in the preceding stage and the phase of the reception signal is corrected in the subsequent stage, the phase control information corresponding to the phase error of the reception signal is generated, and based on the phase control information Then, frequency control information corresponding to the frequency offset of the received signal is generated, and the frequency of the received signal is corrected based on the frequency control information. Therefore, if the signal cannot be recovered by phase correction alone, frequency correction is performed in response to the phase error, and further phase correction is performed, and the frequency offset generated in the signal together with the phase error is corrected. It becomes possible to remove appropriately. Then, an appropriate frequency correction amount can be set according to the magnitude of the phase control information.

  In the signal control apparatus according to the present invention, the phase control information generation unit may generate phase control information corresponding to an integral value of the phase error repeatedly detected by the phase error detection unit.

  According to this configuration, when the phase error is repeatedly detected, the frequency control information corresponding to the frequency offset of the received signal is generated based on the phase control information corresponding to the integral value of the phase error, and the frequency control is performed. Based on the information, the frequency of the signal is corrected. Therefore, if the signal cannot be recovered by repeating only the phase correction, the frequency is corrected in accordance with the integral value of the phase error, and further, the phase correction is performed, and the frequency generated in the signal The offset can be appropriately removed together with the phase error.

  In the signal control device of the present invention, the phase control information generation unit includes a phase control information holding unit that holds the generated phase control information, and the frequency control information generation unit includes the phase frequency conversion information generation unit. A reset control means for resetting the phase control information held by the phase control information holding means when the phase frequency conversion information generated by the above is not the same as the phase frequency conversion information generated immediately before Also good.

  According to this configuration, when the phase frequency conversion information changes, the correction amount of the frequency corresponding to the phase error is determined. Therefore, the phase control information corresponding to the phase error is reset to remove the next frequency offset. Can be prepared.

  In the signal control apparatus of the present invention, the frequency correction unit may multiply the frequency of the signal by a frequency correction amount generated as frequency control information by the frequency control information generation unit.

  According to this configuration, the frequency offset generated in the received signal is removed by multiplying the frequency using the correction amount of the set frequency as a coefficient.

  In the signal control apparatus according to the present invention, the frequency correction unit includes a table holding unit that holds a table corresponding to the frequency control information, and the frequency correction unit refers to the table held in the table holding unit. A corrected multiplication value may be generated.

  According to this configuration, the amount of calculation can be reduced by holding the table corresponding to the frequency control information.

  In addition, the present invention includes a receiving unit that receives a phase-modulated signal having a predetermined frequency, and the signal control device according to any one of the above that processes a received signal obtained from the signal received by the receiving unit. It is the receiver characterized by this.

The present invention is also a signal control method for adjusting the frequency and phase of a received signal obtained by receiving a phase-modulated signal having a predetermined frequency, the frequency correcting step for correcting the frequency of the received signal, A phase error detection step for detecting an error between a phase of the received signal whose frequency is corrected by the frequency correction step and a phase determined by the phase modulation; and a phase correction step for correcting the phase error detected by the phase error detection step And a phase control information generation step for generating phase control information corresponding to the phase error detected by the phase error detection step, and a phase control information generated by the phase control information generation step. A frequency control information generation step corresponding to a frequency offset, and the frequency correction step includes: Based on the frequency control information generated by the frequency control information generating step, correcting the frequency of the received signal, said frequency control information generating step, each time the phase control information is generated by the phase control information generating step, A comparison step of comparing the phase control information with a first threshold value determined according to a condition for correcting the frequency of the received signal, and a second threshold value smaller than the first threshold value; The phase control information decreases when it is determined that the phase control information is greater than the first threshold, and increases when the phase control information is determined to be smaller than the second threshold by the comparison step, A phase frequency that does not change when it is determined by the comparison step that the phase control information is equal to or lower than the first threshold and equal to or higher than the second threshold. And a phase frequency conversion information generating step of generating conversion information, generating a correction amount of frequency determined according to the phase frequency conversion information phase frequency conversion information generated by the generating step as said frequency control information Features.

  According to the present invention, when the signal cannot be restored by only the phase correction, the frequency is corrected corresponding to the phase error, and further, the phase correction is performed. Can be appropriately removed together with the phase error.

  Embodiments of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a receiver incorporating a first signal control device according to the present invention. A first receiver 100-1 illustrated in FIG. 1 is provided in, for example, a mobile phone that performs communication with a base station, and includes an analog processing unit 110 and a digital processing unit 120.

  The analog processing unit 110 includes an antenna 111, an RF unit 112, and an analog / digital conversion unit (A / D) 114. On the other hand, the digital processing unit 120 corresponds to the demodulation / decimation processing unit 122, the frequency correction unit 124 corresponding to the frequency control information generation unit and the frequency correction unit, and the phase error detection unit, the phase correction unit, and the phase control information generation unit. The phase control unit 126, the frequency control unit 128 corresponding to the frequency control information generating means, and the baseband processing unit 130.

  The RF unit 112 receives an analog signal from a base station or the like received by the antenna 111, and converts the frequency of the analog reception signal into a predetermined frequency (for example, a baseband frequency). The analog reception signal whose frequency is converted is input to the A / D 114. The A / D 114 converts the analog reception signal whose frequency is converted into a digital reception signal, and outputs the digital reception signal to the demodulation / decimation processing unit 122 in the digital processing unit 120. The demodulation / decimation processing unit 122 demodulates the input digital reception signal. Further, the demodulation / decimation processing unit 122 incorporates a decimation filter (not shown), and reduces the sampling frequency of the demodulated digital reception signal to a predetermined frequency and outputs it.

  The phase control unit 126 receives the digital reception signal output from the demodulation / decimation processing unit 122 via the frequency correction unit 124 and detects the phase error in order to remove the phase error generated in the digital reception signal. Then, the phase error is integrated for each symbol to generate phase error information.

  FIG. 2 is a diagram illustrating a configuration of the phase control unit 126. 2 includes a multiplier 202, a multiplier 204, a sign inverter (NEG) 206, a limiter (LM) 208, a multiplier 210, an adder 212, and an integration tap corresponding to a phase error information holding unit. (NT) 214, multiplier 126, multiplier 218, adder 220, multiplier 222, multiplier 224, adder 226, adder 228, sum-of-squares calculator 230, reciprocal calculator 232, multiplier 234, and tap ( nT) 236.

  FIG. 3 is a flowchart showing the operation of the phase control unit 126. When reception starts (Yes in S101), the phase control unit 126 receives the digital reception signal output from the demodulation / decimation processing unit 122 via the frequency correction unit 124, and calculates the phase error of the digital reception signal. Detect (S102). Further, the phase controller 126 integrates the phase error to generate and hold phase error information (GTA0) (S103).

  Specifically, the multiplier 204 multiplies the digital reception signal by the normalized vectors NORX and NORY, normalizes the digital reception signal to a predetermined position on the vector plane, and outputs an imaginary component (im). The output value is the phase error detected at that time. The sign inverter 206 reverses the sign of this phase error, and the limiter 208 limits the output of the sign inverter 206 to a predetermined range and outputs it.

  The multiplier 210, the adder 212, the integration tap 214, and the multiplier 218 constitute an integration circuit. Multiplier 210 multiplies the output of limiter 208 by coefficient OFT1. The integration tap 214 holds the integration result of the phase error detected in the previous symbol, and the adder 212 adds the output of the multiplier 210 and the output of the integration tap 214, so that phase error information ( GTA0) is updated.

  Next, the phase control unit 126 calculates and reflects the phase correction amount (ZZR, ZZI) for removing the phase error (S104). Specifically, the multiplier 216 multiplies the output of the limiter 208 by a coefficient OFT2. Adder 220 adds the output of multiplier 216 and the output of multiplier 218. The multipliers 222 and 224, the adders 226 and 228, the sum of squares calculation unit 230, the reciprocal number calculation unit 232, the multiplier 234, and the tap 236 constitute an integration circuit. Multiplier 222 multiplies the output of adder 220 and the imaginary component of the output of tap 236. The multiplier 224 multiplies the output of the adder 220 and the real component of the output of the tap 236. Adder 226 subtracts the output of multiplier 222 from the real component of the output of tap 236. Adder 228 adds the imaginary component of the output of tap 236 and the output of multiplier 224. The sum of squares calculation unit 230 calculates the sum of squares from the outputs of the adders 226 and 228. The reciprocal computing unit 232 computes the reciprocal of the output of the square sum computing unit 230. Multiplier 234 multiplies the outputs of adders 226 and 228 and the output of reciprocal computing unit 232. As a result, the amplitude is normalized, and the obtained value is held in the tap 236, and becomes a new phase correction value (ZZR, ZZI).

  The phase control unit 126 outputs the phase error information (GTA0) generated and held in S103 to the frequency control unit 128 at the guard time (Yes in S105) (S106).

  Next, the phase control unit 126 determines whether or not a tap reset signal (RST), which will be described later, is input from the frequency control unit 128 (S107). Here, the tap reset signal (RST) is input to the integration tap 214. When the tap reset signal (RST) is not input, the process returns to the reception start waiting (S101) again, and the subsequent operations are repeated. On the other hand, when the tap reset signal (RST) is input, the integration tap 214 is reset (S108), returns to the reception start waiting (S101) again, and the subsequent operations are repeated.

In this way, the phase error information (the phase error integration result by the phase controller 126) (
GTA0) is generated and output to the frequency control unit 128, the frequency control unit 128 performs processing necessary to remove the frequency offset generated in the digital reception signal.

  FIG. 4 is a diagram illustrating a configuration of the frequency control unit 128. The frequency control unit 128 illustrated in FIG. 4 includes a phase error determination unit 302 corresponding to the comparison unit, an adder 304 corresponding to the phase frequency conversion information generation unit, a limiter (LM) 306, a tap (T) 308, and a reset control. A tap reset signal generator 310 corresponding to the means is configured.

  FIG. 5 is a flowchart showing the operation of the frequency control unit 128. The phase error determination unit 302 determines whether or not the phase error information (GTA0) from the integration tap 214 in the phase control unit 126 has been input (S201). When the phase error information (GTA0) is input, the phase error determination unit 302 determines whether the phase error information (GTA0) is larger than a predetermined first threshold value (S202).

  Here, the threshold value is determined according to a condition for correcting the frequency of the digital reception signal in a frequency correction unit to be described later. Specifically, the threshold value is determined corresponding to a frequency correction unit in the frequency correction unit. It is the value that has been. Here, the first threshold is phase error information (GTA0) corresponding to the positive direction of the frequency correction unit, and the second threshold is phase error information (GTA0) corresponding to the negative direction of the frequency correction unit. . When the phase error information (GTA0) is larger than the first threshold value, the phase error determination unit 302 sets the output value to −1 (S203).

  On the other hand, when the phase error information (GTA0) is equal to or smaller than the first threshold value, the phase error determination unit 302 determines whether or not the phase error information (GTA0) is smaller than a predetermined second threshold value. (S204).

  When the phase error information (GTA0) is smaller than the second threshold value, the phase error determination unit 302 sets the output value to +1 (S205).

  On the other hand, if the determination in step S204 is negative, that is, if the phase error information (GTA0) is any value greater than or equal to the second threshold and less than or equal to the first threshold, the phase error determination unit 302 outputs the output value. Set to 0 (S206).

  In this way, when the output value of the phase error determination unit 302 is determined, the adder 304 adds the output value and the value held in the tap 308. The added value is limited to a predetermined range by the limiter 306, and then output to the frequency correction unit 124 as frequency offset information (FST) that is phase frequency conversion information (S207).

  Further, the tap 308 inputs frequency offset information (FST) which is an added value whose size is limited by the limiter 306. Thereby, the frequency offset information (FST) held at the tap 308 and obtained at the previous guard time is updated to new frequency offset information (FST). The output value of the tap 308 is used when the adder 304 adds the output value of the phase error determination unit 302 and the output value of the tap 308 at the next guard time.

  Further, when the tap reset signal generation unit 310 receives the frequency offset information (FST) that is the output of the tap 308, the frequency offset information (FST) and the frequency offset that is the output of the tap 308 input at the previous guard time. The information (FST) is compared to determine whether there is a change (S209).

  When there is no change in the frequency offset information (FST), in other words, the phase error information (GTA0) is any value not less than the second threshold value and not more than the first threshold value. When the value is 0, the tap reset signal (RST) is not generated.

  If there is a change in the frequency offset information (FST), in other words, whether the phase error information (GTA0) is larger than the first threshold or smaller than the second threshold, and the output of the phase error determination unit 302 When the value is 1 or -1, a tap reset signal (RST) is output.

  The tap reset signal generator 310 outputs a tap reset signal (RST) for resetting the integration tap 214 to the integration tap 214 (S210). Thereby, as shown in S108 of FIG. 3 described above, the integration tap 214 to which the tap reset signal (RST) is input is reset. Similarly, the tap reset signal generator 310 outputs the tap reset signal (RST) to the frequency corrector 124 (S210). Thereafter, the operation after the determination (S201) on whether or not the phase error information (GTA0) is input is repeated again at the next guard time.

Therefore, when the phase error information (GTA0) is larger than the first threshold value or smaller than the second threshold value, the frequency offset information (FST) is updated, and the phase control unit 126 responds to the phase error. Instead of the phase correction, the frequency correction unit 124 described later performs frequency correction.

  FIG. 6 is a diagram illustrating a configuration of the frequency correction unit 124. The frequency correction unit 124 illustrated in FIG. 6 includes an adder 402, a logical product operator (AND) 404, a tap (nT) 406, a carrier shift table reference unit 408, a carrier shift table holding unit 409 corresponding to a table holding unit, and , And a multiplier 410.

  FIG. 7 is a flowchart showing the operation of the frequency correction unit 124. When reception is started (Yes in S301), the frequency correction unit 124 adds the frequency offset information (FST) input at the previous guard time and the value held in the tap 406 by the adder 402. This added value is output to the logical product operator (AND) 404. The logical product operator (AND) 404 calculates the logical value of the input addition value and m−1 obtained by subtracting 1 from the number of records (index number) m of the carrier shift table held in the carrier shift table holding unit 409 described later. The product is calculated and used as a reference index.

  For example, when the frequency offset information (FST) is 2, the value held in the tap 406 is 14, and the number of indexes is 16, the added value output from the adder 402 is 2 in the frequency offset information (FST), The sum of 14 held in the tap 406 and 16 is obtained. The logical product operator (AND) 404 obtains the logical product result 0 of the addition value 16 (binary number: 10000) and the bit string of 15 (binary number: 1111) obtained by subtracting 1 from the index number 16. By this calculation, each record of the carrier shift table held in the carrier shift table holding unit 409 is cyclically referred to in the carrier shift table reference unit 408. As a condition, the index number m is a power of 2.

  The reference index calculated by the logical product operator (AND) 404 is sent to the carrier shift table reference unit 408. The reference index is sent to the tap 406 and held in the tap 406 (S302).

  When the carrier shift table reference unit 408 receives the reference index from the logical product operator (AND) 404, the carrier shift table reference unit 408 refers to the carrier shift table held in the carrier shift table holding unit 409, and determines the frequency correction amount corresponding to the reference index. Obtain (S303).

  FIG. 8 is a diagram illustrating an example of a carrier shift table. As shown in FIG. 8, in the carrier shift table, each record is configured by associating an index with a frequency correction amount in each of the real component and the imaginary component. The carrier shift table reference unit 408 acquires a frequency correction amount associated with the same index as the reference index from the AND circuit 404.

  The acquired frequency correction amount is sent to the multiplier 410. When the frequency correction amount is input, the multiplier 410 multiplies the vector component of the digital reception signal from the demodulation / decimation processing unit 122 by the vector component of the frequency correction amount (S304). By repeating the series of operations from S302 to S304 for each symbol, the frequency of the digital reception signal is corrected and the frequency offset is removed (S304).

  Further, the frequency correction unit 124 determines whether or not the tap reset signal (RST) from the frequency control unit 128 is input at the guard time (Yes in S305) (S306). When the tap reset signal (RST) is not input, the process returns to the reception start waiting (S301) again, and the subsequent operations are repeated. On the other hand, when the tap reset signal (RST) is input, the tap 406 is reset and the frequency offset information (FST) is input (S307), and the operations after the reception start waiting (S301) are repeated again. .

  Again, returning to FIG. The frequency-corrected digital reception signal output from multiplier 410 is sent to phase control section 126. The phase control unit 126 corrects the phase of the digital reception signal after the frequency correction so as to remove the phase error based on the phase correction amount calculated in S102 of FIG. Specifically, the multiplier 202 in the phase control unit 126 multiplies the frequency-corrected digital received signal by the phase correction amount (ZZR, ZZI) held in the tap 236, thereby obtaining the phase correction amount. A digital reception signal that has been phase-corrected according to (ZZR, ZZI) is output. Further, the baseband processing unit 130 receives the digital reception signal after phase correction from the phase control unit 126, converts it into continuous data, and outputs it to a reception data processing unit (not shown).

  In this way, the first receiver 100-1 generates phase error information that is an integration result of the phase error of the received signal, and further sets a correction amount of the frequency of the received signal based on the phase error information. Then, the frequency of the received signal is corrected. Therefore, when the signal cannot be restored by only the phase correction, the phase error integration result is converted into a frequency correction amount to correct the frequency, in other words, the frequency offset is removed instead of the phase correction, Since the phase correction is performed after the frequency offset is removed, the frequency offset generated in the received signal can be appropriately removed together with the phase error.

  Next, another embodiment of the present invention will be specifically described with reference to the drawings. FIG. 9 is a diagram showing a configuration of a receiver incorporating the second signal control device according to the present invention. The second receiver 100-2 shown in FIG. 9 is provided in a modem in a mobile phone that communicates with a base station, for example, like the first receiver 100-1 shown in FIG. is there. Compared with the first receiver 100-1, the second receiver 100-2 has a configuration in which a frequency correction unit 134 is incorporated in the demodulation / decimation processing unit 132.

  FIG. 10 is a diagram illustrating a configuration of the frequency correction unit 134. 10 includes an adder 452, a logical product operator (AND) 454, a tap (nT) 456, a table selection unit 457, a decimation demodulation table reference unit 458, and a decimation demodulation table corresponding to the table holding unit. A holding unit 459 and a multiplier 460 are included.

  FIG. 11 is a flowchart showing the operation of the frequency correction unit 134. When reception is started (S 401), the adder 452 of the frequency correction unit 134 receives the fixed value 1 and adds the fixed value 1 and the value held in the tap 456. This added value is output to a logical product operator (AND) 454. The logical product operator (AND) 454 calculates the logic of the input addition value and m−1 obtained by subtracting 1 from the number of records (index number) m of the decimation demodulation table held in the decimation demodulation table holding unit 459 described later. The product is calculated and used as a reference index (S402). By this calculation, the decimation demodulation table reference unit 458 refers to the records of the decimation demodulation table held in the decimation demodulation table holding unit 459 in a cyclic manner.

  The reference index calculated by the AND operator (AND) 454 is sent to the decimation demodulation table reference unit 458. Further, the reference index is sent to the tap 456 and held in the tap 456. Further, the decimation demodulation table reference unit 458 refers to the decimation demodulation table selected in S407, which will be described later, based on the reference index from the AND operator (AND) 454, and the corrected multiplication value corresponding to the reference index. Is acquired (S403). The multiplier 460 multiplies this correction multiplication value by the scalar component of the digital reception signal from the A / D 11 (S404). By repeating the series of operations from S402 to S404 for each symbol, the digital reception signal is decimated and demodulated, the frequency is corrected, and the frequency offset is removed. Further, the frequency correction unit 134 determines whether or not the tap reset signal (RST) from the frequency control unit 128 is input at the guard time (Yes in S405) (S406). When the tap reset signal (RST) is not input, the process returns to the reception start waiting (S401) again, and the subsequent operations are repeated. On the other hand, when a tap reset signal (RST) is input, the tap 456 is reset.

  Further, frequency offset information (FST) from the frequency control unit 128 is input to the table selection unit 457 (S407), and this frequency offset information (FST) is sent to the decimation demodulation table reference unit 458 as decimation demodulation table selection information. It is done.

  The decimation demodulation table reference unit 458 selects the decimation demodulation table held in the decimation demodulation table reference unit 458 based on the decimation demodulation table selection information from the table selection unit 457. FIG. 12 is a diagram illustrating a correspondence relationship between the frequency offset information (FST) and the decimation demodulation table. A decimation demodulation table is prepared for each frequency offset information (FST). Each decimation demodulation table is a corrected multiplication value in the multiplier 460 when performing both demodulation and frequency correction. Then, the operation after the reception start waiting (S401) is repeated.

  As described above, the signal control device and the signal control method of the present invention can appropriately remove the frequency offset and the phase error generated in the received signal, and are useful as a signal control device and the like.

It is a figure which shows the structure of the 1st receiver which incorporates a signal control apparatus. It is a figure which shows the structure of a phase control part. It is a flowchart which shows operation | movement of a phase control part. It is a figure which shows the structure of a frequency control part. It is a flowchart which shows operation | movement of a frequency control part. It is a figure which shows the 1st structure of a frequency correction part. It is a flowchart which shows the 1st operation | movement of a frequency correction part. It is a figure which shows the structure of a carrier shift table. It is a figure which shows the structure of the 2nd receiver incorporating a signal control apparatus. It is a figure which shows the 2nd structure of a frequency correction part. It is a flowchart which shows the 2nd operation | movement of a frequency correction part. It is a figure which shows the correspondence of frequency offset information and a decimation demodulation table.

Explanation of symbols

100-1, 100-2 Receiver 110 Analog processing unit 111 Antenna 112 RF unit 114 A / D
120 Digital processing unit 122, 132 Demodulation / decimation processing unit 124, 134 Frequency correction unit 126 Phase control unit 128 Frequency control unit 130 Baseband processing unit

Claims (7)

A signal control device that adjusts the frequency and phase of a received signal obtained by receiving a phase-modulated signal having a predetermined frequency,
Frequency correction means for correcting the frequency of the received signal;
Phase error detection means for detecting an error between the phase of the received signal whose frequency is corrected by the frequency correction means and the phase determined by the phase modulation;
Phase correction means for correcting the phase error detected by the phase error detection means;
Phase control information generating means for generating phase control information corresponding to the phase error detected by the phase error detecting means;
Based on the phase control information generated by the phase control information generating means, the frequency control information generating means corresponding to the frequency offset of the received signal,
The frequency correction means corrects the frequency of the received signal based on the frequency control information generated by the frequency control information generation means ,
The frequency control information generating means includes
Each time phase control information is generated by the phase control information generating means, the phase control information, a first threshold value determined according to a condition for correcting the frequency of the received signal, and the first A comparison means for comparing a second threshold value smaller than the threshold value;
The phase control information decreases when the phase control information is determined to be greater than the first threshold, and increases when the phase control information is determined to be lower than the second threshold by the comparison unit. Phase frequency conversion information generation means for generating phase frequency conversion information that does not change when it is determined by the comparison means that the phase control information is less than or equal to the first threshold and greater than or equal to the second threshold. And
Signal control apparatus according to claim that you generate a correction amount of frequency determined according to the phase frequency conversion information phase frequency conversion information generated by the generating means as said frequency control information.   2. The signal control apparatus according to claim 1, wherein the phase control information generation unit generates phase control information corresponding to an integrated value of the phase error repeatedly detected by the phase error detection unit. The phase control information generating means has phase control information holding means for holding the generated phase control information,
The frequency control information generation unit is held by the phase control information holding unit when the phase frequency conversion information generated by the phase frequency conversion information generation unit is not the same as the previous phase frequency conversion information. signal control apparatus according to claim 1 or 2, characterized in that it has a reset control means for resetting the phase control information that. It said frequency correction means, the signal according to the correction amount of frequency generated as the frequency control information by the frequency control information generating unit, in any one of claims 1 to 3, characterized in that to multiply the frequency of the signal Control device. The frequency correction means has table holding means for holding a table corresponding to the frequency control information,
With reference to the table held in the table holding unit, the signal control device according to any one of claims 1 to 4, characterized in that to generate the correction multiplying value of the frequency. Receiving means for receiving a phase-modulated signal having a predetermined frequency;
Receiver; and a signal control device according to any one of claims 1 to 5 for processing the received signals obtained from the signal received by the receiving means. A signal control method for adjusting the frequency and phase of a received signal obtained by receiving a phase-modulated signal having a predetermined frequency,
A frequency correction step of correcting the frequency of the received signal;
A phase error detection step for detecting an error between the phase of the received signal whose frequency is corrected by the frequency correction step and the phase determined by the phase modulation;
A phase correction step for correcting the phase error detected by the phase error detection step;
A phase control information generation step for generating phase control information corresponding to the phase error detected by the phase error detection step;
Based on the phase control information generated by the phase control information generation step, the frequency control information generation step corresponding to the frequency offset of the received signal,
The frequency correction step corrects the frequency of the reception signal based on the frequency control information generated by the frequency control information generation step ,
The frequency control information generation step includes
Each time phase control information is generated by the phase control information generation step, the phase control information, a first threshold value determined according to a condition for correcting the frequency of the received signal, and the first A comparison step for comparing with a second threshold value smaller than the threshold value;
Decrease when the phase control information is determined to be greater than the first threshold value by the comparison step, and increase when the phase control information is determined to be less than the second threshold value by the comparison step; Phase frequency conversion information generation step for generating phase frequency conversion information that does not change when it is determined that the phase control information is equal to or lower than the first threshold and equal to or higher than the second threshold by the comparison step. And
A signal control method , wherein a frequency correction amount determined according to the phase frequency conversion information generated in the phase frequency conversion information generation step is generated as the frequency control information .

Images