JP3097582B2 - Frequency sweep circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency sweep circuit, and more particularly, to a frequency sweep circuit used in a multilevel modulator / demodulator for transmitting a digital signal.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional carrier recovery system used for digital radio.

In FIG. 2, a modulated wave input from a signal input terminal IN is multiplied by a multiplier 1 with a reproduced carrier wave output from a voltage controlled oscillator 6. Then, the output signal of the multiplier 1 is removed of unnecessary harmonics by the low-pass filter 2 to become a demodulated baseband signal. After that, the sample is quantized by the analog / digital converter 3 and then converted into a digital signal. From this digital signal, the phase error detector 4 detects a phase error between the carrier and the reproduced carrier, and outputs a control signal corresponding to the error. The control signal is smoothed by the loop filter 5 which is a low-pass filter, and becomes a carrier phase control signal of the voltage controlled oscillator 6. On the other hand, the analog sweeper 7, which is connected to the control signal in an AC manner, is an analog oscillator having a part of the positive feedback path as an input / output terminal, and oscillates the sweep signal when synchronization is lost depending on the state of the control signal. The range of establishment is expanded, and oscillation stops in the synchronous state.

[0004]

However, in the above-mentioned conventional carrier recovery circuit, since an analog oscillator is used as the frequency sweep circuit, it is difficult to implement an IC, and the oscillation conditions are liable to change. There were problems such as the frequency and amplitude being limited.

The present invention has been made in view of the above points, and an object of the present invention is to configure a main part of a frequency sweep circuit with a digital circuit so that an IC can be easily realized. Another object of the present invention is to provide a frequency sweep circuit which is stable without changing the oscillation condition and has a large degree of freedom in setting the oscillation frequency and amplitude.

[0006]

According to a first aspect of the present invention, there is provided a frequency sweep circuit used in a multilevel modulator / demodulator for transmitting a digital signal, wherein a confirmation signal for confirming a pull-in is provided. , A sweep wave generator for generating a frequency sweep signal, a first adder for adding the output of the pull-in confirmation wave generator and the output of the sweep wave generator, and receiving A phase error signal, which is a phase error between a carrier and a reproduced carrier, and an output of the first adder, which determine whether or not there is a correlation between them and output a control signal for controlling the sweep wave generator. A decision unit, a second adder that adds the output of the first adder and the phase error signal, a digital / analog converter that receives the output of the second adder as an input,
A loop filter that receives the output of the analog converter as an input,
And a voltage-controlled oscillator that receives the output of the loop filter and generates the reproduced carrier.

[0007] The correlation determinator described in the basic aspect includes a correlation detector and a pull-in determinator, and the correlation detector inputs the phase error signal and smoothes it.
A shift register and a third adder, the pull
Assuming that the frequency ratio between the confirmation wave and the reference operation clock is N,
The output of the adder 3 is used as a data input and the pull-in confirmation wave is used.
No. 2 operating with N / 2 frequency-divided clock input from generator
1 flip-flop, a second flip-flop receiving the output of the first flip-flop, and a first subtraction receiving both the output of the first flip-flop and the output of the second flip-flop. Vessel and the first
Check the pull-in by using the output from the adder as the data input
Operates with N / 2 frequency-divided clock input from wave generator
A third flip-flop, a fourth flip-flop receiving an output of the third flip-flop,
A second subtractor that inputs both the output of the flip-flop and the output of the fourth flip-flop;
And an EX-OR circuit for inputting both the output of the subtractor and the output of the first subtractor, and the output of the EX-OR circuit, and averaging this value for a certain period to obtain a correlation value. And a fourth shift register for obtaining
And a second subtractor that receives both the correlation value output from the fourth adder and a predetermined threshold value and compares them, If the correlation value exceeds the threshold value, the carrier recovery loop is determined to be in a synchronized state, while if the correlation value is less than the threshold value, the carrier recovery loop is determined to be in an asynchronous state. Have been.

Further, a characteristic aspect of the present invention is that a wave generated by the confirmation wave generator described in the basic aspect is a triangular wave.

[0009]

As can be understood from the above embodiment, the frequency sweep circuit of the present invention is capable of synchronizing the synchronous loop by detecting whether or not the negative phase component of the pull-in confirmation wave exists in the phase error signal. It is determined whether the state is the state, and if the sweep wave generator is controlled to be asynchronous, a sweep wave is generated. If the state is synchronous, the current level is maintained, so that the oscillation frequency is swept only in the asynchronous state.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a frequency sweep circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a frequency sweep circuit according to the present invention.

In FIG. 1, components 1 to 6 are the same as those shown in the conventional example, that is, the multiplier 1,
It includes a low-pass filter 2, an analog / digital converter 3, a phase error detector 4, a loop filter 5, and a voltage controlled oscillator 6.

Further, in this embodiment, in addition to the above components, the pull-in confirmation wave generator 8, the sweep wave generator 9, the adder 10, the correlation detector 11, the pull-in determiner 12, the adder 1
3. A digital / analog converter 14 is provided.

After the output of the pull-in confirmation wave generator 8 is added to the output of the sweep wave generator 9 by the adder 10,
The digital / analog converter 14 converts the signal into an analog signal. The output of the digital / analog converter 14 passes through the loop filter 5 and becomes the control voltage of the voltage controlled oscillator 6.

On the other hand, the output of the phase error detector 4 is input to the correlation detector 11. The correlation detector 11 receives the output of the phase error detector 4 and the output of the adder 10 as inputs, detects the correlation between the two inputs, and outputs the correlation to the pull-in determiner 12. The pull-in determiner 12 determines whether the signal is synchronous or asynchronous from the output of the correlation detector 11 and outputs a control signal to the sweep wave generator 9 based on the result.

Next, the operation of the frequency sweep circuit shown in FIG. 1 will be described. First, the digital pull-in confirmation wave output from the pull-in confirmation wave generator 8 is inserted into the phase error signal output from the phase error detector 4 through the adder 10 and the adder 13. At this time, it is assumed that the frequency of the confirmation wave is lower than the band of the loop filter 5 and sufficiently lower than the sampling speed of the phase error detector 4. It is also assumed that the amplitude is sufficiently smaller than the output signal of the phase error detector 4.

The waveform of the confirmation wave under this condition is arbitrary, but is assumed to be a triangular wave here for the sake of explanation. At this time, the sweep wave has a sufficiently large amplitude with respect to the output of the phase error detector 4 and has a lower frequency than the pull-in confirmation wave.

FIG. 3 shows the waveform at each point at this time. In FIG. 3, (a) shows the output of the sweep wave generator 9,
(B) is the output of the pull-in confirmation wave generator 8, (c) is the output of the adder 10, (d) is the output of the smoothed phase error detector 4, (e) is the output of the correlation detector 11, ( f) is the output of the pull-in judging device 12.

If the carrier recovery loop is in a synchronous state, the negative feedback effect of the phase locked loop will cause the phase error signal to have an antiphase component of the output of the adder 10. On the other hand, when the carrier recovery loop is in an asynchronous state, no negative feedback action occurs, and no negative-phase component of the output of the adder 10 appears in the phase error signal (FIG. 3C, FIG. 3). (D)).

The correlation detector 11 detects a negative correlation between the phase error signal and the output of the adder 10, thereby detecting the reverse phase component of the adder 10 included in the phase error signal (FIG. 2). 3 (c)). The pull-in judging unit 12 judges that the synchronization state is reached when the correlation amount output from the correlation detector 11 exceeds a certain value (see FIG. 3D).

Next, the operation after the determination will be described. When it is determined that the state is the asynchronous state, the sweep determination unit 12 causes the sweep wave generator 9 to generate a sweep wave. This sweep signal is supplied to an adder 10, an adder 13, a digital / analog converter 1
4. The voltage is applied to the voltage controlled oscillator 6 through the loop filter 5 to expand the pull-in range of the carrier recovery loop in which the oscillation frequency of the recovered carrier is swept. On the other hand, when the synchronization state is determined, the pull-in determination unit 12 outputs a sweep stop signal to the sweep wave generator 9. The sweep wave generator 9 stops the sweep by the sweep stop signal and fixes the output level.

FIG. 4 shows an example of the pull-in confirmation wave generator 8. According to the pull-in confirmation wave generator shown in FIG. 4, a triangular wave having a period N times the clock is output.

FIG. 5 shows an example of the correlation detector and the pull-in judging unit. According to FIG. 5, the phase error signal input at IN1 is smoothed by the shift register 18 and the adder 19 and input to the flip-flop 20. The flip-flop 20 receives N from the pull-in confirmation wave generator.
It operates using the を frequency-divided clock as a clock. Thereby, the flip-flop 20 pulls in the output of the adder 19 and alternately samples the peaks and valleys of the confirmation wave. The output of the flip-flop 20 is input to the subtractor 22 and the flip-flop 21, and the output of the flip-flop 21 is output to the subtractor 22. Since the output of the flip-flop 21 is delayed by N / 2 clocks with respect to the output of the flip-flop 20, the difference between the signal at the peak and the signal at the valley of the pull-in confirmation wave is output to the output of the subtractor 22. IN2
Similarly, the subtraction of the input from the adder 10 by the subtracter 25 through the flip-flops 23 and 24 outputs the difference between the value at the peak and the value at the valley of the pull-in confirmation wave. When the synchronization is established and a negative feedback action occurs, the subtractor 22
And the outputs of the two subtractors of the subtractor 25 have a negative correlation, so that the exclusive OR (E
X-OR), the correlation between the two can be detected. That is, if there is a correlation, EX-OR
The output of the circuit 26 has a high probability of taking a positive value. Conversely, when there is no correlation, the output of the EX-OR circuit 26 outputs positive and negative with equal probability. That is, the EX-OR circuit 2
The correlation value can be obtained by averaging the outputs of 6 through a shift register 27 and an adder 28 for a certain period. The correlation value is compared with a predetermined threshold value by the subtractor 29, and when the threshold value is exceeded, it is determined that the state is synchronous, and when the correlation value is less than the threshold value, it is determined that the state is asynchronous.

[0024]

According to the frequency sweep circuit of the present invention, since the main part of the circuit is constituted by a digital circuit, it can be easily integrated into an IC, the oscillation conditions are stable, and the degree of freedom in setting is large. Has an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a frequency sweep circuit according to the present invention.

FIG. 2 is a block diagram of a conventional demodulator.

FIG. 3 is a diagram of a waveform at each point of the circuit of FIG. 1;

FIG. 4 is a diagram showing a pull-in confirmation wave generator.

FIG. 5 is a diagram illustrating a correlation detector and a pull-in determination unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplier 2 Low-pass filter 3 Analog / digital converter 4 Phase error detector 5 Loop filter 6 Voltage control oscillator 7 Analog sweeper 8 Pull-in confirmation wave generator 9 Sweep wave generator 10, 13 Adder 11 Correlation detection Device 12 pull-in judging device 14 digital / analog converter 15 N / 2 frequency divider 16 2 frequency divider 17 up / down counter 18, 27 shift register 19, 28 adder 20, 21, 23, 24 flip-flop 22, 25, 29 subtractor 26 EX-OR circuit

Claims (3)

(57) [Claims] A frequency sweep circuit used in a digital signal transmission multi-level modulator / demodulator, comprising: a pull-in confirmation wave generator for generating a confirmation signal for pull-in confirmation; and a sweep wave generator for generating a frequency sweep signal. A first adder for adding the output of the pull-in confirmation wave generator and the output of the sweeping wave generator, a phase error signal indicating a phase error between a received carrier and a recovered carrier, and a first adder. And a correlation determiner for determining whether or not there is a correlation between the two, and outputting a control signal for controlling the sweep wave generator, and adding the output of the first adder and the phase error signal. A second adder, a digital / analog converter having an output of the second adder as an input, a loop filter having an output of the digital / analog converter as an input, and an output of the loop filter being input. age Frequency sweep circuit, comprising a voltage controlled oscillator for generating the serial reproduction carrier. 2. A correlation detector comprising a correlation detector and a pull-in determiner, wherein the correlation detector receives the phase error signal and smoothes it by a first shift register and a third adder. And the frequency ratio between the pull-in confirmation wave and the reference operation clock
Is N, the output of the third adder is the data input,
N / 2 frequency division clock input from the recording confirmation wave generator
A first flip-flop operating with a clock, a second flip-flop receiving an output of the first flip-flop, and both an output of the first flip-flop and an output of the second flip-flop. A first subtractor to be input, and an output from the first adder as a data input.
N / 2 frequency divider input from the pull-in confirmation wave generator
A third flip-flop operating in lock, a fourth flip-flop receiving an output of the third flip-flop, and inputting both an output of the third flip-flop and an output of the fourth flip-flop A second subtractor, an EX-OR circuit that inputs both an output of the second subtractor and an output of the first subtractor,
A second shift register and a fourth adder that receive an output of the OR circuit and obtain a correlation value by averaging the value over a certain period of time; and the pull-in determiner includes the fourth shift register. A second subtractor for inputting and comparing both the correlation value output from the adder and a predetermined threshold value, wherein the carrier recovery loop is provided if the correlation value exceeds the threshold value. 2. The frequency sweep circuit according to claim 1, wherein the frequency sweep circuit is configured to determine a synchronous state, and determine that the carrier recovery loop is an asynchronous state when the correlation value falls below the threshold value. 3. The frequency sweep circuit according to claim 1, wherein the wave generated by the pull-in confirmation wave generator is a triangular wave.