JPH09252327A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a costas digital demodulator in which the number of components is reduced and multi-value QAM(quadrature amplitude modulation) demodulation, is attained with a simple configuration. SOLUTION: A lock detection circuit 28 in a costas digital demodulator 100 monitors the level of an in-phase demodulation signal and an orthogonal demodulation sigixal by a costas system to change a lock discrimination output into an active state in the asynchronization state A waveform shaping circuit 40 repeats a state of 'H' level or 'L' level for a prescribed time at intervals of a prescribed period to reference potential sets Vref-H and Vref-L fed to a loop filter 18. Accordingly a control voltage of a voltage controlled oscillator(VCO) is increased or decreased by a prescribed quantity and restores to a steady-state at a prescribed time constant. In response to a change in the signal V2c, when the phase lock state is retrieved, a lock discrimination signal is inactive and the mode restores to the usual operating mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator for extracting a baseband signal from a phase-modulated modulated wave by synchronous detection. More specifically, the present invention relates to a Costas-type phase-locked phase recovery circuit for reproducing a carrier required for synchronous detection. The present invention relates to a configuration of a digital demodulator including a circuit.

[0002]

2. Description of the Related Art A typical method for generating a local oscillation wave for performing synchronous detection on a modulation wave in which a carrier wave is phase-modulated is a multiplication method, an inverse modulation (remodulation) method, or Costas. The law is well known. All of these are methods in which a modulation component is removed by a non-linear operation and a carrier wave in which noise and amplitude fluctuations are suppressed by a narrow band filter is reproduced on the receiver side.

Among them, the Costas method is a method of reproducing a carrier wave by multiplying a demodulated baseband signal. Since the processing for reproduction can be performed in the baseband band and a delay line is unnecessary, it can be easily integrated into an IC. Known as the scheme.

That is, in the Costas method, the process of obtaining the control signal for generating the local oscillation wave in phase synchronization with the received carrier wave is in the base band band, so that the synchronous detection circuit is PLL by the IC technique. (Phase Lo
cked Loop) circuit can be integrated.

Here, multi-valued QAM (Quadrature Amplitu
de Modulation) is a modulation method in which phase modulation and amplitude modulation are simultaneously performed on a carrier wave in order to transmit a plurality of bits of information at a time. For example, 16-value QA
M and others are known.

However, in the following description, the constituent parts of the multi-level QAM demodulator corresponding to amplitude modulation are not essential, and therefore, in order to simplify the explanation, the structure of the demodulator for phase modulation will be mainly described. I will explain.
That is, in the following, QPSK, which is one of multilevel QAM
(Quadrature Phase Shift Keying) This is equivalent to explaining the configuration of the demodulator.

First, before explaining the configuration of the QPSK demodulator, the principle of the Costas method will be briefly described.

Since QPSK has data on two axes (I, Q), if this data is D _I , D _Q (D _I , D _Q take a value of ± 1 at the sample point), the modulated wave is as follows: It becomes as follows.

D ₁ × cos (w _C t) + D _Q × sin (w _C t) (Equation 1) If the reproduced carrier wave (local oscillation wave) is reproduced with a phase shift of θ, reproduction is performed. The I ', Q'signals are as follows.

I ′ = D ₁ × cos (θ) −D _Q × sin (θ) (Equation 2) Q ′ = D _Q × cos (θ) −D _I × sin (θ) ... (Equation 3) Then, by multiplying I ′ and Q ′, I ′ × Q ′ = (D _I × D _Q ) {cos ² (θ) −sin ² (θ)} = D _I × D _Q × cos (2θ) (Equation 4) Therefore, as the phase difference between the received modulated wave and the regenerated carrier wave increases from 0, the regenerated I ′,
It can be seen that the magnitude of the Q'signal becomes smaller.

The output obtained by multiplying the sum and difference of the I'signal and the Q'signal is as follows.

(I ′ + Q ′) × (I′−Q ′) = {D _I + D _Q ) × cos (θ) + (D _I −D _Q ) × sin (θ)} × {D _I −D _Q ) × cos (θ) − (D _I + D _Q ) × sin (θ)} = (D _I + D _Q ) × (D _I −D _Q ) cos ² (θ) − (D _I + D _Q ) × (D _I −D _Q ) sin ² (θ) + {− (D _I + D _Q ) ² + (D _I −D _Q ) ² } × cos (θ) × sin (θ) = − 4D _I × D _Q × cos (θ ) × sin (θ) = − 2D _I × D _Q × sin (2θ) (Equation 5) Ignoring the constant coefficient and multiplying (Equation 4) and (Equation 5), D _I ² × D _Q ² × sin (4θ) = sin (4θ) (Equation 6)

Here, in deriving the equation 6, since D _I = ± 1 and D _Q = ± 1 (each value at the sampling point) in the calculation process, the signal D _I and the signal D _Q are In between, it is used that the following relationships of (Equation 7) to (Equation 9) are established.

D _I ² + D _Q ² = 2 (Equation 7) (D _I + D _Q ) × (D _I −D _Q ) = 0 (Equation 8) D _I ² = D _Q ² = 1 ... (Equation 9) By the above signal processing, it is possible to obtain only the phase difference θ of the reproduced carrier wave (local oscillation wave) that does not depend on the modulation wave as in (Equation 6), and using this value, the local oscillator that outputs the local oscillation wave By performing feedback control of the operation of, the carrier wave having no phase difference can be reproduced on the receiver side.

[0015]

According to the Costas method, the phase difference θ between the received modulated wave and the reproduced carrier wave can be detected, but the frequency error between them cannot be detected.

For this reason, in a carrier wave reproducing circuit generally using the Costas method, a VCO (Voltage Controlled) for carrier wave reproducing is forcibly forced to a frequency that can be pulled in by the Costas circuit.
Oscillator) circuit or a method of sweeping the output frequency of a VCO for a frequency converter is used.

FIG. 6 is a schematic block diagram showing the structure of a conventional Costas-type multilevel QAM demodulator 200.

The received modulated wave is first converted to an intermediate frequency (hereinafter, referred to as an intermediate frequency by a frequency down converter (not shown) in the first stage.
Call it IF. ) Is converted to. A band-pass filter (hereinafter referred to as BPF) 2 removes an unnecessary frequency signal component from the IF input. Then, the IF input is multiplied by the locally oscillated wave from the VCO 36 in the mixer 4 and further converted into the second IF. Here, the output of the VCO 36 input to the mixer 4 is the V output from the loop filter 26.
It is configured to be controlled by the CO control voltage.

As will be described later, the control of the output frequency of the VCO 36 is controlled in accordance with the frequency error detected from the in-phase component and the quadrature component of the baseband signal and the detection result of the phase locked state. There is.

The second IF signal has mixers 8 and 10 after further unnecessary signal components are removed in BPF 6.
Respectively. The mixer 8 has a V for carrier wave reproduction.
The local oscillation wave in which the output from the CO 20 is changed in phase by 90 ° in the 90 ° phase shifter 22 is also input. Therefore, in the mixer 8, the second IF signal is multiplied by the 90 ° phase-converted local oscillation wave, and in the low-pass filter (hereinafter referred to as LPF) 12,
After the unnecessary frequency components are removed, the in-phase demodulated signal (hereinafter,
It is called an I demodulation signal. ) Is output.

On the other hand, the mixer 10 has a V for reproducing a carrier wave.
The local oscillation wave from the CO 20 is also input. Therefore, the second IF signal is output as a quadrature demodulation signal (hereinafter referred to as a Q demodulation signal) after being multiplied by the local oscillation wave in the mixer 10 and the unnecessary frequency component being removed by the LPF 14.

The phase error detection circuit 16 periodically samples the I demodulated signal and the Q demodulated signal, and detects the phase error between the two by performing the processing corresponding to the above equation 6,
The phase error signal corresponding to the phase difference between the I demodulated signal and the Q demodulated signal is output to the loop filter 18.

The loop filter 18 is a kind of integrating circuit, which removes a signal component of a phase error signal having a frequency higher than a predetermined frequency, smoothes it and converts it into a VCO control voltage, and oscillates the frequency of the VCO 20 for carrier wave reproduction. Are in control.

Therefore, the mixers 8 and 10, the loop filters 12 and 14, the phase error detection circuit 16, the loop filter 18, the carrier recovery VCOs 20 and 90 °.
The phaser 22 forms a so-called Costas loop.

As described above, based on the phase difference between the received modulated wave detected from the demodulated I demodulated signal and the Q demodulated signal and the local oscillated wave, the oscillation frequency of the VCO 20 is maintained so that the phase locked state is maintained. Is controlled. However, in the Costas loop, only the phase error is detected, so that a structure for maintaining the frequency error at almost 0 is required to maintain the demodulation operation normally. In other words, when there is a deviation between the frequency of the received modulated wave and the frequency of the local oscillation wave, a configuration is required to forcibly shift the frequency of the local oscillation wave to the retractable range of the Costas circuit. .

Therefore, the multilevel QAM demodulator 2 shown in FIG.
In 00, when a frequency error occurs between the frequency of the reception modulated wave and the local oscillation wave, in order to forcibly generate the point where the frequency error is 0, the control voltage of the VCO 36 for frequency conversion is separately The sweep signal generated by the VCO 30 is added.

That is, the frequency error detection circuit 24 receives the I demodulated signal and the Q demodulated signal and detects the frequency error in the range where the frequency error between the received modulated wave and the local oscillation wave is less than or equal to a predetermined value. , And outputs the corresponding frequency error detection signal df to the loop filter 26. Loop filter 26 receives signal df, smoothes its value, and outputs a corresponding VCO control voltage V1c. In this state, the lock determination output Lj from the lock detection circuit 28 that monitors the output levels of the I demodulated signal and the Q demodulated signal is in the inactive state (“H” level), and the switch 32 is in the non-conductive state. Has become. Therefore, the output voltage V1c of the loop filter 26 is output from the adder 34, and the output frequency of the VCO 36 is controlled accordingly. Therefore, the frequency error detection circuit 24 that receives the I demodulated signal and the Q demodulated signal, the loop filter 26 that receives the output signal df and outputs the VCO control voltage V1c, the adder 34, the VCO 36, and the mixer 4 form a negative feedback loop. The output frequency of the VCO 36 is controlled so that the formed frequency error becomes zero.

Here, when the lock detecting circuit 28 detects that the frequency error is equal to or more than a predetermined value and the output levels of the I demodulated signal and the Q demodulated signal are less than a certain value,
The lock detection circuit 28 changes its output signal Lj to the active state (“L” level). In response to this, the switch 32 becomes conductive, and the sweep signal from the VCO 30 is output to the adder 34. Therefore, VC
The VCO output from the loop filter 26 is supplied to O36.
A voltage in which the control voltage V1c and the sweep signal from the VCO 30 are superimposed is applied.

The above signal V1c and the sweep signal are V
The operation of the multi-valued QAM demodulator 200 while being applied to the CO 36 will be described in more detail with reference to FIG. 7.

In FIG. 7, the hatched area (a) is the frequency pull-in range of the Costas circuit, and (b) is the VCO 36.
It shall be the initial value of the control voltage of.

In the initial state, since the VCO control voltage is not in the area (a), this circuit cannot perform the phase lock and cannot reproduce the synchronized carrier wave. Therefore, the lock detection circuit 28 in FIG.
However, it is determined that the VCO for sweep signal
The switch circuit 32 connected to 30 is also made conductive. The sweep signal is superimposed on the control input of the VCO 36 for frequency conversion by the adder 34. As a result, the control voltage of the VCO changes in a sine wave as shown in FIG. C2 and c3, which are the points where the VCO control voltage that draws a sine wave enters the region (a)
In, the Costas circuit can perform operations with synchronized phases.

In the example shown in FIG. 7, the phase lock cannot be completed at the operating point c2, but the phase lock is completed at the operating point c3. That is, the lock detection circuit 28 in FIG. 6 detects the phase lock state at the operating point c3 for the first time, and brings the switch 32 into the non-conducting state to stop the sweep of the control voltage.

By this series of operations, the frequency error between the received modulated wave and the local oscillation wave is returned to a value of almost 0, and the phase lock operation in the Costas circuit is also returned to the synchronous state.

However, the conventional multilevel QAM demodulator 2
Since 00 has the above-described configuration, in order to maintain the frequency error at a predetermined value or less, the down converter V
In addition to CO36 and VCO20 for reproducing carrier wave generation,
There is a problem that the VCO 30 for generating the sweep signal is required and the circuit configuration becomes complicated.

The present invention has been made to solve the above problems, and its object is to provide multi-valued QAM.
In the demodulator, the number of parts is reduced and the configuration is simpler.
It is an object of the present invention to provide a digital demodulator capable of forcibly converting the frequency of a local oscillation wave to a frequency at which the Costas circuit can be pulled.

[0036]

The Costas type digital demodulator according to claim 1 is a Costas type digital demodulator which receives and demodulates a digital signal transmitted by a carrier which is multi-valued QAM modulated. Local oscillating means for outputting a first local oscillating wave of a corresponding frequency and a second local oscillating wave having a phase orthogonal to the first local oscillating wave in accordance with the control signal; a carrier wave and a first local part. First reproducing means for receiving the oscillating wave and extracting the in-phase component of the baseband signal; and second reproducing means for receiving the carrier wave and the second local oscillating wave and extracting the quadrature component of the baseband signal, Phase error detection means for receiving the in-phase component and the quadrature component and outputting a phase error signal according to the phase difference between the first local oscillation wave and the carrier wave, and for receiving the in-phase component and the quadrature component, at least one of Level A phase synchronization detection unit that activates the filter control signal in response to the value being equal to or less than a predetermined value, a smoothing unit that receives the phase error signal, and a filtering unit that outputs the oscillation control signal, and the filtering unit includes: The oscillation control signal is changed within a predetermined range according to the activation of the filter control signal.

According to a second aspect of the Costas digital demodulator, in the structure of the Costas digital demodulator according to the first aspect, the phase synchronization detecting means detects the level value of the in-phase component at a predetermined cycle, and a predetermined value. In the following cases, the first level inverting means for activating the first error signal and the first level inverting means for accumulating the number of activations of the first error signal over a predetermined period.
Counting means, second level discriminating 0 means for detecting the level value of the orthogonal component in a predetermined cycle, and activating the second error signal when the level value is equal to or less than the predetermined value; It includes a second counting means for integrating the number of times of activation of the error signal, and a synchronization determining means for activating the filter control signal according to the integration result of the first and second counting means.

The Costas type digital demodulator according to a third aspect is the Costas type digital demodulator according to the second aspect, in which the phase synchronization detecting means receives the output of the synchronization determining means and activates the filter control signal. Further, a waveform shaping means for outputting first and second reference potentials, which repeats a state in which both are at the first potential and a state in which both are at the second potential intermittently in the second predetermined cycle, is further provided. The filter means includes a differential amplifying means for receiving the phase error signal at the first input node and outputting an oscillation control signal, and a first amplifying means connected between the first input node and the output node of the differential amplifying means. One capacitance means and a second capacitance means having one end connected to the second input node of the differential amplifier means and the other end held at the first potential;
When either of the first and second reference potentials is the first potential or both are the second potential, either of the corresponding first potential and second potential is changed to a resistor. Via a second input node to the first and second
And a reference potential control means for supplying an intermediate potential between the first and second potentials to the second input node.

[0039]

1 is a schematic block diagram showing the configuration of a Costas type digital demodulator 100 according to an embodiment of the present invention.

Referring to FIG. 1, digital demodulator 100
Has a configuration as a multilevel QAM demodulator.

The digital demodulator 100 receives the IF input and removes unnecessary frequency signal components BPF2 and BPF2.
A mixer 4 that receives the output from the PF 2 and the output from the VCO 34, multiplies them to output a second IF signal, and a mixer 4
B, which removes unnecessary frequency signal components by receiving the output of
A mixer 10 that receives the PF 6, the output of the BPF 6, and the local oscillation wave from the carrier recovery VCO 20 and multiplies them by
And output the output of VCO 20 by 90 ° phase conversion 9
0 ° phaser 22, the output of BPF 6 and 90 ° phaser 22
Mixer 8 which receives the output of
And an LPF 12 that receives the output of the mixer 8 and removes unnecessary signal components to output an I demodulated signal, and an output of the mixer 10 that removes unnecessary signal components and outputs a Q demodulated signal. The LPF 14, the I demodulation signal and the Q demodulation signal, receives the frequency error between the received modulated wave and the local oscillation wave, detects the frequency error, outputs the frequency error signal df, and receives the signal df to smooth it. , VCO control signal V1c is output as loop filter 26, and signal V
1c, and a VCO 34 that outputs a local oscillation wave having a corresponding frequency.

The digital demodulator 100 further receives the I demodulated signal and the Q demodulated signal, detects a phase error between the received modulated wave and the local oscillated wave, and outputs a phase error signal, and a phase error detection circuit 16. A lock detection circuit 28 that receives the I demodulated signal and the Q demodulated signal and determines the phase synchronization state;
The loop filter 1 receives the output of the lock detection circuit 28.
8, the reference potentials Vref-H and Vref-L
A waveform shaping circuit 40 for outputting a phase error signal and reference potentials Vref-H and Vref-L
Loop filter 1 for outputting O control voltage V2c
8, a VCO 20 that receives the signal V2c and outputs a local oscillation wave of a corresponding frequency, and a 90 ° phase shifter 22 that receives the output of the VCO 20 and converts the phase by 90 ° and outputs the 90 ° phase shifter.

FIG. 2 is a schematic block diagram showing the structure of the loop filter 18. The loop filter 18 is a so-called active filter circuit including a differential amplifier (op amp) as a basic constituent element.

The loop filter 18 is a differential amplifier 182.
And a capacitor 1 connected between the negative input node In2 of the differential amplifier and the output node of the differential amplifier 182.
84, a capacitor 186 connected between the positive input terminal In1 of the differential amplifier 182 and the ground potential, and a phase error signal from the phase error detection circuit 16 to convert the phase error signal to a predetermined potential, and the differential amplifier Charger pump circuit 188 for outputting to input node In2 of 182, and differential amplifier 182
Of the potential level of the input node In1 of the waveform shaping circuit 40
And a reference potential control circuit 190 for controlling according to the reference potentials Vref-H and Vref-L.

Here, reference potentials Vref-H and Vr
ef-L is a lock detection circuit 28, as will be described later.
The period during which it is determined that the demodulation operation is not normally performed and is in the unlocked state is a signal which repeats a period in which both are at the power supply potential and a period in which both are at the ground potential intermittently in a predetermined cycle. That is, during the period when the lock detection circuit 28 determines that it is in the unlocked state, the predetermined period signal V
Both ref-H and Vref-L are at "L" level, and the signal Vref-H is "H" for a certain period thereafter.
At the level, Vref-L becomes "L" level. Then, the signals Vref-H and Vref-L are both at the "H" level for a predetermined period. After that, the above operation is repeated during the period when the lock detection circuit determines that the lock state is not locked.

The reference potential control circuit 190 has one end connected to the node In1 and the other end receiving the signal Vref-H, and a resistor 192 in parallel with the resistor 192 and at the node In1.
From the resistor 192 to the other end of the resistor 192 in the forward direction, a resistor 194 having one end at the node In1 and the other end receiving the signal Vref-L, and a resistor 194 in parallel with the resistor 194. Diode 198 connected in the forward direction from the other end of 194 toward node In1.

Therefore, in the loop filter 18, the signal Vref-H is at "H" level, and the signal Vref-L is
When is at "L" level, the following operation is performed.

In this case, the potential level of the node In1 is
It is an intermediate value between the “H” level and the “L” level and has a potential divided by the resistors 192 and 194. Therefore, the differential amplifier 182 and the capacitor 184 constitute an integrating circuit, and the phase error signal smoothed by a predetermined time constant is used as the VCO control signal V2c.
Output as

Hereinafter, this state will be referred to as a normal mode. Next, from the operating state in the normal mode, the signal V
When both ref-H and signal Vref-L become "H" level, the potential level of node In1 is raised to "H" level. Therefore, the differential amplifier circuit 182
Also, the output level of 1 changes greatly according to the change of the input potential level. After that, when the signal Vref-H returns to the “H” level and the signal Vref-L returns to the “L” level, the voltage is applied in the reverse direction to the diode 198, so that the node In1 goes to the “H” level. The electric charge accumulated in the capacitor 186 at the time of is discharged through the resistor 194. Therefore, with the time constant determined by the capacitance value of the capacitor 186 and the resistance value of the resistor 194, the potential level of the node In1 returns to near the potential level in the normal mode.

Therefore, VCO control signal V2
After the potential level of c largely fluctuates, it gradually returns to the output level range in the normal mode with a predetermined time constant.

On the other hand, when both the signal Vref-H and the signal Vref-L are at the "L" level from the operating state in the normal mode, the VCO control signal V2c.
Fluctuates greatly in the opposite direction to the above case. After that, the signal Vref-H and the signal Vref-L
Becomes "H" level and "L" level respectively,
The VCO control signal V2c is charged with a time constant determined by the resistance value of the resistor 192 and the capacitance value of the capacitor 186, and the potential level of the node In1 also returns to the potential level in the normal mode. Therefore, the VCO control signal V2c also returns to near the level in the normal mode.

That is, the signal Vref-H and the signal V
By controlling ref-L and as described above, the VCO control signal V output from the loop filter 18 is output.
2c can be changed in a predetermined range and with a predetermined time constant, and accordingly, the frequency of the local oscillation wave output from the VCO 20 can be swept in a predetermined range.

That is, the Costas type digital demodulator 10
At 0, when the frequency error is equal to or higher than a predetermined value and the output levels of the I demodulated signal and the Q demodulated signal are equal to or lower than the predetermined value, the VCO control signal V2c output from the loop filter 18 is changed. Then, the configuration is such that the phase locked state is restored again.

Therefore, the VCO 30 for generating the sweep signal, which is required in the configuration of the conventional Costas type digital demodulator 200, becomes unnecessary, and the circuit configuration can be simplified.

FIG. 3 shows the lock detection circuit 28 shown in FIG.
3 is a schematic block diagram showing the configuration of a waveform shaping circuit 40. FIG.

The lock detection circuit 28 samples the I demodulated signal at a predetermined cycle, judges the level of the I demodulated signal, and activates the first error signal when it detects that the I demodulated signal is below a predetermined value. And an error integration counter 286 that integrates the number of times the first error signal is activated for a predetermined period, and a level determination is performed by receiving the Q demodulation signal, and if it is determined that the value is less than or equal to a predetermined value, the second error signal The level determination circuit 284 that activates the second error signal, the error integration counter 288 that integrates the number of activations of the second error signal for a predetermined period, and the outputs from the error integration counters 286 and 288 receive the synchronization state. The lock determination circuit 290 for determining whether or not the error integration counter 286 controls the error integration counter 286 and the error integration counter 286 at a predetermined cycle. An integrated value of beauty 288 and a reset circuit 292 for generating a reset signal for resetting.

The waveform shaping circuit 40 includes the lock determination circuit 28.
If it is in the locked state after receiving the judgment result from
The "H" level potential is output as the signal Vref-H,
In the unlocked state, the Vref-H generation circuit 402 sets the signal Vref-H to the "L" level for a predetermined period in a predetermined cycle, and in the locked state, the potential of the "H" level is supplied to the signal Vref. -L, and when in the unlocked state, Vref-H for a predetermined period at a predetermined cycle.
A Vref-L generation circuit 404 that shifts the signal Vref-L to "H" level with a half cycle shift from the generation circuit 402.
And

That is, in the lock detection circuit 28,
When it is determined that the output level of either the I demodulated signal or the Q demodulated signal is equal to or lower than a constant level value for a predetermined period, the reference potentials Vref-H and Vref-L are set in a predetermined cycle as described above. Intermittently, a period in which both are at "H" level and a period in which both are at "L" level are repeated. On the other hand, the lock detection circuit 28
During the period in which it is determined that the lock state is established, the reference potential V
The ref-H is maintained at the "H" level and the reference potential Vref-L is maintained at the "L" level.

The operations of the lock detection circuit 28 and the waveform shaping circuit 40 will be described in more detail below.

FIG. 4 is a timing chart for explaining the operations of the lock detection circuit 28, the waveform shaping circuit 40 and the loop filter 18.

Referring to FIG. 4, level determination circuits 282 and 284 in lock determination circuit 28 respectively input I demodulated signal and Q at a predetermined sampling point.
The level value of the demodulated signal is determined. When the phase synchronization is perfectly established, the data value at the sampling point shall be +1 or -1 in the demodulation of the QPSK signal. At this time, if the data value at the sampling point is not within the range of + 1 ± α or −1 ± α (for example, α = 0.5), the level determination circuit outputs the first and second error signals respectively output. Activate.

Error accumulation counters 286 and 288
Counts the number of times that the first and second error signals output from the corresponding level determination circuits 282 and 284 are active for a certain period. The lock determination circuit 290 determines whether or not it is in the synchronization state, depending on whether or not any of the integrated values exceeds the threshold level during the above-mentioned fixed period. The error integration counters 286 and 288 are configured to integrate the number of active states of the error signal because the level of the I demodulation signal or the Q demodulation signal is + 1 ± α or −1 due to noise.
This is because it may be outside the range of ± α.

In FIG. 4, it is assumed that it is determined that the lock inversion output is in the active state (“L” level) as the initial state and is in the unlocked state.

At time t0, reference potential Vref-H changes to "L" level for a predetermined period (Δt). Therefore, since the reference potentials Vref-H and Vref-L both become the "L" level, the + input voltage of the differential amplifier 182 of the loop filter 18 shown in FIG. To do. In response to this, the output voltage of the differential amplifier 182 changes to the side where the input voltage is inverted and greatly increases.

After the time Δt has elapsed, the reference potential Vref-H
Is returned to the “H” level, the + of the differential amplifier 184
The input voltage also returns to the intermediate level with a predetermined time constant.

At time t1, this time the reference potential Vre
f-L changes to the "H" level only during the time Δt.
Therefore, the + input voltage of the differential amplifier 182 is large +
Shift to the side.

In response to this, the output voltage of the differential amplifier 182, that is, the VCO control signal V2c changes to the side of greatly decreasing. After a lapse of time Δt from the time t1, the reference potential Vref-L returns to the “L” level, and thereafter, + to the differential amplifier 182 with a predetermined time constant.
The input voltage also returns to the intermediate level, and accordingly, the output voltage V2c of the differential amplifier 182 also returns toward the intermediate level.

On the other hand, the error integrating counter has level determining circuits 282 and 28 for the period from time t0 to time t2.
The number of activations of the error signal from 84 is integrated.
In this case, since the error integrated value in the period from time t0 to t2 exceeds the predetermined threshold value, the lock determination circuit 290 determines that it is still in the unlocked state.
In response to this, again at time t2, the reference potential Vref is reached.
-H changes to "L" level during the time period Δt. On the other hand, according to the reset signal from the reset circuit 292,
The count values of the error integration counters 286 and 288 are reset.

After that, between time t2 and time t4, the error integration counters 286 and 288 again integrate the number of activations of the error signals from the level determination circuits 282 and 284, and the reference potentials Vref-H and Vref. −
Similarly to time t0 to time t2, L repeats a state where it is both at the "L" level and a state where it is at the "H" level intermittently.

At time t4, the integrated values of the error integration counters 286 and 288 are again set to the lock determination circuit 290.
Judge. In this case, since the error integration counter value still exceeds the threshold value, the lock determination circuit determines that it is in the unlocked state and maintains the lock determination output in the active state (“L” level). In this state, the reference potentials Vref-H and Vref-L are again
It changes similarly to the period from time t4 to time t6 and the period from time t2 to time t4. When the Costas circuit returns to the phase locked state according to the change in the output voltage of the differential amplifier 182, the error integration counter value in the period from time t4 to time t6 decreases, and the error integration value in this period becomes equal to or less than the threshold value. Become. Therefore, the lock determination circuit 290
Determines that the lock state has been restored at time t6, and changes the lock determination output to the inactive state (“H” level).

In response to this, the Vref-H generation circuit 40
The output level of 2 holds "H" level, and Vref-L
The output level of the generation circuit 404 holds the "L" level.

Therefore, the + input voltage of the differential amplifier 182 also holds the intermediate potential. That is, the output voltage of the differential amplifier 182, that is, the VCO control signal V2c is
In accordance with the phase error signal from the phase error detection circuit 16, the phase locked state is maintained while making a slight change.

FIG. 5 shows time t4 to time t in FIG.
FIG. 6 is an enlarged view showing a change in VCO control voltage in FIG.

In FIG. 5, the frequency pull-in range (a) of the Costas circuit is shown by hatching. At time t4, the VCO control voltage is at the position (b), and the phase cannot be locked. When the lock detection circuit 28 determines that the current state is not the phase lock state, the lock detection circuit 28 sets the level of the reference potential Vref-L among the reference potentials output from the waveform shaping circuit 40 to the “H” level.

The diode 198 connected in parallel with the resistor 194 causes the + input voltage of the loop filter to rise at once. Next, after the lapse of time Δt, the reference potential Vref−
When the L level returns to the “L” level, the output voltage of the loop filter, that is, V
The CO control voltage gradually drops.

At time t5, the reference potential Vref-H
Becomes the "L" level during the period of time Δt. At this time, the diode 1 connected in parallel with the resistor 192
96 causes the + input voltage of the differential amplifier 182 of the rope filter to drop at once. After the lapse of time Δt, the level of the reference potential Vref-H returns to the “H” level again,
The output voltage of the loop filter, that is, the VCO control signal V2c gradually rises with a slope determined by the time constant of RC. In FIG. 5, it is assumed that the rising frequency falls within the pull-in frequency range of the Costas circuit during the rising, and the phase is locked at (c1) in the drawing. After that, the first and second error signals output from the level determination circuits 282 and 284 are not activated, so that the integrated values of the error integration counters 286 and 288 do not increase. Therefore, at time t6, the lock determination circuit 290 determines that the lock state has been restored, and sets the lock determination output to the inactive state (“H” level). After that, the reference potential V
The ref-H and Vref-L become the "H" level and the "L" level, respectively, and the normal mode operation is performed.

That is, these operations make it possible to forcibly move the frequency of the local oscillation wave within the pull-in range of the Costas circuit.

In the present embodiment described above, the configuration for sweeping the VCO control voltage V2c for controlling the VCO 20 for carrier wave regeneration has been described, but the configuration in which the sweep VCO 30 is omitted is as follows. The present invention is not limited to this. For example, the output voltage V1c of the loop filter 26 may be swept and the oscillation frequency of the down converter VCO 34 may be swept according to the reference potential output from the waveform shaping circuit 40. is there.

[0079]

With the above configuration, in the Costas type digital demodulator, the error between the frequency of the locally oscillated wave generated in the demodulator for demodulation operation and the frequency of the received modulated wave is a predetermined value. As described above, even if it is necessary to sweep the oscillation frequency of the local oscillation wave to sweep the local start frequency to the retractable range of the Costas circuit, a dedicated oscillation circuit for performing this sweep is unnecessary, and it is easier to perform. There is an advantage that the Costas type digital demodulator can be configured with the circuit configuration.

This results in a reduction in the number of parts,
It also makes it possible to reduce manufacturing costs.

[Brief description of drawings]

FIG. 1 is a Costas type digital demodulator 100 according to the present invention.
FIG. 2 is a schematic block diagram showing the configuration of FIG.

2 is a schematic block diagram showing a configuration of a loop filter 18 of the Costas type digital demodulator 100. FIG.

3 is a schematic block diagram showing configurations of a lock detection circuit 28 and a waveform shaping circuit 40 of the Costas type digital demodulator 100. FIG.

FIG. 4 is a timing chart showing the operation of the Costas digital demodulator 100.

5 is an enlarged view of a main part of the timing chart shown in FIG.

FIG. 6 is a schematic block diagram showing a configuration of a conventional Costas type digital demodulator 200.

FIG. 7 is a timing chart for explaining the operation of the conventional Costas type digital demodulator 200.

[Explanation of symbols]

 2,6 Bandpass filter 4,8,10 Mixer 12,14 Lowpass filter 16 Phase error detection circuit 18 Loop filter 20 Carrier recovery VCO 22 90 ° Phaser 24 Frequency error detection circuit 26 Loop filter 28 Lock detection circuit 30 For sweep VCO 32 switch circuit 34 adder 36 VCO for down converter 100 Costas type digital demodulator 200 Conventional Costas type digital demodulator

Claims (3)

[Claims] 1. A Costas type digital demodulator for receiving and demodulating a digital signal transmitted by a carrier wave which is multi-valued QAM modulated, wherein a first local oscillation wave of a frequency corresponding to an oscillation control signal. A local oscillating means for outputting a second local oscillating wave having a phase orthogonal to the first local oscillating wave; First reproducing means for extracting; second reproducing means for receiving the carrier wave and the second local oscillation wave to extract a quadrature component of a baseband signal; and receiving the in-phase component and the quadrature component, A phase error detection unit that outputs a phase error signal according to a phase difference between the first local oscillation wave and the carrier wave, and a level value of at least one of the in-phase component and the quadrature component that is predetermined. Phase synchronization detection means for activating a filter control signal, smoothing by receiving the phase error signal, and filter means for outputting the oscillation control signal according to the following, the filter means: Changing the oscillation control signal in a predetermined range according to activation of the filter control signal,
Costas type digital demodulator. 2. The phase synchronization detection means detects a level value of the in-phase component at a predetermined cycle, and when the level value is less than a predetermined value, a first level determination means that activates a first error signal, and a predetermined level. A first counting means for accumulating the number of activations of the first error signal over a period of, and a level value of the quadrature component is detected at a predetermined cycle. Second level inverting means for activation; second counting means for integrating the number of times of activation of the second error signal over a predetermined period; and integration results of the first and second counting means. The Costas type digital demodulator according to claim 1, further comprising a synchronization determination means for activating the filter control signal in response. 3. A state in which the phase synchronization detecting means receives the output of the synchronization determining means and becomes both at a first potential intermittently in a second predetermined cycle during an active period of the filter control signal. And a waveform shaping means for outputting a first and a second reference potential which repeats a state in which both become a second potential, and the filter means receives the phase error signal at a first input node, A differential amplifier that outputs an oscillation control signal; a first capacitor that is connected between the first input node and an output node of the differential amplifier; and a second input of the differential amplifier. One end is connected to the node,
The second capacitance means whose other end is held at the first potential, and the first and second reference potentials are both the first capacitance.
Of the first potential and the second potential corresponding to both of the above potential and the second potential.
Is supplied to the second input node via a resistor, and the first and second reference potentials are
The reference potential control means for supplying an intermediate potential between the first and second potentials to the second input node in the case of the first potential and the second potential, respectively. Costas type digital demodulator.