JPH05336185A - Digital orthogonal detection demodulator - Google Patents

Abstract

PURPOSE:To obtain orthogonal amplitude outputs or phase outputs by applying required correction to data obtained by direct sampling of an input modulation wave signal concerning the digital detection demodulator demodulating a modulated wave signal transmitting information by phase or amplitude or the both. CONSTITUTION:The demodulator demodulating a modulated wave to transmit information based on a rariation in a phase or amplitude and both of a carrier whose frequency is fc is provided with a sampling means 1, the modulated wave is sampled by using a sampling clock whose frequency is fs and a sampled value is outputted and an amplitude S of the modulated wave is obtained by the sample value. Or the demodulator is provided with sampling means 2, 3 to sample the modulated wave based on two sampling clocks whose frequencies are fsa, fsb with different phases and sample values Sa, Sb are outputted and the two orthogonal components I, Q of the modulated wave are outputted from the sampled values Sa, Sb at conversion means 4 or 5 or a phase phi with respect to the reference phase of the modulated wave is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection demodulator for demodulating a modulated wave signal that transmits information by phase and / or amplitude, and more particularly to an intermediate frequency composed of an n phase phase modulated wave or an amplitude modulated wave. The present invention relates to a digital quadrature detection demodulator that obtains quadrature amplitude output or phase output by correcting data obtained by directly sampling a signal.

When data is transmitted by an electric signal or an optical signal, there is a method of transmitting a signal whose phase and / or amplitude is modulated by information and detecting and demodulating the signal on the receiving side to reproduce the original information. , Is commonly used.

In such a detection demodulator for demodulating a modulated wave signal that transmits information by phase, amplitude, or both, the data obtained by directly sampling the modulated wave signal is subjected to a required correction. In addition, it is desired to be able to obtain quadrature amplitude or phase outputs.

[0004]

2. Description of the Related Art FIG. 24 shows an example of a conventional detection demodulator, wherein 11 and 12 are mixers, 13 is a local oscillator, 14 is a 90 ° hybrid, 15 and 16 are low-pass filters (LPF), 17 , 18 is an analog-digital converter (A / D), 19 is a detector, 20 is a bit timing recovery circuit (BTR), 21 is a clock generator, 2
2 is an automatic frequency control unit (AFC).

The mixers 11 and 12 have an intermediate frequency (IF) signal (carrier frequency f _c, phase φ) applied to one input, and a local signal (frequency f _l ) from the local oscillator 13 to the other input. , 90 ° hybrid 14 and the signals which have been phase-shifted so as to be orthogonal to each other generate signals of the sum and difference frequencies of both signals, but the LPFs 15 and 16 remove the sum frequency components. Therefore, cos {2 consisting of the frequency components of the difference
_{π (f c -f l) +} φ}, sin {2π (f c -f l)
+ Φ} is output from the LPFs 15 and 16 as a baseband signal.

[0006] The A / Ds 17 and 18 convert the orthogonal baseband signal components composed of analog signals from the LPFs 15 and 16 into digital signals according to the clock from the BTR 20 and input them to the detection unit 19. The detection unit 19 performs required detection and demodulation processing such as synchronous detection and differential detection on both signal components to restore the data string DATA transmitted by the IF signal.

The BTR 20 has a phase synchronization circuit (PLL), divides the clock from the clock generator 21,
A clock synchronized with the data string from the detector 19 is generated and supplied to the A / Ds 17 and 18. The AFC 22 synchronizes with the data string from the detection unit 19 and automatically controls the frequency of the clock generator 21, for example.
The clock frequency of the clock generator 21 is synchronized with the data string in 9. The AFC 22 may be used for other purposes. Also, A / D 17 and 18 are BT
The conversion operation is performed only at the data points by the clock from R20 to reduce the current consumption.

[0008]

In the conventional detection demodulator shown in FIG. 24, the mixers 11, 12, LPF1
5,16,90 ° hybrid 14, local oscillator 1
3 is an analog circuit, each element is large,
Not only is it disadvantageous in reducing the circuit scale, but adjustment is difficult and there is a problem in stability.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems of the prior art. In the detection demodulator for demodulating the modulated wave signal that transmits information by phase, amplitude or both, By directly sampling the modulated wave signal so that the quadrature detection component can be taken out, it can be configured by a digital circuit,
Therefore, it is an object of the present invention to provide a digital quadrature detection demodulator capable of reducing the circuit scale.

[0010]

[Means for Solving the Problems] (1) The present invention has a frequency f
_In a demodulator that demodulates a modulated wave that transmits information by changing the phase and / or the amplitude of the carrier wave of _c ,
A sampling means 1 for sampling the modulated wave with a sampling clock of frequency f _s and outputting a sample value is provided, and the amplitude S of the modulated wave is obtained by this sample value.

(2) Further, according to the present invention, in a demodulator for demodulating a modulated wave for transmitting information by changing the phase and / or the amplitude of a carrier wave of frequency f _c , the modulated wave has the same period but different phase. Sampling means 2 and 3 for sampling with two sampling clocks f _{sa and} f _sb and outputting sample values S _{a and} S _b , and sample values S _{a and} S
and a conversion means 4 for outputting two orthogonal components I and Q of the modulated wave from _b .

(3) According to the present invention, in the case of (2), the conversion means 4 calculates from the sample values S _a, S _b when the phases of the sampling clocks f _sa, f _sb have a deviation angle θ from the orthogonal relationship. , I = S _b , Q = S _a / cos θ−S _b tan θ, and two orthogonal components I and Q of this modulated wave are output.

(4) According to the present invention, in the case of (2), the conversion means 4 causes the time difference Δt between the sampling clocks f _{sa and} f _sb.
Where n is a natural number for the carrier frequency f _C and Δt
= (1/4) f _c × (1 + 4n) or Δt = (1 /
4) When there is a relation of f _c × (3 + 4n), I = S _b, Q
= S _a or I = −S _b, Q = S _a , the two orthogonal components I and Q of this modulated wave are output.

(5) Further, according to the present invention, in a demodulator for demodulating a modulated wave for transmitting information by changing the phase and / or the amplitude of a carrier wave of frequency f _c , the modulated wave has the same period but different phase. Sampling means 2 and 3 for sampling with two sampling clocks f _{sa and} f _sb and outputting sample values S _{a and} S _b , and sample values S _{a and} S
_b to φ = arctan {S _a / (S _b cos θ) −t
and a conversion means 5 for obtaining the phase φ of this modulated wave.

(6) According to the present invention, in the case of (5), the conversion means 5 causes the time difference Δt between the sampling clocks f _{sa and} f _sb.
Where n is a natural number for the carrier frequency f _C and Δt
= (1/4) f _c × (1 + 4n) or Δt = (1 /
4) φ = arc when there is a relationship of f _c × (3 + 4n)
tan (S _a / S _b ) or φ = −arctan (S _a
/ S _b ), the phase φ of this modulated wave is obtained.

(7) Further, according to the present invention, in any one of the cases (2) to (6), the sampling clocks f _{sa and} f _sb are generated by the reproduction clock of the BTR 6 which reproduces the bit timing from the output of the conversion means 4 or 5. In addition to the generation, the correction means 7 is provided to correct the phase of the output of the sampling means 2 or 3 or the output of the conversion means 4 or 5 according to the advance or delay of the reproduction clock.

(8) According to the present invention, in the case of (7), the integrating means 8 is provided to integrate the advance and the delay of the reproduction clock of the BTR 6, and the correcting means 7 corrects according to the result of the integration. It is the one.

(9) Further, according to the present invention, in any one of (2) to (6), the sampling clocks f _sa, f _sb are generated by the clock f _s for sampling the modulated wave or the master clock f _m for the baseband signal. Along with
The correction means 9 is provided to set the carrier frequency f _C and the clock f _s.
Or sampling means 2, depending on the frequency difference from f _m
The phase of the output of 3 or the output of the conversion means 4 or 5 is corrected.

(10) In the case of (9), the present invention further comprises an integrating means 10 for integrating the frequency difference between the carrier frequency f _C and the clock f _s or f _m, and correcting according to the result of the integration. The means 9 makes a correction.

[0020]

In the present invention, the input modulated wave signal is sampled at two appropriate timings, and the quadrature detection co
The components corresponding to the s component and the sin component are extracted. In the following, the principle operation of the present invention will be described in terms of sections.

FIG. 1 shows the principle configuration of the present invention. (A) is a configuration for demodulating the amplitude S of a modulated wave, (b) is two orthogonal components I of the modulated wave, The configuration when demodulating Q and (c) show the configuration when demodulating the phase φ of the modulated wave.

(1) In the present invention, as shown in FIG. 1 (a), the most basic structure of a detection demodulator for demodulating a signal of a modulation system in which information is contained in phase and / or amplitude. , The carrier wave frequency f _c is sampled at the frequency f _s by the sampling circuit, and the amplitude S of the modulated wave is sampled.
To get directly.

FIG. 2 illustrates frequency conversion by the sampling method. Now, if the IF signal of frequency f _c is
When sampling is performed at a certain frequency f _s , a frequency component of f _d = | f _s −f _c | appears in the sampling output, as shown in FIG.

When the carrier frequency is f _{c and} the phase of _the carrier is φ, the IF signal is expressed as follows. cos a sample with (2πf _c t + φ) ... This frequency f _s, the rewritten _{equation, cos (2πf c t + φ} ) = cos {2π (f s + f d) t + φ} However f _d = f _c -f _s f _c / 2 <f _s <2 * f _c

The sampling period is T _s = 1 / f _s , and the timing is t = t _s * k = k / f _s (k is a natural number). Substituting this into _{equation, cos {2π (f s +} f d) t s * k + φ} = cos {2π (f s + f d) k / f s + φ} = cos {2πk (1 + f d / f s) + φ} …

Since k is a natural number, the first term 1 in cos which is a trigonometric function in the above equation can be eliminated, so the equation can be expressed as follows. cos (2πkf _d / f _s + φ) ... Reexpressing this as a function of t, cos (2πf _d t + φ).

As is clear from the equation, the IF signal cos
The frequency f _d obtained when (2πf _c t + φ) is sampled at the frequency f _s has the phase information φ of the original carrier frequency f _c as it is. On the contrary, by knowing the phase of the frequency component f _d , the original IF signal f _c
You can know the phase of.

(2) Further, in the present invention, as shown in FIG. 1 (b), in the detection demodulator for demodulating the signal of the modulation system in which the information is included in the phase and / or the amplitude, the period is the same. The modulated wave is sampled by two clocks having different phases, and the obtained sample value is converted to obtain two orthogonal components of the modulated wave.

Two orthogonal amplitude components are required as the information indicating the phase. Therefore, the IF signal of frequency f _c , which is a modulated wave, is sampled at the timings of two clocks f _{sa and} f _sb having the same period but different phases, so that the sample values S _{a and} S _b obtained are modulated. Obtain two orthogonal components I and Q of the wave.

(3) Further, in the present invention,
In the demodulator, a carrier frequency f is provided by providing a converter.
_CSampling clock f for the modulated wave of_sa,f_sb
Is obtained when the phase of is deviated by θ from the orthogonal relationship.
Pull value S_a,S_bTherefore, I = S _b, Q = S_a/ Cos θ-
S_borthogonal by performing the transformation of tan θ
Try to get two components.

FIG. 3 shows the sample timing of the modulated wave and the phase plane. (A) shows the relationship between the modulated wave of the carrier frequency f _C and the sampling clocks f _{sa and} f _sb (however, the modulated wave). The phase relationship between the sampling clock and the sampling clock is not written correctly), and (b) shows the sampled values S _{a and} S _b in this case on the phase plane. In addition, FIG. 4 explains the derivation of the quadrature amplitude and the phase on the phase plane.

Both sample values S _a, S on the phase plane
The deviation angle θ from the orthogonality of _b can be obtained from the phase difference (time difference) between the modulated wave f _c and the sampling clocks f _{sa and} f _sb . Sampling clock f _sa, f _sb
And the timing of sampling t _sa, and t _sb by, when the time difference between Delta] t, respectively sampled _{data, S a = cos (2πf c} t sa + φ) ... S b = cos (2πf c t sb + φ) = cos {2πf _c (t _sa + Δt) + φ} = cos (2πf _c t _sa + 2πf _c Δt + φ) ... Therefore, the phase difference between the sample values S _{a and} S _b is θ ′ = 2.
πf _c Δt. Therefore, the deviation θ from the orthogonal relationship between the sample values S _{a and} S _b is as follows. θ = π / 2−θ ′ = π / 2−2πf _c Δt

The sample value S _a, thus obtained _,
From S _b and the phase difference θ, two orthogonal amplitude components based on the phase at the sample value S _a or S _b can be geometrically obtained. Here, based on the sample value S _b , both amplitude components are I = S _b Q = S _a / cos θ−S _b tan θ.

FIG. 5 shows a phase plane when the phase relations are different. The symbols indicate the same as in FIG. 3, and both amplitude components I and Q and the phase angle θ are also shown. The same can be obtained.

(4) In the present invention, in the demodulator shown in (2), especially the carrier frequency f of the modulated wave is
_c and the time difference Δt between the sampling clocks f _{sb and} f _sb
, Δt = (1/4) fc × (1 + 4n) (n is a natural number) or Δt = (1/4) fc × (3 + 4n), so that I = S _b , Q = S _The circuit configuration is simplified by setting _a or I = −S _b and Q = S _a .

The time difference Δt between the frequency f _{c of the} modulated wave and the sampling clocks f _{sa and} f _sb is Δt = (1/4) fc
When there is a relationship of × (1 + 4n) (n is a natural number), the sample values S _{a and} S _b represent the amplitude of the orthogonal component as they are.

This is the same when θ = 0 in the phase plane shown in FIG. That is, in this case, 2π
f _c Δt = π / 2. Substituting this into the above equations, S _a = cos (2πf _c t _sa + φ) S _b = cos (2πf _c t _sb + φ) = cos {2πf _c (t _sa + Δt) + φ} = cos {2πf _{c t sa + (π / 2} ) + φ} = sin (2πf c t sa + φ} Therefore _{I = S b, Q = S} a

Similarly, the time difference Δt between the frequency f _c of the modulated wave and the sampling clocks f _{sa and} f _sb is Δt = (1 /
4) When fc × (3 + 4n) (n is a natural number), the sample values S _{a and} S _b are equal to the state of θ = π, so that the orthogonal components I and Q are inverted by inverting the sign of I.
Can be asked. That is, I = −S _b , Q = S _a

(5) Further, in the present invention, as shown in FIG. 1 (c), in the detection demodulator for demodulating the signal of the modulation system in which the information is included in the phase and / or the amplitude, Then, sampling is performed with two clocks f _{sa and} f _sb having the same period but different phases, and φ = arctan {S _a / (S _b cos θ) −tan from the obtained sample values S _{a and} S _b.
The phase φ of the modulated wave is obtained by performing the conversion represented by θ}.

That is, the phase φ of the modulated wave f _c with reference to the sampled value S _b is as shown in FIG. 4, tan φ = OQ / OI = (OP / cos θ−OI tan θ) / OI = OP / (OI cos θ) Since −tan θ, φ = arctan {S _a / (S _b cos θ) −tan θ} can be obtained.

(6) Further, in the present invention,
In the demodulator, especially the carrier frequency f of the modulated wave
_cAnd sampling clock f_sa,f_sbAccording to the phase of
The difference Δt is Δt = (1/4) fc × (1 + 4n) (n
Is a natural number) or Δt = (1/4) fc × (3 + 4n)
By making the relationship φ = arctan (S_a/
S _b) Or φ = −arctan (S_a/ S_b)age
To simplify the circuit configuration.

In this case, Δt = (1/4) fc × (1
+ 4n), θ = 0, and Δt = (1/4) fc
Since θ = π when × (3 + 4n), according to the above equation, when the phase angle θ = 0, φ = arctan (S
_a / S _b ), and when the phase angle θ = π, φ = −arc
tan (S _a / S _b ).

(7) In the present invention, (1) to
In the demodulator shown in any one of (6), a clock f _s for sampling the modulated wave or a clock for creating the sampling clocks f _{sa and} f _sb is provided with a clock generator for sampling, I will supply it from now on.

Clock f for sampling the modulated wave_s,Also
Is the sampling clock f_sa,f _sbFor creating
The clock is provided by the sample clock generator
Therefore, select the sampling clock to any frequency.
be able to.

(8) Further, in the present invention, (1) to
In the demodulator shown in any one of (6), the clock f _s for sampling the modulated wave or the clock for creating the sampling clocks f _{sa and} f _sb is the master clock for processing the baseband signal. It is created by dividing f _m .

Clock f for sampling the modulated wave_s,Also
Is the sampling clock f_sa,f _sbFor creating
A clock for processing the baseband signal.
Clock f from the clock generator_mDivide by to create
You can This eliminates the need for one oscillator
Therefore, it is possible to reduce the hardware scale.
It

(9) Further, in the present invention, (1) to
In the demodulator shown in any one of (6), the bit timing of the transmission signal is extracted as a clock f _s for sampling the modulated wave or a clock for creating the sampling clocks f _{sa and} f _sb. Use the recovered clock from the (bit timing recovery circuit).

Clock f for sampling the modulated wave_s,Also
Is the sampling clock f_sa,f _sbFor creating
Extract the bit timing of the transmission signal as a clock
The recovered clock from the BTR can be used. This
This reduces the hardware scale by omitting the oscillator.
And A / D converter for A / D converting the input signal
The operating speed of can be reduced.

(10) Further, in the present invention, in the demodulator shown in (9), the phase of the demodulated signal is changed by changing the sampling point for the modulated wave based on the jitter of the reproduced clock from the BTR. The change is made by adding a correction to the demodulation phase according to the integral value of the deviation of the sampling points, so that the demodulation output of the correct phase is obtained.

6A and 6B are diagrams for explaining the change in the phase of the sample point due to the jitter and the correction method thereof. FIG. 6A shows the change in the phase of the sample point due to the jitter, and FIG. 6B shows the correction method. Shows.

Using the clock reproduced by the BTR
Sampling clock f_sa,f _sbIf you create
The BTR collects data at the center of the eye pattern
Since it works like a crowd, it always has jitter. So
Therefore, the sampling clock f_sa,f_sbAlso has jitter
The phase of the sampled point is the unit of jitter resolution.
It changes with. The phase change due to jitter in this case is
Like

Now, assuming that the time change based on the jitter at the sample timing from the BTR is ± t _j , the phase of the sample point when there is no jitter is S, and the phase of the sample point changed by the jitter is S ′. , the _{S = 2πf c t s + φ} S '= 2πf c (t s ± kt j) + φ = 2πf c t s ± 2πf c kt j + φ. Here, k indicates the amount of movement of the sample point integrated from the initial state.

Since the carrier frequency f _{c of the} modulated wave and the time change ± t _j of the sample timing are known, it is possible to obtain the demodulated output of the correct phase by performing the correction of subtracting ± 2πf _c kt _j from the phase of S ′. You can

FIG. 7 shows a correction circuit for phase change due to jitter, and 30 is a phase correction section for correcting the phase of demodulated data. In the BTR 31, the clock lead / lag determination unit 32 causes the clock lead / lag due to jitter,
Up / down (U / D) counter 33 that determines the delay
Integrates the time change amount of the sample timing by counting up or down according to the determined advance and delay. The correction data selection unit 34
Based on the integration result of the U / D counter 33, the correction data for performing the phase correction of the demodulation data is selected. The timing adjustment delay unit 35 controls the phase correction unit 30 based on the selected correction data, whereby the phase correction of the data is performed in the phase correction unit 30 and the corrected demodulation data is output.

(11) Further, in the present invention, in the demodulator shown in (9), particularly when the differential detection is used,
Although the phase of the demodulated signal changes due to the variation of the sampling point for the modulated wave based on the jitter of the recovered clock from the BTR, the demodulation phase is corrected according to the difference from the previous sample value. To obtain a demodulated output with the correct phase.

FIG. 8 illustrates a correction method in the case of differential detection. Sample clocks f _sa, f having a phase difference of 90 ° with respect to the carrier frequency f _c of the modulated wave
Detection demodulation is performed by sampling with _sb . However, based on the operation of the BTR, the sampling clocks f _{sa and} f _sb have a phase lead _{and a} lag as shown in the figure, and the sampled data The phase also changes.

At this time, when a phase change occurs in the sampling clock, the phase of the sample data is changed correspondingly, so that the phase becomes the same as the immediately preceding data. Therefore, the delay detection result is always 0. Becomes

FIG. 9 shows a correction circuit for a phase change at the time of differential detection. The same components as those in FIG. 7 are designated by the same numbers. 1 based on jitter at the time of differential detection
Since only the change from the phase of the immediately preceding data needs to be corrected, the operation is the same as in the case of FIG. 7 except that the U / D counter for performing the integration operation is unnecessary.

(12) In the present invention, the phase of the sampled value is based on the fact that the carrier frequency f _c and the master clock f _m for the baseband signal are not synchronized because of the frequency difference in the demodulator. By adding a correction corresponding to the frequency difference to the demodulated signal for the deviation,
Try to get the correct phase.

Since there is a frequency difference between the modulated wave f _c and the master clock f _m for the baseband signal, when sampling is performed with the clock f _s obtained by dividing the master clock,
Since the modulated wave cannot be sampled at the same timing, the phase of the demodulated signal gradually changes.

[0061] deviation of the phase in this case, when the n-th timing (n is a natural _{number) t sn = (1 / f} s) × n , and each sample value _{S 1 = 2πf c t s1 +} φ = 2πf c _{/ t s + φ S 2 =} 2πf c t s2 + φ = (2πf c / t s) × 2 + φ: the _{S n = 2πf c t sn +} φ = (2πf c / t s) × n + φ.

Carrier frequency f_cIs known, so sump
Value S_nFrom the phase of (2πf_c/ T _s) × n
By performing positive, the correct demodulation phase can be obtained.
This is to correct the frequency difference caused by the circuit configuration,
Frequency stability and Doppler shift of transmit / receive local oscillator
It does not correct the frequency difference due to. Correction of the latter
Can be done, for example, by the AFC shown in FIG.
It

FIG. 10 shows a phase correction circuit for the frequency difference, and the same components as those in FIG. 7 are designated by the same numbers. In this case, the frequency difference is counted by the counter 36, and the timing adjustment delay unit 35 controls the phase correction unit 30 by the correction data corresponding to the count value in the correction data unit 37.
The phase of the demodulated data is corrected and the corrected data is output.

(13) Further, in the present invention, the demodulator shown in (12) is not synchronized because there is a frequency difference between the carrier frequency f _c and the master clock f _m for the baseband signal. When the frequency difference is small with respect to the phase shift of the sample value based on the above, the demodulation signal of the correct phase is obtained by pulling the frequency by AFC.

When the frequency difference between the carrier frequency f _c and the master clock f _m for the baseband signal is small and there is no particular problem, the carrier frequency f _c and the baseband signal for the baseband signal are determined by AFC based on the demodulated output signal. It is possible to pull in the frequency difference from the master clock f _m .

(14) Further, in the present invention, in the demodulator shown in (12), there is a frequency difference between the carrier frequency f _c and the master clock f _m for the baseband signal, so that they are not synchronized. Based on, for the phase shift of the sample value, especially in the case of differential detection, by adding to the demodulation phase a correction according to the difference from the previous sample value,
Make sure to obtain the demodulated output with the correct phase.

In the case of differential detection, only the difference from the phase of the immediately previous data need be corrected. The difference from the phase of the immediately preceding data due to the frequency difference is always 2πf _c / f _s , which is constant, so correction can be performed with a constant correction value, and the integrator shown in FIG. 7 is unnecessary. Is.

FIG. 11 shows a phase correction circuit based on the frequency difference at the time of differential detection. The same components as those in FIG. 10 are designated by the same numbers. In this case, the timing adjustment delay unit 35 controls the phase correction unit 30 with the constant correction data in the correction data unit 37 to perform phase correction on the demodulated data that has been delay-detected, and outputs the corrected data. To do.

(15) Further, in the present invention, in the detection demodulator for demodulating the signal of the modulation system in which the information is included in the phase and / or the amplitude, the modulated wave frequency f _c and the master clock f for the baseband signal f _m and f _m =
_{(F c / 4) (1} + 2n) * k (k is a natural number) so as to become the relationship, so as to obtain a demodulated output with a constantly correct phase.

The carrier frequency f _{c of the} modulated wave and the master clock f _m for the baseband signal are f _m = (f _c /
4) When there is a relationship of (1 + 2n) * k (k is a natural number), the modulation wave frequency f _c and the master clock f _m are always synchronized, so a phase correction circuit is not required and the circuit configuration is simple. become.

[0071]

FIG. 12 shows an embodiment (1) of the present invention, in which 41 is an analog-digital converter (A /
D). As explained in the action section (1), A
/ D41 can obtain the demodulation output S by sampling the input IF signal composed of the modulated wave of the carrier frequency f _{c at} the frequency f _s in the A / D 41 and extracting the amplitude of the modulated wave. At this time, frequency conversion using an analog signal is not required.

FIG. 13 shows an embodiment (2) of the present invention, in which 42 and 43 are analog-to-digital converters (A / D), and 44 is a converter for converting a sample value into an orthogonal demodulation output. Is.

As described in the section of action (2), A
/ D42 and 43 sample the input IF signal consisting of the modulated wave of the carrier frequency f _c by the sampling clocks f _{sa and} f _sb to generate sample values S _{a and} S _b. By converting S _{a and} S _b , two orthogonal components I and Q of the modulated wave are demodulated and output.

FIG. 14 shows a modification of the embodiment (2), in which 45 is an analog-digital converter (A /
D) and 46 are OR circuits (OR), and 47 and 48 are flip-flops (FF).

In FIG. 14, A / D 45 is a carrier
Frequency f_cThe input IF signal consisting of the modulated wave of
Sampling clock f given via 46_sa,f
_sbSample time-divisionally and output sample value
However, the FFs 47 and 48 have the sampling clock f_sa,f
_sbThe sampled value is latched according to _a,
S_bBy outputting the two orthogonal components of the modulated wave
Demodulate I and Q.

According to the embodiment shown in FIG. 14, since one analog-digital converter is used in a time division manner for sampling, the circuit scale can be reduced.

FIG. 15 shows another modification of the embodiment (2), in which the same parts as those in FIG. 14 are indicated by the same numbers, and 65 is a bit timing reproduction for reproducing the bit timing from the demodulation output. The circuit (BTR) 66 is a read only memory (ROM).

As described in the paragraph (10) of the operation, as a clock for creating the sampling clocks f _{sa and} f _sb for sampling the modulated wave, the BTR (bit timing reproduction circuit) for extracting the bit timing of the transmission signal is used. ) From the BTR, the phase of the demodulated signal changes when the sampling point for the modulated wave fluctuates based on the jitter of the recovered clock from the BTR, and the value corresponding to the deviation of the sampling point is output. By having a converter for
To get. Note that the phase φ can be output as the demodulation output.

As the converter in this case, the sample value S
It is possible to use the ROM 66 that generates corrected demodulated data from _a and S _b and the phase shift between the carrier frequency f _c and the sampling clock from the BTR 65.

FIG. 16 shows an embodiment (3) of the present invention, in which the same components as those in FIGS. 13 and 14 are designated by the same reference numerals.

As described in the section (3) of the operation, when the phases of the sampling clocks f _{sa and} f _sb are deviated from the orthogonality by the angle θ with respect to the input IF signal composed of the modulated wave of the carrier frequency f _c , A / D45 time-divisionally samples the input IF signal by the sampling clocks f _{sa and} f _sb provided via the OR circuit 46, and outputs sample values, and the FFs 47 and 48 output the sampling clocks f _{sa and} f s. By latching the sample value according to _sb , the sample value S _a, S _b is output, and the converter 44
From the sampled values S _a, S _b , I = S _b , Q = S _a / c
By applying the conversion of os θ-S _b tan θ,
Demodulated outputs I and Q consisting of two orthogonal components are obtained.

FIG. 17 shows an embodiment (4) of the present invention, in which the same components as those in FIG. 16 are designated by the same numbers.

As described in the section (4) of the action, the time difference Δt between the sampling clocks f _{sa and} f _sb with respect to the input IF signal composed of the modulated wave of the carrier frequency f _c is
When Δt = (1/4) fc × (1 + 4n) (n is a natural number) or Δt = (1/4) fc × (3 + 4n), the A / D 45 outputs the input IF signal to the OR circuit 46. Sampling clocks f _{sa and} f _sb , which are given via
The FFs 47 and 48 output the sample values S _{a and} S _b by latching the sample values according to the sampling clocks f _{sa and} f _sb , and the converter 44 outputs the sample values S _{a and}
From S _b , I = S _b , Q = S _a or I = −S _b , Q =
By outputting as S _{a, a} demodulation output composed of two orthogonal components is obtained.

FIG. 18 shows an embodiment (5) of the present invention, in which the same elements as those in FIG. 17 are indicated by the same numbers, and 49 is a converter for converting the sampled value into the phase of the modulated wave. is there.

As described in the section of action (5), A
The / D 45 time-divisionally samples the input IF signal by the sampling clocks f _{sa and} f _sb having the same cycle and different phases, which are given through the OR circuit 46, and outputs sample values, and the FFs 47 and 48. Latches the sample values according to the sampling clocks f _{sa and} f _sb to output the sample values S _{a and} S _b , and the converter 49
From the sampled values S _a, S _b , φ = arctan {S _a
The phase φ of the modulated wave is output by performing the conversion of / (S _b cos θ) -tan θ}.

FIG. 19 shows an embodiment (6) of the present invention, in which the same components as those in FIG. 18 are designated by the same reference numerals.

As described in the section (6) of action,
Carrier frequency f_cFor the input IF signal composed of
Sampling clock f_sa,f_sbThe time difference Δt of
Δt = (1/4) fc × (1 + 4n) (n is a natural number)
Or Δt = (1/4) fc × (3 + 4n)
At this time, the A / D 45 outputs the input IF signal to the OR circuit 46.
Sampling clock f given via_sa,f_sbTo
Therefore, sample in a time-sharing manner and output the sample value,
The FFs 47 and 48 use the sampling clock f_{sa ,}f_sbTo
Depending on the sample value,
Value S_a,S_bAnd the converter 49 outputs the sample value S_a,
S_bTherefore, φ = arctan (S_a/ S _b) Or φ =
-Arctan (S_a/ S_b) Is output as
Thus, the phase φ of the modulated wave is output.

FIG. 20 shows an embodiment (7) of the present invention. The same parts as those in FIG. 19 are shown by the same numbers, 51 is a read only memory (ROM), 52 is a clock generator, 53 is a BTR, 54 is an up / down (U / D) counter, 55 is a jitter phase correction data section,
56 is an addition unit, 57 is a counter, 58 is a frequency difference correction data unit, 59 is an addition unit, and 60 is an AFC.

As described in the section of action (1), A
/ D45 obtains the amplitude of the modulated wave by sampling the IF signal of frequency f _c . At this time, the OR circuit 46
Since the sampling clocks f _{sa and} f _sb given by the above are shifted in time, the A / D 45 is used in a time division manner.
The FFs 47 and 48 separate the data sampled by the sampling clocks f _{sa and} f _sb into sample values S _{a and} S _b .

As described in the item (5) of the operation, the sample values S _{a and} S _b, which are amplitude changes, are converted into the phase φ by the converter composed of the ROM 51.

Item of action (8)_,As explained in (9)
The sampling clock f_sa,f _sbIn the base van
The master clock for the master signal, the clock from the BTR53.
Use the imming signal. The clock generator 52
At this time, a clock is supplied to the BTR 53.

As explained in the section of action (10), B
Based on the operation of TR53, when the demodulation phase changes due to the shift of the sampling points, the U / D counter 54
In the BTR 53, the time change of the sampling timing due to the jitter in the BTR 53 is integrated, and in the jitter phase correction data unit 55, the correction data for performing the phase correction of the demodulation data is selected based on the integration result, and in the addition unit 56. , By adding the selected correction data to the output of the ROM 51, the phase change due to the jitter is corrected.

Alternatively, as explained in the section (12) of the operation, since there is a frequency difference between the carrier frequency f _c and the master clock for the base band, when the sample data is out of phase, the counter 57 causes the frequency difference. And the correction data for phase correction of the demodulation data is selected in the frequency difference correction data unit 58 based on the integration result, and the selected correction data is added to the output of the ROM 51 in the addition unit 59. By doing so, the phase change due to the frequency difference is corrected.

Alternatively, as described in the operation (13), when the frequency difference between the carrier frequency f _c and the master clock for the baseband signal is small, the AFC 60 pulls in this frequency difference to obtain the correct phase. To obtain the demodulated signal of.

In the embodiment of FIG. 20, the ROM 5
Instead of obtaining the output of the phase φ from 1, two orthogonal components I and Q are output, and the correction based on the advance / delay of the BTR 53 and the correction based on the frequency difference are orthogonal to each other.
You may make it carry out with respect to each of the components I and Q.

FIG. 21 shows an embodiment (8) of the present invention, in which the same components as in FIG. 20 are designated by the same reference numerals, 61 is a delay circuit (D), and 62 is an adder.

The points described in the paragraphs (1), (5), (8), (9) and (13) of the operation are the same as in the embodiment of FIG. Action term (1
As described in 1), when the phase of the demodulated signal changes based on the jitter of the recovered clock from the BTR,
When the differential detection is used, only the change from the phase of the immediately preceding data based on the jitter needs to be corrected, and thus the BT
In R53, correction data for performing phase correction of demodulation data is selected in addition to the jitter phase correction data unit 55 without integrating the time change of sampling timing due to jitter, and the correction data selected by the addition unit 56 is selected. Is added to the output of the ROM 51 to correct the phase change due to the jitter.

As described in the section (14) of the operation, when there is a phase shift of the sample value due to the frequency difference between the carrier frequency f _c and the master clock f _s for the baseband signal, In the case of differential detection, only the difference from the phase of the immediately preceding data needs to be corrected, but the difference from the phase of the immediately preceding data due to the frequency difference is always 2πf.
_{Since c} / f _s is constant, the correction can be performed with a constant correction value. Therefore, the addition unit 59 adds the constant correction data in the frequency difference correction data unit 58 to the delay-detected demodulation data. Phase correction is performed and the corrected data is output. When the phase change due to the jitter is not corrected, the frequency difference correction data is added in the adding section 62 via the delay circuit 61,
Generates a phase corrected output.

In the embodiment of FIG. 21, the ROM 5
Instead of obtaining the output of the phase φ from 1, two orthogonal components I and Q are output, and the correction based on the advance / delay of the BTR 53 and the correction based on the frequency difference are orthogonal to each other.
You may make it carry out with respect to each of the components I and Q.

FIG. 22 shows an embodiment (9) of the present invention, in which the same components as those in FIG. 21 are designated by the same numbers.

The points described in the paragraphs (1), (10), (11), and (13) of the operation are the same as those of the embodiment shown in FIGS. 20 and 21.
As described in the section (6) of the action, the carrier frequency f _c of the modulated wave and the time difference Δt due to the phases of the sampling clocks f _{sa and} f _sb are Δt = (1/4) fc × (1+
4n) (n is a natural number) or Δt = (1/4) fc ×
In the relationship of (3 + 4n), φ = arctan (S _a /
The circuit configuration can be simplified by outputting the phase change φ from the ROM 51 as S _b ) or φ = −arctan (S _a / S _b ).

As described in the section (15) of the action, the carrier frequency f _c of the modulated wave and the master clock f _m for the baseband signal are f _m = (f _c / 4) (1
When there is a relationship of + 2n) * k (k is a natural number), the modulated wave frequency f _c and the master clock f _m are always synchronized, so that the phase correction circuit is not required and the circuit configuration is simplified.

In the embodiment of FIG. 22, the ROM 5
Instead of obtaining the output of the phase φ from 1, the orthogonal two components I and Q are output, and the correction based on the advance and delay of the BTR 53 is performed on the orthogonal two components I and Q, respectively. Good.

FIG. 23 shows an embodiment (10) of the present invention, in which the same components as in FIG. 20 are designated by the same reference numerals, 63 is a clock generator for samples, and 64 is a clock generator 63. It is a frequency divider that divides the clock of.

The points described in the paragraphs (1), (6), (10), (12) and (13) of the operation are the same as in the embodiment of FIG. Action term
As described in (7), the clock for generating the sampling clocks f _{sa and} f _sb for sampling the modulated wave is the clock generator 63 for sampling and the frequency divider 6
Since 4 is provided and is supplied from now on, the sampling clock can be selected to an arbitrary frequency.

In the embodiment of FIG. 23, the ROM 5
Instead of obtaining the output of the phase φ from 1, two orthogonal components I and Q are output, and the correction based on the advance / delay of the BTR 53 and the correction based on the frequency difference are orthogonal to each other.
You may make it carry out with respect to each of the components I and Q.

[0107]

As described above, according to the present invention, a detection demodulator for demodulating a signal of a modulation system in which information is contained in phase and / or amplitude is obtained by directly sampling an input modulated wave signal. A quadrature amplitude output or phase output can be obtained by applying a required correction to the obtained data. The detection demodulator of the present invention can be configured with a digital circuit, and therefore, the circuit scale can be reduced as compared with the conventional detection demodulator using an analog circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, in which (a) is a configuration when demodulating an amplitude S of a modulated wave, and (b) is demodulating two orthogonal components I and Q of the modulated wave. The configuration in the case, (c) shows the configuration for demodulating the phase φ of the modulated wave.

FIG. 2 is a diagram illustrating frequency conversion by a sampling method.

FIG. 3 is a diagram showing a sample timing of a modulated wave and a phase plane.

FIG. 4 is a diagram illustrating derivation of quadrature amplitude and phase on a phase plane.

FIG. 5 is a diagram showing a phase plane when the phase relationship is different.

FIG. 6 is a diagram illustrating a change in the phase of a sample point due to jitter and a correction method thereof.

FIG. 7 is a diagram showing a circuit for correcting a phase change due to jitter.

FIG. 8 is a diagram illustrating a correction method in the case of differential detection.

FIG. 9 is a diagram showing a correction circuit for a phase change at the time of differential detection.

FIG. 10 is a diagram showing a phase correction circuit for a frequency difference.

FIG. 11 is a diagram showing a phase correction circuit based on a frequency difference at the time of differential detection.

FIG. 12 is a diagram showing an embodiment (1) of the present invention.

FIG. 13 is a diagram showing an embodiment (2) of the present invention.

FIG. 14 is a diagram showing a modification of the embodiment (2).

FIG. 15 is a diagram showing another modification of the embodiment (2).

FIG. 16 is a diagram showing an embodiment (3) of the present invention.

FIG. 17 is a diagram showing an embodiment (4) of the present invention.

FIG. 18 is a diagram showing an embodiment (5) of the present invention.

FIG. 19 is a diagram showing an embodiment (6) of the present invention.

FIG. 20 is a diagram showing an embodiment (7) of the present invention.

FIG. 21 is a diagram showing an embodiment (8) of the present invention.

FIG. 22 is a diagram showing an embodiment (9) of the present invention.

FIG. 23 is a diagram showing an embodiment (10) of the present invention.

FIG. 24 is a diagram illustrating a conventional detection demodulator.

[Explanation of symbols]

 1 Sampling Means 2 Sampling Means 3 Sampling Means 4 Converting Means 5 Converting Means 6 BTR 7 Correcting Means 8 Integrating Means 9 Correcting Means 10 Integrating Means

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[Procedure amendment]

[Submission date] November 19, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 4

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 6

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

(4) According to the present invention, in the case of (2), the conversion means 4 determines that the time difference Δt between the sampling clocks f _sa and f _sb is Δt = (1 where n is a natural number with respect to the carrier frequency f _c . / 4f _c ) × (1 + 4n) or Δt =
When the relationship is (1 / 4f _c ) × (3 + 4n), I =
Two orthogonal components I and Q of this modulated wave are output according to the relation of S _b , Q = S _a or I = −S _b , Q = S _a .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

[0015] (6) The present invention in the case of (5), the conversion means 5, the sampling clock _{f sa,} time difference Delta] t of the _{f sb} is, where n is a natural number with respect to the carrier frequency _{f c,} Δt = (1 / 4f _c ) × (1 + 4n) or Δt =
When the relationship is (1 / 4f _c ) × (3 + 4n), φ =
arctan _(S a / Sb) or φ = -arctan
Due to the relationship (S _a / S _b ), the phase φ of this modulated wave
Is what you get.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

(4) Further, in the present invention, in the demodulator shown in (2), especially the carrier frequency f of the modulated wave is used.
_c and the time difference Δ between the sampling clocks f _sb and f _sb
By setting t such that Δt = (1 / 4fc) × (1 + 4n) (n is a natural number) or Δt = (1 / 4fc) × (3 + 4n), I = S _b , Q = S _a Alternatively, the circuit configuration is simplified by setting I = −S _b and Q = S _a .

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The time difference Δt between the frequency f _{c of the} modulated wave and the sampling clocks f _sa and f _sb is Δt = (1 / 4f
c) × (1 + 4n) (n is a natural number),
The sample values S _a and S _b represent the amplitude of the orthogonal component as they are.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

Similarly, the time difference Δt between the frequency f _c of the modulated wave and the sampling clocks f _sa and f _sb is Δt =
In the case of the relationship of (1 / 4fc) × (3 + 4n) (n is a natural number), the sample values S _a and S _b are equal to the state of θ = π, so that the quadrature component I is inverted by inverting the sign of I. , Q can be obtained. That is, I = −S _b , Q = Sa

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

(6) Further, in the present invention, in the demodulator shown in (5), particularly the carrier frequency f of the modulated wave is used.
_c and the time difference Δt due to the phases of the sampling clocks f _sa and f _sb are Δt = (1 / 4fc) × (1 + 4n)
(N is a natural number) or Δt = (1 / 4fc) x (3 + 4 )
n =), φ = arctan (S
_a / S _b ) or φ = −arctan (S _a / S _b ).
As a result, the circuit configuration is simplified.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

In this case, Δt = (1 / 4fc) × (1
+ 4n), θ = 0, and Δt = (1 / 4fc)
Since θ = π when × (3 + 4n), according to the above equation, when the phase angle θ = 0, φ = arctan (S
_a / S _b ), and when the phase θ, = π, φ = −arc
tan (S _a / S _b ).

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0083

[Correction method] Change

[Correction content]

As explained in the section of action (4),
The time difference Δ between the sampling clocks f _sa and f _sb with respect to the input IF signal composed of the modulated wave of the carrier frequency f _c.
When t has a relationship of Δt = (1 / 4fc) × (1 + 4n) (n is a natural number) or Δt = (1 / 4fc) × (3 + 4n), the A / D 45 outputs the input IF signal to the OR circuit 46. And outputs the sample value in a time-division manner by the sampling clocks f _sa and f _sb , and the FFs 47 and 48 latch the sample value according to the sampling clocks f _sa and f _sb. Output sample values S _a and S _b , and the converter 44 calculates I = S _b and Q = S from the sample values S _a and S _b.
By outputting as _a or I = −S _b , Q = S _a , _a demodulation output composed of two orthogonal components is obtained.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0087

[Correction method] Change

[Correction content]

As described in the section of operation (6),
The time difference Δ between the sampling clocks f _sa and f _sb with respect to the input IF signal composed of the modulated wave of the carrier frequency f _c.
When t has a relationship of Δt = (1 / 4fc) × (1 + 4n) (n is a natural number) or Δt = (1 / 4fc) × (3 + 4n), the A / D 45 outputs the input IF signal to the OR circuit 46. And outputs the sample value in a time-divisional manner by the sampling clocks f _sa and f _sb , and the FFs 47 and 48 latch the sample value according to the sampling clocks f _sa and f _sb. Output sample values S _a and S _b , and the converter 49 calculates φ = arctan from the sample values S _a and S _b.
(S _a / S _b ) or φ = −arctan (S _a /
By outputting as S _b ), the phase φ of the modulated wave is output.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0101

[Correction method] Change

[Correction content]

Action terms (1), (10), (11),
The point described in (13) is the same as the embodiment of FIGS. 20 and 21. As described in the section (6) of the action, the time difference Δt due to the phases of the carrier frequency f _c of the modulated wave and the sampling clocks f _sa and f _sb is
t = (1 / 4fc) × (1 + 4n) (n is a natural number) or Δt = (1 / 4fc) × (3 + 4n),
_{φ = arctan (S a / S} b) or, φ = -arc
The circuit configuration can be simplified by outputting the phase change φ from the ROM 51 as tan (S _a / S _b ).

Claims (10)

[Claims] 1. A demodulator that demodulates a modulated wave that transmits information by changing the phase and / or the amplitude of a carrier wave of frequency f _c , and samples the modulated wave with a sampling clock of frequency f _s to obtain a sample value. A digital quadrature detection demodulator comprising sampling means (1) for outputting and obtaining the amplitude S of the modulated wave by the sample value. 2. A demodulator for demodulating a modulated wave that transmits information by changing the phase and / or the amplitude of a carrier wave of frequency f _c , wherein two sampling clocks f _sa having the same period but different phases are used for the modulated wave. _, the sample values S _a and sampled by f _sb, the sampling means for outputting S _b (2,3), the sample value S _a, orthogonal from S _b of the modulated wave to the two components I, conversion to output the Q A digital quadrature detection demodulator provided with means (4). 3. The conversion means (4) comprises the sampler.
Glock clock f_sa,f _sbThe phase of
Sample value S when having_a,S_bTherefore, I = S_b Q = S_a/ Cos θ-S_btan θ is converted to obtain two orthogonal components I and Q of the modulated wave.
Is output.
Quadrature detection demodulator. 4. The conversion means (4) comprises the sampler.
Glock clock f_sa,f _sbOf the carrier frequency f
_C, Where n is a natural number, Δt = (1/4) f_c× (1 + 4n) or Δt = (1/4) f_cWhen there is a relationship of × (3 + 4n), I = S_b,Q = S_a Or I = -S_b,Q = S_a According to the relation, the two orthogonal components I and Q of the modulated wave are
The digital signal according to claim 2, wherein the digital signal is output.
Quadrature detection demodulator. 5. A demodulator for demodulating a modulated wave that transmits information by changing the phase and / or the amplitude of a carrier wave of frequency f _c , wherein two sampling clocks f _sa having the same period but different phases are used for the modulated wave. _, the sample values S _a and sampled by f _sb, the sampling means (2, 3) for outputting the S _b, the sample value S _a, from _{S b φ = arctan {S a} / (S b cosθ) -tanθ} A digital quadrature detection demodulator comprising: a conversion means (5) for performing the following conversion to obtain the phase φ of the modulated wave. 6. The conversion means (5) comprises the sampler.
Glock clock f_sa,f _sbOf the carrier frequency f
_C, Where n is a natural number, Δt = (1/4) f_c× (1 + 4n) or Δt = (1/4) f_cWhen there is a relationship of × (3 + 4n), φ = arctan (S_a/ S_b) Or φ = -arctan (S_a/ S_b), The phase φ of the modulated wave is obtained by
The digital quadrature detection demodulator according to claim 5, which is a characteristic. 7. The digital quadrature detection demodulator according to claim 2, wherein the conversion means (4)
Or B which reproduces the bit timing from the output of (5)
The sampling clocks f _{sa and} f _sb are generated by the reproduction clock of TR (6), and the output of the sampling means (2, 3) or the conversion means (4) or (5) is generated according to the advance or delay of the reproduction clock. The digital quadrature detection demodulator is provided with a correction means (7) for correcting the phase of the output of FIG. 8. The digital quadrature detection demodulator according to claim 7, further comprising an integrating means (8) for integrating the advance and the delay of the reproduction clock of the BTR, and the correcting means (7) according to the integration result. A digital quadrature detection demodulator characterized in that correction is performed in. 9. The digital quadrature detection demodulator according to any one of claims 2 to 6, wherein the sampling clock f _{sa, is} generated by a clock f _s for sampling a modulated wave or a master clock f _m for a baseband signal _.
f _sb is generated, and the output of the sampling means (2, 3) or the output of the conversion means (4) or (5) is generated in accordance with the frequency difference between the carrier frequency f _C and the clock f _s or f _m . A digital quadrature detection demodulator provided with a correction means (9) for correcting the phase. 10. The digital quadrature detection demodulator according to claim 9, further comprising integration means (10) for integrating a frequency difference between the carrier frequency f _C and the clock f _s or f _m, and the integration result is obtained. A digital quadrature detection demodulator characterized in that the correction means (9) performs a correction accordingly.