JPS5870664A - Msk demodulation circuit - Google Patents

Abstract

PURPOSE:To obtain an MSK demodulating circuit with a simple constitution, reproducing a reference carrier wave and a reference clock at the same time, by constituting a clock tracing circuit with a square circuit and a phase locking circuit. CONSTITUTION:An MSK wave is inputted to an input terminal 1 and also synchronizing detectors 2, 3. Demodulated carrier waves shifted with 90 deg. are inputted from a voltage controlled oscillator 6 to the detectors 2, 3, the output of which is inputted to a multiplier 10. The output of multiplication is squared at a square circuit 21 and inputted to a phase locking loop 27 operated in the clock frequency. The loop 27 reproduces clock signals, the reproduced clock signal is frequency-divided into two at a two-frequency-division circuit 27 and inputted to a multiplier 9. The multiplier 9 multiplies the frequency-divided clock signal from the circuit 27 with the signal from the multiplier 10, and the multiplied output is given to the voltage controlled oscillator 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides transmission MSK (MinimumShiftK)
This invention relates to an MSN demodulation circuit for simultaneously determining the phases of a reference carrier wave and a reference clock on the receiving side based on the following wave.

Conventionally, there has been a circuit of this type as shown in FIG.

In the figure, (1) is the input terminal for the MSK wave, and (2) is! Synchronous detector on the channel side, (March t) Synchronous detector on the Q channel side, (4) and (5) are low-pass filters, (6) is a voltage controlled oscillator whose center frequency is the carrier frequency, (7
) is a 90° phase shifter, (3) is a loop filter, (9) is a multiplier, αO is a Costas loose baseband multiplier to be described later, Q21 is a square circuit, α4 is a subtracter, 04 is a A phase detector, αG is a loop filter, q is a voltage controlled oscillator, and αη is a 90° phase shifter.

Next, the operation will be explained. The input MSK wave is transmitted through the channel-side synchronous detector (2) and the Q-channel side synchronous detector (3).
), synchronous detection is performed using the output of the voltage controlled oscillator (6) whose center frequency is the carrier frequency and the output whose phase is shifted by 90° by the 90° phase shifter (7). Next, the 1-channel and Q-channel signals are converted into baseband signals by low-pass filters (4) and (5), respectively, and then multiplied together by a multiplier αQ.The output of the multiplier αG is clocked by a multiplier (9). It is multiplied by the output of the voltage controlled oscillator αQ whose center frequency is half the frequency, and is smoothed by the loop filter (3), resulting in the phase difference between the carrier of the input MSK wave and the output of the voltage controlled oscillator (5). Generates a proportional error voltage.Loop consisting of the above parts■
is a carrier wave tracking loop, which is called a Costas loop. Next, the outputs of the low-pass filters (4) and (5) are halved by the 2 east circuits aυ and (2), respectively, and then the difference between the two is taken by the subtracter 03. Next, the 8 of the subtracter (to) The output of the voltage controlled oscillator αQ is phase-shifted by 90 degrees using a 900° phase shifter αη, and is phase-detected by a phase detector a, which is then smoothed by a loop filter 05 to generate a hexagonal MSK wave clock and voltage control. An error voltage proportional to the phase difference with the output of the oscillator αQ is generated.The loop 6 consisting of these parts becomes a clock tracking loop.

The above operation will be explained below using formulas. Generally M.S.
The K wave has aspects as PSK, and aI81n-:C
O8 town L +aQCO32”r 51nQl, t
It is expressed as (1). aI'Q takes a value of ±1, T is the clock period, and ω0 is the carrier frequency. At this time, the outputs of the low-pass filters (4) and (5) are allin(k17t Cogφ-1(2Cog
6) 1(fijnφ (2) If the output of the control oscillator α is set as Cog(2ω, t+θ), then the loop filter (
8), a DC voltage proportional to cosθ5in2φ is obtained, and the output of the loop filter QcJ is
A DC heavy pressure proportional to n#cos2φ can be obtained. Therefore, Figure 1 shows one closed degree for determining θ and φ.
It can be thought of as a loop, and locking the loop allows the reference carrier and reference clock to be played simultaneously.

In the MSN demodulation circuit according to the method described above, the circuit for regenerating the clock is divided into both I and Q channels, so it is necessary to adjust the phase difference between both channels, and there are two Since it includes square circuits and subtracters,
It had drawbacks such as a complicated circuit.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by configuring a circuit for regenerating a clock using one square circuit and one phase-locked loop, I, It is an object of the present invention to provide an MSN demodulation circuit that does not require adjustment of the phase difference between Q channels, has a simple configuration, and can simultaneously reproduce a reference carrier wave and a reference clock.

FIG. 2 shows an embodiment of the present invention. In Figure 2,
Those with the same numbers as in Figure 1 have the same functions, 3p is a square circuit, □□□ is a phase detector, (to)
is a loop filter, (to) is a voltage controlled oscillator whose center frequency is the off-clock frequency, (2) is a 90' phase shifter, (4
) is a frequency divider circuit, and 翺 is a phase-locked loop consisting of the above (2) to (to).

Next, the operation will be explained.

The circuit of the present invention is a clock tracking circuit c of the conventional circuit shown in FIG.
3]) is not divided into both I and Q channels, but is constructed with one square Q-channel and a phase-locked loop. Since the carrier tracking loop (1) is the same as the conventional circuit shown in FIG. 1, it will not be described here. In Figure 2,
The output of the multiplier tIQ is squared by the two-way circuit 1) and further multiplied by the output of the voltage controlled oscillator (2) with a phase shift of 90'' by the phase detector. Note that the center frequency of the voltage-controlled oscillator (c) is equal to the clock frequency (4ω1.).Next, the output of the phase detector is smoothed by the loop filter (c), and the input MSK wave clock and voltage-controlled oscillator (c) are smoothed. It generates a DC error voltage proportional to the phase difference between the outputs of the oscillator (6), making it possible to track the clock.The output of the voltage controlled oscillator (6) is
os(ωc1→φ), the output of the voltage controlled oscillator is cos
(4ωTt+20), a DC voltage proportional to cosθs in2φ is obtained at the output of the loop filter (3), and a DC voltage proportional to cosθs in2φ is obtained at the output of the loop filter (to).
A DC voltage proportional to in2θ is obtained. Therefore, the input M
It becomes possible to simultaneously reproduce the reference carrier wave and the reference clock of the SK wave. By the way, since the clock regeneration circuit shown in FIG. 2 is not divided into both the l and Q channels as shown in FIG. The configuration is simple.

Although the above embodiment has been described in terms of demodulation of MSK waves, the same effects as in the above embodiments can be achieved also in demodulation of T FM (Tamed FM) waves.

As described above, according to the present invention, the clock regeneration circuit is
Since it is composed of two square circuits and a phase-locked circuit, I,
There is no need to adjust the phase difference between both Q channels, and the circuit configuration can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional MSN demodulation circuit for simultaneously determining the phases of a reference carrier wave and a reference clock of an MSK wave on the receiving side, and FIG. 2 is a circuit diagram of an MSN demodulation circuit according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a demodulation circuit. (7)...Costas loop, (IG...baseband multiplier, 121)...square circuit, wire...
Phase-locked loop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kazuno

Claims (1)

[Claims] (1) MSKl using a Costas loop to simultaneously determine the phases of the reference carrier and reference clock when regenerating the reference carrier and the reference clock from the MSK modulated transmission wave [In the 99 circuit, the Costas for carrier tracking described above The output of the baseband multiplier in the loop is 2
1. An MSN demodulation circuit comprising: one squaring circuit for multiplying the squaring circuit; and a phase-locked loop for tracking the phase of a reference clock signal included in the output of the squaring circuit.