JP2876906B2 - Unique word detection circuit and demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a unique word for detecting a reference burst, establishing a received frame and establishing reception synchronization in TDMA communication and the like, and detecting a unique word contained in the reference burst in the process. The present invention relates to a detection circuit and a demodulation circuit.

[0002]

2. Description of the Related Art In digital communication, in order to establish word synchronization of a binary sequence, a fixed pattern of a fixed bit length, that is, a so-called Unique Word (UW), inserted at a fixed period in a bit sequence is detected. It is fundamental to do. FIG. 3 shows the conventional unique word detector.

[0003] The conventional unique word detection circuit shown in FIG. 3 employs mixers 3 and 4 to which received signals are respectively input.
And a local oscillator 1 for inputting a reference carrier having a frequency approximating the frequency of the carrier of the received IF signal to the mixer 3 as it is, Phaser 2 and mixers 3 and 4
A / D converters 6 and 7 for A / D converting the two-phase modulated waves, a sample pulse generator 5 for outputting a sampling signal to the A / D converters 6 and 7, and an A / D converter A demodulation circuit 14 for demodulating a signal from the output digital data of 6, 7; shift registers 15 and 16 for shifting a reproduction data sequence of the demodulation circuit 14; output signals of these shift registers 15 and 16 and generation of a unique word pattern. Exclusive ORs 17 _{1 to} 17 _2n for taking an exclusive OR with each output signal from the device 18 and these exclusive ORs 17 _{1 to} 17 _2n
An adder 19 for adding the ₁ to 17 _2n output signal, from the threshold detector 20 for performing threshold detection.

[0004] The operation of the above configuration is the same as that of the shift register 1 receiving the reproduced data sequence from the demodulation circuit 14.
5 and 16 have N stages (N is a natural number), and N is the same as the unique word pattern length. The exclusive OR 17 _{1 to} 17 _2n detects the coincidence of the parallel output and the output of the unique word pattern generator 18 for each bit, and calculates the sum of the number of matching bits by the exclusive ORs 17 _{1 to} 17 _2n. It is determined by the adder 19 that when the number of additions is larger than a predetermined threshold value, it is determined that a unique word has been detected.

[0005]

However, the above-described conventional unique word detection circuit has a simple structure, but has the following disadvantages. It is an absolute condition of unique word detection that the data is correctly reproduced in the demodulation circuit 14, but recent digital communication uses an error correction code as typically seen in mobile satellite communication. For example, since good channel quality can be obtained even at a low C / N ratio, it is required to be used under extremely low C / N conditions.
Under such low C / N ratio conditions, it is very difficult for the demodulation circuit 14 to capture signals. Therefore, in the conventional unique word detector, if the C / N ratio is poor, the demodulation circuit 1
4 does not operate correctly, the unique word cannot be detected forever, and communication cannot be performed in many cases.

Therefore, the present invention solves the above-mentioned drawbacks of the conventional unique word detection circuit, and can more surely detect the unique word regardless of the operation of the demodulator.
It is an object of the present invention to provide a unique word detection circuit and a demodulation circuit that can help to speed up synchronization of a demodulation circuit.

[0007]

According to a first aspect of the present invention, there is provided an IF signal using two reference carriers having different phases of π / 2 which are close to the carrier frequency of a received IF signal. Is a complex baseband modulation comprising a real part and an imaginary part, and a unique word detection circuit having A / D converters for the real part and the imaginary part, which samples the complex baseband signal with a sample pulse and converts it into a digital value. A first and a second shift register for holding the output of the real part and imaginary part A / D converters in N samples and a pipeline format, and a unique word generator for generating a unique word in a complex signal format. , The complex multiplication of the nth (n = 0, 1, 2,..., N−1) th output of the unique word generator and the nth outputs of the first and second shift registers. N complex multipliers to be performed respectively, a filter bank which receives the outputs of the N complex multipliers and performs separation for each frequency band, and receives the N outputs of the filter banks to calculate the absolute value It is determined that a unique word is detected when a value equal to or greater than a specified value is obtained in a specific element filter output of the filter bank, a unique word presence / absence detection signal is output, and a carrier frequency error signal is calculated based on the frequency position of the element filter. And a comparing circuit for outputting.

According to the present invention, as a means for speeding up the establishment of the synchronization of the demodulation circuit using the first means, the two reference carriers having different phases of π / 2 which are close to the carrier frequency of the received IF signal are used. An A / D converter for a real part and an imaginary part that performs complex baseband modulation of the IF signal including a real part and an imaginary part, samples the complex baseband signal with a sample pulse, and converts it into a digital value; A / D converter outputs for the real part and the imaginary part are output to a phase synchronization circuit including a complex multiplier, a carrier phase detector, a loop filter, a first adder, a numerical control oscillator, a cosine value generation ROM, and a sine value generation ROM. A demodulation circuit for demodulating the received IF signal by inputting a second sequence output of the complex multiplier to the first and second shift registers according to claim 1;
Obtaining a unique word presence / absence detection signal and a carrier frequency error signal, a unique word detector including a unique word generator, N complex multipliers, a filter bank, and a comparison circuit; A latch circuit that holds the word presence / absence detection signal and an AFC timing signal in synchronization with an AND signal thereof; With
The output of the latch circuit is input to the first adder to assist the synchronization of the phase synchronization circuit.

[0009]

Next, an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a unique word detection circuit according to the present invention. In FIG. 1, the same components as those in the conventional example of FIG. 3 are denoted by the same reference numerals. In FIG. 1, the reception IF
Mixers 3 and 4 to which the modulated signals are respectively input, a local oscillator 1 that generates a reference carrier approximating the carrier frequency of the received IF signal to mixer 3, and outputs the reference carrier as it is. A π / 2 phase shifter 2 that outputs two phase-shifted signals to the mixer 4, mixers 3 and 4 that multiply the received IF signal by reference carriers having different phases, and a two-phase phase of each of the mixers 3 and 4 A / A for a real part which samples a complex baseband signal having a modulated wave as a real part and an imaginary part by a sample pulse input from a sample pulse generator 5 and converts it into a digital display value.
A D converter 6 and an imaginary part A / D converter 7;
A shift register 8 for the real part and a shift register for the imaginary part which hold the digital data output from the converters 6 and 7 in N samples and in a pipeline format (where N represents a unique word pattern length). 9 and a complex unique word pattern composed of a predetermined N-bit real part and imaginary part (the real part pattern and the imaginary part pattern are different) and output to the complex multipliers 10 ₁ to 10 _n . The complex unique word pattern generator 11, the n-th (n = 0, 1, 2,... N-1) th output of the shift registers 8, 9 and the same n-th output of the complex unique word pattern generator 11 Multipliers 101 to ₁ for performing complex multiplication of
0 _n and N of the complex multiplication results of the complex multipliers 10 ₁ to 10 _n
Bank 12 that separates frequency bands to perform frequency numerical analysis on the data of the number of pieces of data, and an absolute value detector 2 that calculates an absolute value from N outputs of the filter bank 12
It is determined that a unique word has been detected due to a value greater than or equal to 11 _{1 to} 21 _n and a specific element filter output of the filter bank 12 from the output of the absolute value detectors 21 _{1 to} 21 _n. A comparison circuit 22 that outputs a signal 40 and outputs a frequency position having an output equal to or higher than the above-described value as a carrier frequency error signal 41, and outputs an element filter output indicated by the signal 41 from the N element filter outputs of the filter bank 12. And a selection circuit 23 for selecting and outputting the selected signal to a signal processing circuit (not shown).

FIG. 2 shows a filter bank 12 used in the present invention.
FIG. As the filter bank 12, a fast Fourier transform, a generalized transmultiplexer demultiplexing circuit, or the like can be used. The operation of the unique word detection circuit of the present invention will be described with reference to FIG. First,
When the N pieces of data in the shift registers 8 and 9 and the complex unique word pattern output from the complex unique word pattern generator 11 match, the outputs of the complex multipliers 10 ₁ to 10 _n sample N single sine waves. It will be. This can be expressed by the following equation.

[0011]

(Equation 1)

## EQU1 ## Here, T is a sample period. Here, W _C and θ _C are the carrier frequency and phase at the outputs of the A / D converters 6 and 7, respectively. Ideally W
_{Although C} = 0, it is not actually 0 due to the difference between the received IF modulation signal and the oscillation frequency of the local oscillator 1. Now, shift registers 8 and 9 have complex values

[0013]

(Equation 2)

Is held.

The unique word generator 11 has a complex unique word pattern

[0016]

(Equation 3)

And outputs it to the complex multipliers 10 ₁ to 10 _n .

Complex multipliers 10 ₁ , 10 ₂ ,..., 1
The output of 0 _N

[0019]

(Equation 4)

[0020]

(Equation 5)

[0021]

(Equation 6)

[0022]

(Equation 7)

## EQU1 ## Therefore, now, when the received input signal matches the unique word pattern,

[0024]

(Equation 8)

In the case where

[0026]

(Equation 9)

## EQU1 ##

That is, there is no other case where only a single harmonic wave is sampled and held for N samples. Therefore, filter bank 12
Thus, as shown in FIG. 2, one large-amplitude signal 45 appears in any of the element filter outputs, so that the unique word detection and the frequency phase shift of the signal can be easily detected. More specifically, assuming that the sample frequency is f ₀ and the unique word pattern length is N (sample), the step frequency Δf in FFT or generalized transmultiplexer is

[0029]

(Equation 10)

The frequency analysis can be performed with the accuracy described above. Here, as N is larger, the bandwidth of each element filter becomes narrower.
The N ratio increases. That is, assuming that the total power at the outputs of the A / D converters 6 and 7 is constant, the output of the filter 12 in which the carrier signal exists, that is, the complex unique word output from the complex unique word pattern generator 11 and the shift registers 8 and 9 When the pattern of the signal output from the terminal matches, the output amplitude becomes relatively large, so that it can be easily detected. Conversely, if the patterns of the shift registers 8 and 9 do not match the unique word, the absolute value detector 21
Outputs _{1 to} 21 _n have substantially the same signal level. Therefore, the signal 45 shown in FIG. 2 is identified by the absolute value detectors 21 _{1 to} 21 _n and the comparison circuit 22, and the unique word presence / absence detection signal 40 and the carrier frequency error signal 41 are output. The selection circuit 23 outputs the signal 4 from the comparison circuit 22.
The element filter output in which the signal 45 appears is selected from each output of the filter bank 12 based on 1 and output to the outside as a signal 42. This signal 42 contains information such as the correlation between the unique word pattern of the complex unique word pattern generator 11 and the received signal.

Next, one application example of the present invention is shown in FIG.
The portion from the local oscillator 1 to the A / D converters 6 and 7 is the same as the circuit configuration described in FIG. 1, but the outputs of the A / D converters 6 and 7 are input to the complex multiplier 30, Further, the complex baseband signal of the complex multiplier 30 is input to a unique word detection circuit 31 and a carrier phase detector 24 for reproducing a carrier phase. The output of the carrier phase detector 24 controls a numerically controlled oscillator (hereinafter NCO) 27 via a loop filter 25 and an adder 26. This N
The output of the CO 27 is input to a cosine value generation ROM 28 and a sine value generation ROM 29.
8. The output of the sine value generation ROM 29 is input to the complex multiplier 30.

The unique word detection circuit 31 and the adder 3
2, the above-mentioned circuit parts other than the latch 33 and the AND 34 are well known in the prior art.
Are shift registers 8 and 9 of the present invention, complex multipliers 10 ₁ to 10 _n , complex unique word pattern generator 11, filter bank 12, and absolute value detectors 21 ₁ to 21 shown in FIG.
1 _n , a comparison circuit 22, and a selection circuit 23. Although the complex multiplier 30 operates as a synchronous demodulator, when the unique word detector 31 of the present invention detects a unique word and outputs the detection presence / absence signal 40 to an external frame synchronization circuit, the frame synchronization circuit 30 An AFC timing signal indicating the arrival of a word is output. This A
The AND operates so that the latch 33 latches the carrier frequency error signal 41 at the time when the FC timing signal coincides with the detection presence / absence signal. In addition,
The AFC timing signal input from the outside is always 1 in the initial state before synchronization establishment pull-in. If the frequency error 41 for each input of the AFC timing signal becomes large, the increase is accumulated by the adder 32 by adding the error 41 to the output of the latch 33. The output of the latch 33 is output from the complex multiplier 30 to the carrier phase detector 24, the loop filter 25, the adder 26,
NCO 27, cosine value generation ROM 28, sine value generation ROM
The signal is input to an adder 26 of a phase-locked loop (PLL) consisting of 29, and synchronization is established by pull-in by a correction operation of the phase-locked loop. That is adder 32, latch 33,
This is the function of AND34. Therefore, even when the synchronous demodulation operation of the complex multiplier 30 is not determined, the unique word detection circuit 31 of the present invention can accurately detect the presence / absence of a unique word and also obtain the frequency error information. Can be quickly established.

Once synchronization is established, the output of the complex multiplier 30 correctly demodulates the modulated signal. Next, when a unique word arrives, the frequency error 41 becomes 0, so that the output of the latch 33 is held at the previous value and does not change.

As described above, according to the present invention, even when the demodulation circuit is not operating, the carrier frequency error is detected simultaneously with the unique word detection, and the initial frequency control of the demodulation circuit can be performed more quickly.

[0035]

As described above, according to the present invention, the unique word is detected first from the demodulated signal after the synchronization is established in the demodulator and frame synchronization is established. At the same time, the frequency error of the reproduced carrier is also detected, thereby correcting the phase error of the reproduced carrier. Thus, unique word detection can be stably achieved even under a low C / N ratio condition, and a faster signal can be obtained. Reception synchronization can be established. That is, unique word detection can be performed stably even for a received signal having a frequency error. Further, since the unique word detection circuit of the present invention can detect not only the presence or absence of a unique word but also the frequency error of the received signal,
The initial frequency control of the demodulation circuit can be executed, which is effective in further speeding up the synchronization of the demodulation circuit.

[Brief description of the drawings]

FIG. 1 relates to one embodiment of the present invention, and is a circuit diagram showing a configuration thereof.

FIG. 2 is a diagram showing a frequency characteristic of a filter group used in the present invention and an output spectrum when a unique word arrives.

FIG. 3 is a diagram showing a configuration of a conventional unique word detection circuit.

FIG. 4 is a diagram showing an application of the unique word detection circuit of the present invention to a cycle detection demodulation circuit.

[Explanation of symbols]

Reference Signs List 1 local oscillator 2 π / 2 phase shifter 3, 4 mixer 5 sampling pulse generator 6, 7 A / D converter 8, 9 shift register 10 ₁ to 10 _n complex multiplier 11 complex unique word pattern generator 12 filter Group 14 Demodulation circuit 15, 16 Shift register 17 _{1 to} 17 _2n Exclusive OR 19 Adder 20 Threshold detector 21 _{1 to} 21 _n Absolute value detector 22 Comparison circuit 23 Selection circuit 24 Phase detector 25 Loop filter 26, 32 Adder 27 numerically controlled oscillator 28 cosine value generation ROM 29 sine value generation ROM 30 complex multiplier 31 unique word detection circuit 40 unique word presence / absence detection signal 41 carrier frequency error signal

Claims (2)

(57) [Claims] 1. A π approximating a carrier frequency of a received IF signal.
A real part for performing complex baseband modulation of the IF signal using a real part and an imaginary part using two reference carriers having different phases from each other, sampling the complex baseband signal with a sample pulse and converting it to a digital value; A / D for imaginary part
A unique word detection circuit comprising a converter, first and second shift registers for holding the outputs of the real part and imaginary part A / D converters in N samples and in a pipeline format, respectively, and a unique word in a complex signal format. And a n-th (n = 0, 1, 2,...) Of the unique word generator.
N-1) N complex multipliers each performing a complex multiplication of an output of the first and second shift registers and n-th outputs of the first and second shift registers; A filter bank for performing separation for each frequency band, and an absolute value is calculated by receiving N outputs of the filter bank, and a unique word is obtained when a specific element filter output of the filter bank has a value exceeding a specified value. A unique word detection circuit comprising: a comparison circuit that determines detection, outputs a unique word presence / absence detection signal, and outputs a carrier frequency error signal based on the frequency position of the element filter. 2. A π approximating a carrier frequency of a received IF signal.
A real part for performing complex baseband modulation of the IF signal using a real part and an imaginary part using two reference carriers having different phases from each other, sampling the complex baseband signal with a sample pulse and converting it to a digital value; A / D for imaginary part
A phase-locked loop comprising a complex multiplier, a carrier phase detector, a loop filter, a first adder, a numerically controlled oscillator, a cosine value generation ROM, and a sine value generation ROM. 2. A demodulation circuit for inputting a / D converter output and demodulating the received IF signal, wherein a two-series output of the complex multiplier is input to the first and second shift registers according to claim 1, and the presence or absence of the unique word is provided. A unique word generator for obtaining a detection signal and a carrier frequency error signal, a unique word detector including N complex multipliers, a filter bank, and a comparison circuit; and the carrier frequency error signal as the unique word presence / absence detection signal. A latch circuit that holds the signal in synchronization with a logical product signal of the AFC timing signal and a sum of an output of the latch circuit and the carrier frequency error signal Obtains a second adder for outputting said latch circuit, a demodulation circuit, characterized in that to help pull-in of the latch circuit and the phase synchronization circuit inputs an output to the first adder.