JPH07143197A - Receiver for digital signal - Google Patents

Abstract

PURPOSE:To receive a digital signal correctly even when frame synchronization is not correctly taken by obtaining digital information being received information based on an instantaneous phase or the relation of instantaneous phases of preceding and succeeding frames at a discrimination circuit. CONSTITUTION:The receiver is provided with a receiver 40 demodulating a reception signal to obtain a base band signal, a reception filter 41 forming a matched filter corresponding to a sender filter, a phase detection circuit 42 connecting to an output of the reception filter 41 and a discrimination circuit (DECODER) 43 providing an output of digital information based on the phase detected by the phase detection circuit 42. Then the phase detection circuit 42 uses an instantaneous spectrum analysis means to detect the instantaneous phase of a demodulated base band signal, and the discrimination circuit 43 obtains digital information being received information based on the detected instantaneous phase or the relation of instantaneous phases of preceding and succeeding frames. That is, the phase detection circuit (PHASE DETECTOR) 42 is formed by using an instantaneous spectrum analysis means such as an ST-DFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal receiving apparatus, and more particularly to a receiving apparatus which can normally receive a digital signal even when transmission characteristics such as mobile communication change with time.

With the diversification of communication, in addition to the function of "anytime, anywhere, with anyone", a function of accurately transmitting digital information has been required in order to support any medium.

Therefore, various digital transmission techniques and techniques for automatically equalizing transmission line characteristics have been provided, and digital information can be transmitted in the same manner as analog information. However, there remains a problem that, when the transmission path characteristics drastically fluctuate with time as in mobile communication, it is not possible to sufficiently cope with it, or even if it is possible, it is not economically advantageous.

Therefore, it is desired to provide a system capable of economical and effective digital communication.

[0005]

2. Description of the Related Art FIG. 5 is a block diagram of the configuration of a general digital communication receiver. For such a receiving device,
From the transmission side, a baseband signal obtained by phase-modulating a baseband carrier signal with digital information is passed through an appropriate transmission filter, then modulated to the frequency of light or electromagnetic waves, and transmitted through an arbitrary transmission path.

The transmitted signal is received by the receiving device as shown in FIG. 5 and demodulated by an appropriate receiver (RX) 40. The demodulated and obtained baseband signal is input to a reception filter (REC FIL) 41 which constitutes a matched filter system corresponding to the transmission filter.

The reception filter (REC FIL) 41 suppresses the baseband signal from noise and distortion mixed in on the transmission path, and then the phase detection circuit (PHASE DETECTOR) 42.
Entered in. This phase detection circuit (PHASE DETECTOR) 4
In 2, the phase of each frame of the received baseband signal is obtained.

Then, the subsequent decision circuit (DECODER) 43 decides the transmission digital information assigned to the frame period from the phase value of each frame or the value determined by a predetermined calculation or functional relationship with the phase values of the preceding and following frames. Then, the received digital signal is obtained from the determined digital information.

Further, detailed configuration examples of the phase detection circuit (PHASE DETECTOR) 42 and the determination circuit (DECODER) 43 in the conventional receiver will be described with reference to FIGS. 6 and 7, respectively.
A π / 4-Shifted DQPSK (hereinafter simply referred to as DQPSK) is used as a digital transmission system to simplify the following description.
Will be described as an example, but other systems are the same and can be easily inferred, so the description is omitted.

FIG. 6 shows a phase detection circuit (PHASE DETECTOR).
42 is a block diagram of a configuration corresponding to No. 42 as a basic configuration for detecting the phase for each frame.
Fourier Transform) is used.

The output of the reception filter (REC FIL) 41, which is the baseband signal In input to the phase detection circuit (PHASE DETECTOR) 42, and the signal cos (ωt of the frequency ω from the PLL circuit 431, which includes the phase difference φ. + φ) and π /
Signal sin (ωt + φ) whose phase is shifted by 90 degrees in the 2-phase shifter 423
The products of and are performed in multipliers 420 and 421, respectively. Further, these outputs are accumulated in accumulators 424 and 425 for the frame period, respectively.

By executing the sum of products, the I component (0 degree component) and the Q component (90 degree component) of the baseband signal are obtained. Next, from the I component and the Q component, tan ^{-1 is} calculated by the arithmetic circuit 426.
(I / Q) is calculated and the frame phase is calculated. The obtained frame phase is guided to the decision circuit (DECODER) 43 and returned to digital information.

Further, in FIG. 6, 427 is an I component and Q.
A power ratio detection circuit that detects the power ratio of the components, and controls the PLL circuit 431 based on the detected power ratio.

Reference numeral 430 is a frame extraction circuit,
The frame signal from the judgment circuit (JUDGE) 435 which constitutes the judgment circuit (DECODER) 43 described later is detected, and thereby the accumulators 424 and 425 are reset for each frame.

FIG. 7 shows a configuration example of the decision circuit (DECODER) 43. The delay circuit (DELAY) 432 is a phase detection circuit (PH
The delay amount for one frame period is given to the output from the ASE DETECTOR) 42.

The arithmetic circuit (Σ) 433 receives two frames from the difference between the input phase signal from the phase detection circuit (PHASE DETECTOR) 42 and the phase signal delayed by one frame period by the delay circuit (DELAY) 432. Calculate the phase difference between the periods.

A 2π correction circuit (CORRECTOR) 434 corrects the phase difference based on the value of the phase difference and the sign so that the phase difference is correctly -360 to 360 degrees. Judgment circuit (JUDGE) 435
Determines from the output of the 2π correction circuit (CORRECTOR) 434 the received digital information to any one of the dibits of 00, 01, 10 and 11 in accordance with the determination standard determined in advance on the transmission side, and associates it.

Further, the bit conversion circuit 436 converts the dibit judged by the judgment circuit (JUDGE) 435 into each bit and outputs it as a serial digital signal.

[0019]

Here, in the above-mentioned conventional receiving apparatus, in particular, a phase detection circuit (PHASE DETECT) is used.
OR) 42, the sum of products period has a very important meaning in the process of obtaining the frame phase by obtaining tan ^-1 (I / Q) from the I component and the Q component or by determining the sign. , If a slight deviation from the correct time causes a big error. Therefore, it is necessary to extract an appropriate frame period.

However, in practice, the transmission path becomes a multipath transmission path in a free space in an urban area, for example, and it is practically impossible to extract the frame period, and the phase equalization is not directly necessary for the information transmission. Alternatively, an equalization operation such as channel estimation is required. Moreover, the propagation path itself changes in mobile communication, making it almost impossible to estimate the frame period.

The phase error φ generated when a baseband carrier is assumed is controlled to maximize the power ratio between the I and Q signals when the frame period is correctly extracted (that is, frame synchronization). By doing so, it is possible to keep the value as small as possible.

However, even in this case, when the transmission characteristic is quasi-static, it is possible, but when the transmission characteristic changes at a relatively high speed, the estimation error is unavoidable and causes the transmission error. There is a problem that becomes.

Further, the judgment circuit of the decoder circuit 43 (JUDG
E) In 435, the received digital information is 00, 01,
When determining either 10 or 11, the case where the phase difference takes a value near the center of the judgment reference value is the most correct case where the frame synchronization and the baseband carrier signal are reproduced, and based on the value of the phase difference. The frame phase is controlled.

Actually, when the phase difference changes so as to approach the judgment reference value, the frame synchronization is corrected by slightly advancing or delaying the frame synchronization. There is a problem that it is almost impossible to correctly take the above, and the transmission error rate cannot be kept low.

From the above facts, in the conventional method in which digital reception is performed by subjecting the intra-frame baseband signal to DFT processing, it is premised that the frame is reproduced extremely correctly, which causes a problem of transmission error. Existed. In addition, there is a problem in that it is impossible to correctly extract a frame because the transmission path has frequency characteristics and various delay paths.

Therefore, according to the present invention, a receiver which can correctly receive a digital signal even when the transmission path has a frequency characteristic and is a multipath transmission path and the frame synchronization cannot be taken correctly. The purpose is to provide.

[0027]

A baseband obtained by fixing the phase of a baseband carrier signal for each fixed period (frame) and associating the fixed phase or the relationship with the phase of another frame with digital information. In a communication system that modulates and communicates signals, a digital signal receiving apparatus according to the present invention includes a receiver that demodulates a received signal to obtain a baseband signal, and a receiving filter that forms a matched filter corresponding to a transmitting filter. It has a phase detection circuit connected to the output of the reception filter and a judgment circuit (DECODER) for outputting the digital information from the detected phase of the phase detection circuit.

Then, the phase detection circuit detects the instantaneous phase of the demodulated baseband signal using the instantaneous spectrum analysis means, and the decision circuit (DECODER) detects the instantaneous phase of the detected or the instantaneous value of the preceding and succeeding frames. It is configured to obtain digital information which is received information from the relationship with the phase.

Also, in one aspect of the present invention, the instantaneous spectrum analysis means is a short time DFT (ST-
DFT) or the generalized ST-DFT instantaneous spectrum is analyzed.

Furthermore, in another aspect, the phase detection circuit comprises:
The instantaneous spectrum analysis means is used to detect the instantaneous phase of the demodulated baseband signal at about the center of the received baseband signal.

[0031]

[Operation] Short time DFT (S
It is configured to detect the instantaneous phase of the demodulated baseband signal using an instantaneous spectrum analysis means such as T-DFT).

When such an instantaneous spectrum analyzing means is used, since the phase at an arbitrary time (n) can be obtained, it is not necessary to extract a frame unlike the conventional DFT format. Therefore, the need for strict frame synchronization is eliminated.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention employs a phase detection circuit (PHASEDETECTOR) 42 in the ST configuration in the conventional receiver configuration described above.
-It is characterized in that it is configured by using an instantaneous spectrum analysis means such as DFT.

Before explaining the construction of the embodiment of the phase detection circuit (PHASE DETECTOR) 42 according to the present invention using such ST-DFT, the principle thereof will be explained in comparison with the conventional construction.

Now, the signal x of π / 4-shifted DQPSK x
(t) is expressed as follows. x (t) = I _k cos 2πf _m t / T + Q _k sin 2πf _m t / T

Here, (k-1) T≤t≤kT, T = N
τ and τ is the number of repetitions of the sampling frequency.

If there is a phase difference of θ in the carrier frequency extracted by the demodulator of the receiving apparatus, the received vector value I _k is given by the equation (1).

[0038]

[Equation 1] Here, T = τN is the frame length, and N per frame
There are sample times. Also, the vector value Q _k is
Similarly, it is given as in Equation 2.

[0039]

[Equation 2] As shown in Expressions 1 and 2, when θ is 0, the maximum power ratio of the vector values I _k and Q _k is given. At this time, the phase of the extracted carrier is the signal x (t) included in the IF band.
Synchronize with your carrier. Therefore, the relationship of Equation 3 is established.

[0040]

[Equation 3] The demodulation performed by the equations 1 and 2 for the continuous signal x (t) is equivalently performed by the DFT on the sample data x (n). Here, n is a sampling clock. FIG. 3 is an explanatory diagram of a unit sample response of a window function, and a dotted line in the figure means an operand for a data stream showing a frame of DFT.

The first one-sided band of the DFT is used to implement equations (1) and (2), and the arrangement of the first one-sided bands is shown in the phase plane by the dotted lines in FIG.
The center frequency of the first side band frequency range (f _m / 2,
It is set to 3f _m / 2) on the f _m. This is because the bandwidth of each one side band is f _{m in} the meaning of frequency analysis.
Because it is chosen by.

[0042] When the sampling frequency f _S is at Nf _m, vector values I _k, Q _k, the first side band, f _S
Centering on / N, it is given by the literal numbers 1 and 2.

However, it is well known that the DFT analysis error due to one sample shift is almost equal to that of the maximum N / 2 sampling shift. This requires a strict synchronization state in the communication system, which is practically unfeasible.

Even if the frames are exactly synchronized,
With respect to frequency components, frames disappear during transmission on a non-linear wireless communication channel, and frame synchronization becomes a serious problem.

On the other hand, the new concept of the instantaneous spectrum according to the present invention reduces the need for frame synchronization, and is important in solving such a big problem.

That is, the frequency component of the instantaneous spectrum corresponding to the first one side band of the DFT is the short time DF.
In the case of k = 1 in T (hereinafter ST-DFT), it is expressed as in Equation 4.

[0047]

[Equation 4] Here, the vector value h (p) is a frequency analysis window function that is f _S / N in ST-DFT,
For example, it is represented by the following Expression 5.

[0048]

[Equation 5] The length of the vector value h (p) window is −1 ≦ p / mN
≤1, ie given by 2 mN. The vector value h (p) defined by Equation 5 is shown by a solid curve (i) starting from p = 0 in FIG.

The code period shown above the (-N / 2, N / 2) period in the figure is equal to that of the DFT, and the main frame of the ST-DFT corresponding to the k-th code period is adjacent to the k-th frame.
They are located in the (-N, N) period with 50% overlap during the -1 and k + 1th code periods.

When the main frame of the ST-DFT is made to coincide only with the k-th code period, the window vector h (*) is changed as shown by the chain line (ii) in FIG.

This modification doubles the one-sided band in the frequency domain, as shown by the shaded area in FIG.
It can be easily understood that the expansion of this one-sided band does not cause any problem. Because the noise in the expanded region is the modified window function h
This is because (*) has been removed by the reception filter 41 (see FIG. 5) that includes the regions of (0, f _m / 2) and 3f _m / 2 or more.

That is, the instantaneous spectrum given by the window function h (*) shown by the chain line curve (ii) in FIG. 3 and the one-sided band shown by the shaded area in FIG.
The paper “Application of the G” published by the inventors
eneralized Short Time DFTto the Hilbert Transforme
r and Its Characteristics "(M. Kishi, T. Ishigur
o, and Y. Kozaki, IEEE VTC'93), as described on page 665, right column, STgDFT and STgIFT are given by
This is because it is recognized that it is given by the 0th frequency component (k = 0) when ξ = 1/2 when defined as

[0053]

[Equation 6] Here, ξ is a positive real number, and 0 ≦ ξ <1.
x (r) is the input data at the sampling time r. h
(N−r) is the same window function as the definition of ST-DFT, and when h (p) = 1, p = 0 and h (p) =
When 0 and p = Nu, u is a non-zero integer.

Then, it is expressed as the following Expression 7.

[Equation 7]

Further, h (p) is expressed by the following equation 8.

[Equation 8] STgDFT provides a strong solution for obtaining I _k and Q _k without intersymbol distortion. This is because the window function h (*) given in Equation 7 crosses zero at every N sample clocks.

ST-DFT or ST described above
A configuration example of the receiving device based on the principle of the present invention using gDFT will be described below.

In the embodiment of the present invention, the phase detecting circuit 42 is characterized in the configuration of the receiving apparatus shown in FIG.
Other receiver 40, reception filter 41 and decoder 4
The configuration of No. 3 is the same as that described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of a phase detection circuit as an embodiment of the present invention. That is, the circuit of FIG. 1 is used in place of the phase detection circuit 42 of FIG. Further, according to the present invention, strict frame synchronization is not required, so that the determination circuit (JU) of the determination circuit (DECODER) 43 (JU
The frame detection signal from the DGE) 435 becomes unnecessary in the phase detection circuit shown in FIG.

The phase detection circuit according to the embodiment of the present invention shown in FIG. 1 includes shift registers 10 and 1 for buffer systems.
1 and a shift register 12 for window function h (*). The shift registers 10 and 11 have mN shift stages (that is, for mN frames), and the shift register 12
Has (mN + 1) shift stages (ie, mN + 1 frames).

To the input terminal 1, x (r) which is the output from the reception filter 41 is input. Note that r is the sampling time.

To the multipliers 2 and 3, -sin πr / N given from the signal source 6 through the cos πr / N and π / 2 phase shift circuit 5, and the baseband signal which is an input signal at each sampling time. x (r) is input.

Then, these multiplication results are sequentially input to the shift registers 10 and 11 and shifted. That is, x (r) cos πr / N is shifted in the shift register 10, and −x (r) sin πr / N is shifted in the shift register 11.

On the other hand, in the ROM 12, the window function h
(*) Is configured to be stored as a constant such as a ROM.

Further, between the shift register 10 and the ROM 12, mN multipliers 101, 102, ...
N) are provided. Similarly, the shift register 1
1 and the ROM 12 include mN multipliers 111, 1
12 ... 11 (mN) is provided.

The multipliers 101, 102 ... 10 (mN) provided between the shift register 10 and the ROM 12 are:
It is configured to multiply the signal of each stage of the shift register 10 by the window function h (*) of the ROM 12. Similarly, the multipliers 111, 112, ... 11 (mN) provided between the shift register 11 and the ROM 12 are provided with the signals of the respective stages of the shift register 11 and the window function h of the ROM 12.
It is configured to multiply (*).

The multiplication result of each of the multipliers 101, 102, ..., 10 (mN) is accumulated by the accumulation circuit 7, and the multiplier 11
When the multiplication results of 1, 112 ... 11 (mN) are accumulated by the accumulator circuit 8, the I component and the Q component of the baseband signal are the same as the outputs of the accumulators 424 and 425 in FIG.
The ingredients are obtained.

The operation circuit 9 calculates the I and Q components
^The frame phase φ _h (r) is output by obtaining ^-1 (I / Q) or by determining only the sign of the sign.

As described above, according to the present invention, since the phase at an arbitrary time (r) can be obtained, unlike the conventional DFT format, it is not necessary to extract a frame, and as shown in FIG. There is no need to adjust the phase.

However, the phase of ST-DFT shows a substantially constant value within the frame, and the phase at any time within the frame may be used. However, in the vicinity of the frame edge, the value is slightly deviated from the correct value due to the influence of the matched filter (reception filter) and the transmission band limitation. Therefore, it is preferable to select as close to the center of the frame as possible.

For this reason, it is not necessary to provide the conventional frame extracting circuit 430 and the judging circuit 435 shown in FIGS. 6 and 7 as accurate as possible, but a simple frame synchronization mechanism is provided.
It is desirable to keep the observation point away from the end points of the frame.

In the description of the embodiment shown in FIG. 1, the shift registers 10 and 11 are used. However, the present invention is not limited to such an embodiment, and instead of these registers, for example, RAM and a pointer are used to sequentially change the pointer position, thereby sequentially shifting the data in the shift register in FIG. It is possible to have the function of.

The use of the RAM and the pointer is more advantageous than the use of the shift register in that the speed can be increased.

[0073]

The simulation result is quantitatively obtained based on the configuration of the present invention described above, and the result is examined in comparison with the conventional example, as shown in FIG.

As can be seen from this figure, in the conventional system, the phase detection circuit 42 of FIG. 6 is used in the ST- of the configuration of FIG. 1 using a fading transmission line showing a bit error of about 3 × 10 ^-2 . When it is replaced with the DFT type, it becomes 1 × 10 ^-2 , which is an improvement of about 3 times. This corresponds to the case where the transmission power is increased by 6 dB with the conventional method. Furthermore, it greatly exceeds the improvement of 3 dB obtained by the diversity reception method, and the magnitude of the effect can be easily understood.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a phase detection circuit of the present invention.

FIG. 2 is a diagram showing an effect of the present invention.

FIG. 3 is a diagram illustrating a unit sample response of a window function.

FIG. 4 is an explanatory diagram of one side band arrangement.

FIG. 5 is a block diagram of a configuration of a receiver for general digital communication.

FIG. 6 is a configuration example of a conventional phase detection circuit.

FIG. 7 is a configuration example of a determination circuit.

[Explanation of symbols]

1 Baseband signal input 2, 3 Multiplier 5 π / 2 Phase shifter 6 cos πr / N Oscillator 10, 11 Buffer system shift register 12 Window function ROM 7, 8 Adder circuit 9 tan ^-1 Q / I arithmetic circuit 40 receiver 41 reception filter 42 phase detection circuit (PHASE DETECTOR) 43 judgment circuit (DECODER)

Claims (3)

[Claims] 1. A baseband signal obtained by fixing the phase of a baseband carrier signal every fixed period (frame), and correlating the fixed phase or the relationship with the phase of another frame with digital information. In a receiver of a communication system for performing communication, a receiver (4 that demodulates a received signal to obtain a baseband signal
0), a reception filter (41) forming a matched filter corresponding to the transmission side filter, a phase detection circuit (42) connected to the output of the reception filter (41), and detection of the phase detection circuit (42) A decision circuit (DECODER) (4) that outputs the digital information from the phase
3), the phase detection circuit (42) detects the instantaneous phase of the demodulated baseband signal using the instantaneous spectrum analysis means, and the judgment circuit (DECODER) (43) detects the instantaneous phase. An apparatus for receiving a digital signal, characterized in that it is configured to obtain digital information, which is received information, from the relationship between the instantaneous phase or the instantaneous phases of preceding and following frames. 2. The short-time DF according to claim 1, wherein the instantaneous spectrum analysis means is
T (ST-DFT) or generalized ST
-A digital signal receiving apparatus characterized by analyzing an instantaneous spectrum of a DFT. 3. The phase detection circuit (42) according to claim 1 or 2, wherein the instantaneous spectrum analyzing means detects the instantaneous phase of the demodulated baseband signal at a substantially central point of time of the received baseband signal. A digital signal receiving apparatus having the above-mentioned configuration.