JPH0993163A - Spread spectrum reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the entire circuit configuration by providing a means demodulating data with a product between an output of sum of outputs of spread spectrum signals and a delayed sum output by one bit rate. SOLUTION: The carrier frequency of an SS signal input is frequency- converted by a mixer 1 and a local oscillator 2 up to an integer multiple of a chip rate and sampled by a clock generator 4 and an A/D converter 5 via an amplitude limit amplifier 3. Furthermore, the sampled SS signal is given to a shift register 6 delaying the signal by one chip rate while arranged by a length of a PN code and a multiplier 7 is used for multiplying the output signal by each of values from the MSB to the LSB of the PN code. Data are outputted from a differential delay detector 10 demodulating data by a product between a sum of all output signals by an adder 8 and a sum output delayed by one bit rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving system in spread spectrum (hereinafter referred to as SS) communication.

[0002]

2. Description of the Related Art In a conventional SS receiving system of this type, as a demodulation circuit using a digital matched filter as disclosed in Japanese Patent Laid-Open No. 5-252142,
For example, as shown in FIG. 11, a carrier reproduced by a VCO is multiplied by an SS signal to form data including a spreading code, and then despread through the digital matched filter,
Furthermore, a frequency error is detected by this output and negative feedback is applied to the VCO.

[0003]

In the SS receiving method of the prior art as described above, a circuit for reproducing the carrier is additionally required, and the input SS signal has an AGC with a wide dynamic range. Therefore, it has a drawback that the circuit configuration becomes complicated.

Further, when the above defect example is prolonged and described, since the carrier reproducing circuit is a DC loop, temperature compensation is difficult, and a 90 ° phase shifter for detecting a frequency error is required, and Two circuits related to the 90 ° phase shifter and thereafter are required.

Therefore, the present invention eliminates the need for an AGC circuit for applying the above-mentioned AGC, a carrier reproducing circuit, and a 90 ° phase shifter, and at the same time reduces the number of gates in each circuit, thereby simplifying the overall circuit configuration. The purpose is to obtain an improved SS reception system.

[0006]

The structure of the present invention will be described with reference to FIG. 1. The carrier frequency of the SS signal input is frequency-converted by the mixer 1 and the local oscillator 2 up to an integral multiple of the chip rate, and the amplitude is further changed. The sampling is performed by the clock generator 4 and the A / D converter 5 via the limiting amplifier 3.

Next, the sampled SS signal is passed through a shift register 6 which delays by one chip rate by PN lengths, and the output signals are M of PN code.
A differential delay detector for multiplying from SB to LSB to a multiplier 7 and further demodulating by a product of an output obtained by adding all of the output signals to an adder 8 and a product obtained by delaying the added output by one bit rate. Data is output from 10.

The digital matched filter 9 is composed of the shift register 6, the multiplier 7 and the adder 8.

[0009]

In the SS receiving system configured as described above, the A / D converter 5 and the digital matched filter for amplifying the input SS signal to the limiting level by the action of the amplitude limiting amplifier 3 and performing despreading. 9 works so as to operate effectively and stably.

Then, the above despread SS signal is
Next, the differential delay detector 10 operates so as to obtain a normal data output.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described in detail with reference to the drawings. Before that, in order to facilitate the description, the IF frequency of the SS signal is made equal to the chip rate, and the sampling frequency is set. The clock is 4 times the chip rate.

The PN code is 7 bits "000101".
1 "is used and the carrier frequency of the SS signal is made equal to the chip rate, and the operation will be described as a differentially binary PSK (hereinafter, referred to as DBPSK). Further, FIGS. , And also
Each clock (CLK) input is provided by the clock generator 4 at the same time.

In FIG. 11, the conventional SS reception system using a digital matched filter delays the reproduced data and further applies a PN code to perform despreading. In the present invention, as shown in FIG. After delaying the waveform of PSK, a PN code is further applied to perform despreading, and its configuration is shown in FIG.

Note that the SS signal to be transmitted is of the direct spreading system, the spreading is performed by BPSK, and the data is synchronized with one cycle of the PN code, but the carrier of the SS signal is not necessarily synchronized. There is no.

In FIG. 1, the input SS signal is frequency-converted by the mixer 1 and the local oscillator 2 to an integral multiple of the chip rate, and this output signal is further subjected to the amplitude limiting amplifier 3.
After being amplified to the limiting level (see FIG. 8) by the clock generator, sampling is performed by the clock generator 4 and the A / D converter 5 (a sampling data example of data 0 is shown in FIG. (B) shows an example of sampling data of data 1).

Although the sampling clock is asynchronous with the SS signal, the carrier frequency is equal to the chip rate, so that sampling at a certain time point and sampling four clocks after that are shown in FIG. 3, respectively. As described above, the PN code is shifted by 1 bit, and the phase difference is 0 ° or 180 °.

As described above, according to the SS receiving method of the present invention, since the frequency difference is used, it may be asynchronous and the waveform may be saturated. Regarding the frequency shift, for example, even if the PN length is 63 bits and the shift is 10 PPM,
The deviation is about 63 × 4 × 10 ⁻⁶ × 360 ° = 0.9 °, which is not a problem.

Next, the sampling data ((1)
~ (32)) are stored in the shift register as shown in Fig. 4 (a), (1) for (A), (5) for (B), (9) for (C),
(D) is-(13), (E) is (17), (F) is-(21), and (G) is-(2
The data of (5) is output respectively, and further (H) which added all this data is (1) + (5) + (9)-(13) + (17)-(21)-(25)
Becomes

If one shift is made from this state, FIG.
It becomes like (b), and (H) is (2) + (6) + (9) + (10)-(14) + (1
It becomes 8)-(22)-(26).

Next, FIG. 5 shows waveforms representing the above (A) to (G) and (H) on the time axis.

Then, all of (A) to (G) are added (H)
Is the PN code given to the shift register and the PN of the SS signal
It becomes 7 times (PN length times) between 4 clocks where the signs match,
Further, delay (H) by one cycle of the PN code ((I)),
Data can be demodulated by each ((J)) taking the product of (H) and (I), and the differential detection output for explaining these operations is shown in FIG.

FIG. 7 shows a waveform simulated by DBPSK by an AGC amplifier (configuration is not shown), and FIG. 8 shows a waveform simulated by DBPSK by an amplitude limiting (limiter) amplifier (see FIG. 1).

Further, FIG. 9 shows the Differentially Quadrature
An SS reception system configured by PSK (DQPSK) is shown, and its waveform is shown in FIG. 10, which is simulated by an amplitude limiting (limiter) amplifier.

[0024]

Since the present invention is constructed as described above, it has the following effects.

Since the AGC is not required in the input amplifying section, the conventional FM limiter amplifier can be used as it is, so that the size and cost of the device can be reduced.

Further, since it can be constructed by all digital circuits, it is possible to form a gate array.

Furthermore, since only one system requires two digital matched filters, the number of gates in the gate array can be reduced to about 1/2.

Therefore, since the carrier regeneration loop is eliminated, the operation is stable against temperature changes.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining the present invention.

FIG. 2 is an explanatory diagram of SS-DBPSK according to the present invention.

FIG. 3 is a diagram showing an example of sampling data.

FIG. 4 is a diagram showing a shift state of sampling data.

FIG. 5 is a waveform diagram showing sampling data on a time axis.

FIG. 6 is a waveform diagram showing a differential differential detection output in a PN code.

FIG. 7 is a waveform diagram of DBPSK (AGC amplifier).

FIG. 8 is a waveform diagram of DBPSK (limiter amplifier) of the present invention.

FIG. 9 is an explanatory diagram by SS-DQPSK showing another embodiment of the present invention.

FIG. 10 is a waveform diagram of a DQPSK (limiter amplifier) according to another embodiment of the present invention.

FIG. 11 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1 Mixer (MIX) 2 Local Oscillator (OSC) 3 Amplitude Limiting Amplifier (Limiter) 4 Clock Generator (CLK) 5 A / D Converter 6 Shift Register (D: Delay) 7 Multiplier 8 Adder (Σ) 9 Digital matched filter 10 Differential delay detector

[Procedure amendment]

[Submission date] January 17, 1996

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[Figure 3]

FIG.

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FIG. 4

FIG. 6

[Figure 5]

FIG. 7

[Figure 8]

[Figure 9]

[Figure 10]

FIG. 11 ─────────────────────────────────────────────────── ───

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[Submission date] June 3, 1996

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Title of the invention Spread spectrum reception system

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving system in spread spectrum (hereinafter referred to as SS) communication.

[0002]

2. Description of the Related Art In a conventional SS receiving system of this type, as a demodulation circuit using a digital matched filter as disclosed in Japanese Patent Laid-Open No. 5-252142,
For example, as shown in FIG. 9, after the carrier reproduced by the VCO is multiplied by the SS signal to form the data including the spread code,
Despreading is performed through the digital matched filter, a frequency error is detected by this output, and negative feedback is applied to the VCO.

[0003]

In the SS receiving method of the prior art as described above, a circuit for reproducing the carrier is additionally required, and the input SS signal has an AGC with a wide dynamic range. Therefore, it has a drawback that the circuit configuration becomes complicated.

Further, to describe the above-mentioned defect examples, the carrier regenerating circuit is a DC loop, so temperature compensation is difficult, and a 90 ° phase shifter for detecting a frequency error is required. Two circuits related to the 90 ° phase shifter are required.

Therefore, the present invention eliminates the need for an AGC circuit for applying the above-mentioned AGC, a carrier reproducing circuit, and a 90 ° phase shifter, and at the same time reduces the number of gates in each circuit, thereby simplifying the overall circuit configuration. The purpose is to obtain an improved SS reception system.

[0006]

The structure of the present invention will be described with reference to FIG. 1. The carrier frequency of the SS signal input is frequency-converted by the mixer 1 and the local oscillator 2 up to an integral multiple of the chip rate, and the amplitude is further limited. The sampling is performed by the clock generator 4 and the A / D converter 5 via the amplifier 3.

Next, the sampled SS signal is passed through a shift register 6 which delays by one chip rate by PN lengths, and the output signals are M of PN code.
A differential delay detector for multiplying from SB to LSB to a multiplier 7 and further demodulating by a product of an output obtained by adding all of the output signals to an adder 8 and a product obtained by delaying the added output by one bit rate. Data is output from 10.

The digital matched filter 9 is composed of the shift register 6, the multiplier 7 and the adder 8.

[0009]

In the SS receiving system configured as described above, the A / D converter 5 and the digital matched filter for amplifying the input SS signal to the limiting level by the action of the amplitude limiting amplifier 3 and performing despreading. 9 works for effective and stable operation.

Then, the above despread SS signal is
Next, the differential delay detector 10 operates so as to obtain a normal data output.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described in detail with reference to the drawings. However, for ease of explanation, the IF frequency of the SS signal is equal to the chip rate and the sampling clock Is 4 times the chip rate.

The PN code is 7 bits "000101".
1 "is used, and the carrier frequency of the SS signal and the chip rate are made equal to each other.
Binary PSK (hereinafter referred to as DBPSK) will be described, and FIG. 2 will be used to further explain this operation.
8 through 8 and each clock (CLK) input is provided by the clock generator 4 at the same time.

In FIG. 9, the conventional SS reception system using a digital matched filter delays reproduced data and further applies a PN code to perform despreading. In the present invention, as shown in FIG. After delaying the PSK waveform,
Further, a PN code is applied to perform despreading, and its configuration is shown in FIG.

Note that the SS signal to be transmitted is of the direct spreading system, the spreading is performed by BPSK, and the data is synchronized with one cycle of the PN code, but the carrier of the SS signal is not necessarily synchronized. There is no.

In FIG. 1, the input SS signal is frequency-converted by the mixer 1 and the local oscillator 2 to an integral multiple of the chip rate, and this output signal is further subjected to the amplitude limiting amplifier 3.
After being amplified to the limiting level (see FIG. 8) by the clock generator, sampling is performed by the clock generator 4 and the A / D converter 5 (a sampling data example of data 0 is shown in FIG. (B) shows an example of sampling data of data 1).

Although the sampling clock is asynchronous with the SS signal, the carrier frequency is equal to the chip rate. Therefore, sampling at a certain point and sampling four clocks after that are shown in FIG. ，
As shown in (b), the PN code is shifted by 1 bit, and the phase difference is 0 ° or 180 °.

As described above, according to the SS receiving method of the present invention, since the frequency difference is used, it may be asynchronous and the waveform may be saturated. Regarding the frequency shift, for example, even if the PN length is 63 bits and the shift is 10 PPM,
The deviation is about 63 × 4 × 10 ⁻⁶ × 360 ° = 0.9 °, which is not a problem.

Next, in the digital matched filter 9, if the sampling data (1) to (32) of FIG. 3 are stored in the shift register 6 as shown in FIG. (1), (B) is (5), (C) is (9), (D) is-(13), and (E) is (1).
7) and (F),-(21) is output to (G), and-(25) is output to (G), respectively. Further, (H) obtained by adding all the data by the adder 8 is ( 1)
+ (5) + (9)-(13) + (17)-(21)-
(25)

If one shift is made from this state, FIG.
(B), and (H) is (2) + (6) +
(9) + (10)-(14) + (18)-(22)-
(26).

Next, waveforms representing the above (A) to (G) and (H) on the time axis are shown in (a) and (b) of FIG. 5, respectively.

Then, (H) obtained by adding all of (A) to (G) becomes 7 times (PN length times) in 4 clocks when the PN code given to the shift register 6 and the PN code of the SS signal match. Data can be demodulated by further delaying (H) by one period of the PN code ((I)) and taking the product of (H) and (I) ((J)). The output waveform of the differential delay detector 10 for explaining these operations is shown in FIG.

FIG. 7 shows a waveform simulated by DBPSK by an AGC amplifier (configuration is not shown), and FIG. 8 shows a waveform simulated by DBPSK by an amplitude limiting (limiter) amplifier (see FIG. 1).

[0023]

Since the present invention is constructed as described above, it has the following effects.

Since the AGC is not required in the input amplifying section, a conventional FM limiter amplifier or the like can be used as it is, so that the size and cost of the device can be reduced.

Further, since it can be constructed by all digital circuits, it is possible to form a gate array.

Furthermore, the number of gates in the gate array can be reduced to about 1/2 because only one system has been required for two digital matched filters in the past.

Therefore, since the carrier regeneration loop is eliminated, the operation is stable against temperature changes and the like.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining the present invention.

FIG. 2 is an explanatory diagram of SS-DBPSK according to the present invention.

FIG. 3 is a diagram showing an example of sampling data.

FIG. 4 is a diagram showing a shift state of sampling data.

FIG. 5 is a waveform diagram showing sampling data on a time axis.

FIG. 6 is a waveform diagram showing a differential differential detection output in a PN code.

FIG. 7 is a waveform diagram of DBPSK (AGC amplifier).

FIG. 8 is a waveform diagram of DBPSK (limiter amplifier) of the present invention.

FIG. 9 is a configuration diagram showing a conventional embodiment.

[Explanation of Codes] 1 Mixer (MIX) 2 Local Oscillator (OSC) 3 Amplitude Limiting Amplifier (Limiter) 4 Clock Generator (CLK) 5 A / D Converter 6 Shift Register (D: Delay) 7 Multiplier 8 Addition (Σ) 9 Digital matched filter 10 Differential delay detector

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Claims (1)

[Claims] 1. In a wireless communication system for performing direct spread spectrum, spread spectrum signals are converted by frequency conversion means up to an integral multiple of a chip rate, and further sampled by A / D conversion means via amplitude limiting amplification means. After that, the one-chip rate delay means of the spread spectrum signal is arranged in time series of the code generated by the spread code generation means, and the output of the spread spectrum signal is multiplied by the code generated by the spread code generation means. Further, there is provided a spread spectrum receiving system characterized by further comprising means for demodulating by a product of an output obtained by adding all outputs of the spread spectrum signal and a product obtained by delaying the added output by one bit rate.