JP2848724B2 - Synchronization judgment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization judging circuit for detecting an out-of-synchronization of a spreading code used in demodulation in an apparatus for receiving a spread modulation wave transmitted after being subjected to spread spectrum modulation.

[0002]

2. Description of the Related Art In a communication system employing a direct spread system which is a kind of spread spectrum modulation system, transmission information is converted into a primary modulated wave by a predetermined modulation system and then multiplied by a PN code or other spread codes. As a result, the frequency spectrum is transmitted as a spread modulated wave spread over a wide band. At the receiving end, spread demodulation is performed to restore the energy of the primary modulated wave to the original band by correlating the spread modulated wave with the same spread code synchronized with the spread modulated wave. Is performed.

[0003] Such a spread spectrum modulation method is used not only in a communication system but also in, for example, a distance measuring system. In a receiving apparatus of such a system, a spread modulation wave to be received is required for spread demodulation. Since a spread code synchronized with the synchronization code is indispensable, a synchronization determination circuit that constantly monitors the presence / absence of the synchronization loss is mounted in order to promptly resume synchronization when the synchronization is lost.

FIG. 11 is a diagram showing a configuration example of a conventional synchronization determination circuit. In the figure, a synchronization determination circuit includes a PN code generator (P) that generates a PN code synchronized with a spread modulated wave.
N) 111, a mixer 112 for multiplying the PN code by the spread modulation wave to perform spread demodulation, and a mixer 1
A low-pass filter 113 for removing the harmonic components generated in 12, a detector 114 for rectifying the output of the filter and extracting a DC component, and integrating the extracted DC component to obtain a voltage signal corresponding to the power of the demodulated output. And a comparator 116 that obtains a synchronization determination output indicating whether or not the PN code is out of synchronization according to the magnitude relationship between the voltage signal and the threshold voltage _Vth .

[0005]

In such a conventional synchronization determination circuit, since the threshold is fixedly set, when the signal level of the demodulated output is higher than the threshold, the signal included in the demodulated output is set. Since it is determined that the synchronization state is maintained regardless of the components of, for example,
In the state where the S / N ratio of the reception band is deteriorated and the demodulated output contains a large noise power, the loss of synchronization could not be detected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization determination circuit that can reliably detect the out-of-synchronization of a demodulation spread code even when a large noise power is included in a demodulation output.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. The present invention provides a spread spectrum modulation signal in which a spectrum is spread over a wide band by a spread modulation process in which an autocorrelation value is sharply reduced near its maximum value by a spread modulation process for multiplying the modulated wave by a primary modulated wave. A spread demodulation means 11 for performing a spread demodulation process opposite to the spread modulation process based on the same demodulation spread code to obtain the power level of the demodulated output
And a comparison means 13 for comparing the power level with a predetermined threshold value and detecting out-of-synchronization of the demodulation spread code with respect to the spread modulation wave according to the comparison result. Phase intermittent means 15 for intermittently shifting the phase of the spread code to a value at which the cross-correlation value between the spread code and the modulation spread code becomes smaller than the maximum value, and a demodulation output obtained according to the phase-shifted demodulation spread code. And a threshold varying unit 17 for variably setting a threshold according to the power level of the power supply.

[0008]

According to the present invention, the phase varying means intermittently shifts the phase of the demodulation spread code to a value at which the cross-correlation value between the spread code and the modulation spread code becomes smaller than its maximum value. In the state where the phase of the demodulation spread code is shifted, since the spread code and the modulation spread code cannot be correlated,
The spread demodulation means 11 obtains the power level of the noise obtained as the demodulated output, and the threshold variable means 17 variably sets the threshold value of the comparison means 13 according to the power level. Further, since the above-mentioned noise component has no correlation with the demodulation spreading code, the spread demodulation output 11 is output in a state where the phase of the demodulation spreading code is restored.
A noise component of the same level is also superimposed on the primary modulated wave that is obtained by demodulation.

That is, since the threshold value of the comparing means 13 is variably set in accordance with the power level of the noise superimposed on the demodulated output, even when the noise power is large, a certain noise merge is ensured and the synchronization is lost. Detection can be performed.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing a first embodiment of the present invention.

In the figure, components having the same functions and configurations as those shown in FIG. 11 are denoted by the same reference numerals, and description thereof is omitted here. According to the present embodiment, the PN code generator 111
Is connected to a shift register (SR) 21 for shifting the phase of the PN code obtained at its output, and a PN code generator 11 is provided between the PN code generator 111 and the mixer 112.
And a data selector (SEL) 22 for selecting and outputting one of the output of the shift register 21 and the output of the shift register 21.
5 which obtains the threshold voltage from the output of
/ H) 23, and a flip-flop (FF) 24 for latching the synchronization determination output at a predetermined timing is provided at the output of the comparator 116.

As for the correspondence between the present embodiment and the block diagram shown in FIG. 1, the mixer 112, the low-pass filter 113, the detector 114 and the integrator 115 correspond to the spread demodulation means 11, the comparator 116 and the flip-flop. Reference numeral 24 corresponds to the comparing means 13, the shift register 21 and the data selector 22 correspond to the phase varying means 15, and the sample and hold circuit 23 corresponds to the threshold varying means 17.

FIG. 3 is an operation timing chart of the first embodiment. Hereinafter, the operation of this embodiment will be described with reference to FIGS. The shift register 21 delays the PN code output from the PN code generator 111 by one bit (hereinafter, the one-bit delay time is indicated by “T”) and outputs it. The data selector 22 alternately switches the output of the PN code generator 111 and the output of the shift register 21 at a predetermined cycle (= t) and supplies the output to the mixer 112 (FIG. 3).

Generally, the auto-correlation value of the PN code sharply decreases from its maximum correlation point as shown in FIG. 4 and has no correlation at points separated by T or more on the time axis. During the period when the data selector 22 selects the output of the PN code generator 111, the spread modulated wave is demodulated and the primary modulated wave is output (FIG. 3). A noise signal is output in place of the primary modulated wave (FIG. 3). Such a noise signal generally has no correlation with the PN code described above, and therefore has the same power as the noise signal superimposed on the spread demodulated output of the spread modulated wave.

The sample and hold circuit 23 outputs an output from the integrator 115 in response to the above-described noise signal prior to each timing when the data selector 22 selects the output of the PN code generator 111 instead of the output of the shift register 21. The voltage signal is held and given to the comparator 116 as the threshold voltage _Vth (FIG. 3).

The flip-flop 24 latches the synchronization determination output output from the comparator 116 in accordance with the set threshold voltage _Vth prior to the timing at which the data selector 22 selects the output of the shift register 21 again (FIG. 2). 3) Therefore, the synchronization determination output is based on the maximum value of the voltage signal output from the integrator 115.

As described above, according to this embodiment, the threshold voltage V _th of the comparator 116 is periodically set to a value proportional to the power of the noise signal superimposed on the spread demodulated output.
Even in the state where the S / N ratio of the reception band is deteriorated and the spread demodulation output contains large noise power, the threshold voltage is set to a high value, and the out-of-synchronization can be reliably detected.

FIG. 5 is a diagram showing a second embodiment of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted here.

The present embodiment differs from the embodiment shown in FIG. 2 in that an analog delay line (DL) 51 is provided instead of the sample and hold circuit 23. FIG. 6 is an operation timing chart of the second embodiment.

The operation of this embodiment will be described below with reference to FIGS. Since the delay time of the analog delay line 51 is set in advance to t, the output signal of the integrator 115 delayed by t on the time axis is given to the threshold input terminal of the comparator 116 as shown in FIG.

That is, the comparator 116 operates with the integrated value of the noise signal obtained as the spread demodulated output during the period when the data selector 22 selects the output of the shift register 21 as the threshold voltage _Vth . The same synchronization determination output as in the first embodiment is obtained.

In this embodiment, since the operation of each unit is the same as that of the first embodiment except for the above-mentioned points, in FIG. 6, timings and the like corresponding to FIG. Shown, and the description thereof is omitted here.

FIG. 7 is a diagram showing a third embodiment of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted here.

The difference between this embodiment and the embodiment shown in FIG. 2 is that an analog-to-digital converter (A / D) 71 is arranged downstream of the integrator 115 and the sample-and-hold circuit 2
3 and a comparator 116 in place of a flip-flop 72 and a digital comparator 73 for realizing equivalent functions using digital circuits.

FIG. 8 is an operation timing chart of the third embodiment. Hereinafter, the operation of this embodiment will be described with reference to FIGS. Analog-digital converter 71
Calculates the maximum value of the output of the integrator 115 at a period t in synchronization with the operation of the shift register 21 by using digital signals A, B, C,
D, E,... (FIG. 8). Flip-flop 7
2 holds the digital signal output from the analog-digital converter 71 with a one-cycle delay.

The digital comparator 73 includes the mixer 1
The noise power (indicated by data A, C,...) Obtained in the spread demodulated output during a period (FIG. 8) in which the PN code is given to the PN code 12 via the shift register 21 is used as a threshold. Is determined by the spread demodulation output (indicated by data B, D,...) Obtained during the period (FIG. 8) without passing through the shift register 21. A synchronization determination output similar to the example is obtained.

The operation of this embodiment is the same as that of the first embodiment except for the above-described points. Therefore, in FIG. 8, the timings and the like corresponding to FIG. Here, the description is omitted.

FIG. 9 is a diagram showing a fourth embodiment of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted here.

The difference between this embodiment and the embodiment shown in FIG. 7 is that the analog-to-digital converter 71 is relocated to the subsequent stage of the detector 114, and an equivalent function is replaced by a digital circuit instead of the integrator 115. And a digital integrator (INT) 91 realized by using

FIG. 10 is an operation timing chart of the fourth embodiment. Regarding the operation of the present embodiment, the detector 1
This is the same as the third embodiment except that the instantaneous value of the 14 output signal is converted into a digital signal via the analog-digital converter 71 and then integrated by digital processing of the digital integrator 91. In FIG. 10, FIG.
Are assigned the same numbers (-), and the description thereof is omitted here.

In each of the embodiments described above, a PN code is used as a spreading code for demodulation. However, the present invention is not limited to such a code, but a communication system or a distance measuring system to which the present invention is applied. For example, as described in the Journal of the Institute of Electronics, Information and Communication Engineers, August 1982 (pages 965 to 971), in addition to M-sequences, codes of G-sequences and K-sequences can be selected. Is similarly applicable.

Further, in these embodiments, the data selector 22 alternately selects the output of the PN code generator 111 and the output of the shift register 21 at a constant cycle, and
However, the present invention is not limited to such a cycle. For example, if the holding timing of the sample and hold circuit 23 and the flip-flop 72 and the delay time of the analog delay circuit 51 can be adapted, It is not necessary to make the period for selecting the two outputs the same.

Further, the amount of phase shift of the PN code (spreading code) by the shift register 21 is a value by which the autocorrelation value of the code becomes sufficiently small with respect to the maximum value and it can be determined that there is no correlation. If there is, it may be longer than the code length of the code.

In each embodiment, the comparator 116
By sampling the synchronization determination output by the flip-flop 24 disposed downstream of the digital comparator 73 and the digital comparator 73, it is possible to prevent the output indicating the loss of synchronization from being erroneously transmitted when the phase of the PN code (spreading code) is shifted. However, the present invention is not limited to such a method. For example, an integrating circuit is added to each of the above-described comparators, and the data selector 22 sets the shift register 21 only within a time smaller than the time constant of the integrating circuit. Erroneous transmission described above may be prevented by selecting the output of.

Further, in this embodiment, the comparator 11
6 or a digital comparator 73 that obtains a binary output is used. However, the present invention eliminates out-of-synchronization of a spreading code based on a threshold that is increased or decreased according to the level of noise obtained in the demodulated output as described above. As long as it can be detected, it is applicable even if a multi-valued output is obtained.

[0036]

As described above, in the present invention, the phase of the demodulation spread code is intermittently shifted by utilizing the fact that the noise component of the received frequency band has no correlation with the demodulation spread code. By doing so, the power level of only the noise component is obtained, and the threshold value is increased or decreased according to the power level.

That is, the threshold value has a fixed noise margin with respect to the power level of the noise superimposed on the primary modulated wave obtained by spread demodulation, so that even when the power level of the noise is large, Unlike the conventional example in which the threshold value is fixedly set, the noise is not erroneously recognized as the primary modulated wave, and the out-of-synchronization of the demodulation spreading code is reliably detected.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is an operation timing chart of the first embodiment.

FIG. 4 is a diagram showing an autocorrelation value of a PN code.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is an operation timing chart of the second embodiment.

FIG. 7 is a diagram showing a third embodiment of the present invention.

FIG. 8 is an operation timing chart of the third embodiment.

FIG. 9 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 is an operation timing chart of the fourth embodiment.

FIG. 11 is a diagram illustrating a configuration example of a conventional synchronization determination circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Spread demodulation means 11 13 Comparison means 15 Phase variable means 17 Threshold value variable means 21 Shift register (SR) 22 Data selector (SEL) 23 Sample hold circuit (S / H) 24, 72 Flip-flop (FF) 51 Analog delay line ( DL) 71 Analog-digital converter (A / D) 73 Digital comparator (CMP) 91 Digital integrator (INT) 111 PN code generator (PN) 112 Mixer 113 Low-pass filter 114 Detector 115 Integrator 116 Comparator

Continuation of the front page (56) References JP-A-58-218251 (JP, A) JP-A-59-169244 (JP, A) JP-A-63-97033 (JP, A) JP-A-1-220929 (JP) JP-A-2-22941 (JP, A) JP-A-2-39644 (JP, A) JP-A-61-248631 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB Name) H04J 13/00

Claims (1)

(57) [Claims] 1. A spread modulated wave whose spectrum has been spread over a wide band by a spread modulation process of multiplying a primary modulated wave by a modulation spread code in which an autocorrelation value sharply decreases near its maximum value. Spread demodulation means (11) for performing a spread demodulation process opposite to the spread modulation process based on the same spread code for demodulation as the spread code to obtain a power level of the demodulated output.
And a comparing means (13) for comparing the power level with a predetermined threshold value and detecting out-of-synchronization of the demodulation spreading code with respect to the spread modulation wave according to the comparison result. Phase varying means (15) for intermittently shifting the phase of the demodulation spreading code to a value at which the cross-correlation value between the spreading code and the modulation spreading code becomes smaller than the maximum value; and demodulation with the phase shifted. A threshold value changing means (17) for variably setting the threshold value according to the power level of the demodulated output obtained according to the spread code for use.