JPS609237A - Receiver of spread spectrum signal - Google Patents

Abstract

PURPOSE:To ensure the accurate demodulation by adding the output of a correlator and an averaging circuit and giving the output of the correlator which is set at a level zero in a non-correlation mode to a sample timing generating circuit after applying the digital integration to said output of the correlator. CONSTITUTION:A spread spectrum signal SA is applied to a correlator 2 and an averaging circuit 3, and signals SB and SC are delivered from the correlator 2 and the circuit 3 respectively. An adder 4 adds the signals SB and SC to obtain a signal SD which is set at zero in a non-correlation mode. This signal SD is converted by an A/D converter 5 and integrated by an integrator 10 to be applied to a sample timing generating circuit 14. Thus it is possible to demodulate accurately the data signal produced in the sample timing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to receivers for spread spectrum signals, and more particularly to producing a sample timing signal that provides timing for demodulating data from a spread spectrum signal.

<Prior art and its problems> Some conventional spread spectrum signal receivers are designed to demodulate a data signal from a spread spectrum signal in the following manner. The contents will be explained with reference to FIG. First, the carrier wave component part ωt is extracted from the received signal S (0) containing the data signal d (ri and PNN code (ri) by the carrier wave sampling circuit a. The spread spectrum signal d (L) P (ri) from the carrier wave sampling circuit a is The correlator takes the correlation between the same type of PNN code (ri) as that on the transmitting side. Then, the correlator outputs a data signal d (positive or negative depending on the +1 or -1 of the ri) as shown in Figure 2. A signal with sharp peaks is obtained.The correlator output containing this content is provided to the data demodulator C and the sample timing generator C.

The data demodulator C performs sampling in response to the sample timing of the sample timing generator e, and reads the sign of the peak value of the correlator output. In this way, the data signal d (0) is demodulated.The sample timing generator e determines the timing at which the peak of the output occurs when the output digital integral value of the correlator is equal to or higher than a predetermined value in each cycle of the PN code. Generates a timing signal.However, when the peak value of the output of the correlator is 1, the value when uncorrelated is 1/M (here, M is the number of bits in one cycle of the PN code), which is not zero. Therefore, the digital integral value of the sample timing generator e fluctuates, and especially during non-correlation, the digital integral value fluctuates over time even though the output of the correlator is a nearly constant value. Eventually, the digital integral value (Po in Figure 3) may exceed, for example, the negative threshold level -TH for generating the sample timing signal.
l(l''l: Positive threshold level.

For this reason, the sample timing generator e generates an erroneous sample timing signal, which is undesirable because it confuses the timing for data signal demodulation.

<Objective of the Invention> An object of the present invention is to generate a sample timing signal at accurate timing, thereby enabling accurate demodulation of data signal strength.

<Configuration and Effects of the Invention> For this purpose, the present invention averages the output of a correlator that correlates a spread spectrum signal with a PN code of the same type as that on the transmitting side, and outputs the averaged level of the spread spectrum signal. The output from the averaging circuit is added by an adder, and from this adder, the output of the correlator whose level is zero at the time of non-correlation is digitally integrated and provided to the sample timing generation circuit. Further, the sample timing generation circuit generates a sample timing signal when the peak value of the output obtained by digital integration of the correlator exceeds a threshold level, and supplies this sample timing signal to the sample circuit. Therefore, since the output level of the correlator via the adder at the time of non-correlation is zero, even if the correlator output is digitally integrated, the level of the non-correlation, especially the outlier, will not fluctuate, and therefore this output value will not change. The threshold level will no longer be exceeded when non-a is opened. Thus, according to the invention:
A sample timing signal for restoring a data signal from the correlator output is given to an accurate timing sample circuit, and effects such as accurate data demodulation are achieved.

<Description of Embodiment> FIG. 4 is an internal circuit diagram of a receiver in a spread spectrum communication system according to this embodiment. In Figure 4,
1 is the oscillator, 2 is the received spread spectrum signal SA
- This is a correlator that takes the correlation between [d(riku[)] and PN code P(ri).This correlator 2 has an analog shift register that transfers the oscillation output from the oscillator 1 and locks it, and a transmitter side. It includes a register with the same type of PN code and a product-sum circuit for the outputs of both registers. 3 is an averaging circuit which is the main part of this embodiment. This averaging circuit 3t receives the spread spectrum signal SA. The level of this signal SA is averaged, and the averaged output is outputted as a signal Sc. 4 indicates each signal SB from the correlator 2 and the averaging circuit 3.
, Sc, 5 is an A/D converter that A/D converts the output signal SD of the first adder 4, 6 is the second adder, and 7 is the output signal of the second adder 6. A memory for storing SB, 8 a counter, and 9 a write/read timing generation circuit. This counter 8il'' is counted up by the output from the oscillator 1, and this count period is P
It corresponds to the period of the NN code (RI).

The memory 7 receives the signal SE from the second adder 6 in response to the timing signal from the read/write timing generating circuit 9.
The writing and reading timings of the written signal SE are controlled, and the writing and reading addresses are controlled by the count value of the counter 8. The second adder 6 and this memory 7 are the digital integrator 1
It constitutes 0. Reference numeral 11 denotes a first comparison circuit that compares the magnitude of the output signal SE of the second adder 6 with the reference level TZ (with respect to which the output signal SE of the second adder 6 is compared). The signal SF is output only when 12 is a register into which the count value of the counter 8 is input and stores the count value at the time when the signal SF is output from the first comparator circuit 11; 13 is a register where the count value of the counter 8 and the stored count value of the register 12 are stored; This is a second comparison circuit which compares the inner inputs and outputs a predetermined signal SG when the two match.

The register 12 and the second comparison circuit 13 form a sample timing generation circuit 14. 15Vi second comparison circuit 1
3, the output signal SF is given as a sample gate signal, and by sampling the output of the correlator 2 in response to this sample gate signal SF, the signal "H" is converted into the data signal d(
This is a sample circuit to be restored as follows.

The operation of the receiving circuit constructed in this manner will be explained with reference to FIG.

Fig. 5(a) ll-j: shows the data signal d(ri), Fig. 5(b) shows the PN code P([), and Fig. 5(c) shows the spread spectrum signal formed by both signals. This spread spectrum signal SA is given to the correlator 2 and the averaging circuit 3. From the correlator 2, as shown in FIG.
A signal SB shown in is output. On the other hand, the averaging circuit 3 outputs a signal SC shown in FIG. 5(e)f.

The signal SB has a sharp peak on the positive side when there is a correlation, and becomes a negative level signal when the heel is out of phase. On the other hand, the average value signal Sc is a signal whose level is slightly more positive than the zero level. Therefore, when both signals SB and SC are added by the first adder 4, the added signal SD as shown in FIG. 5(f) is obtained.
becomes. As is clear from Fig. 5 ([), this signal S
D becomes zero level when there is no correlation. This signal SD is
After performing N/D conversion in the /D converter 5, the signal is applied to the second adder 6. The second adder 6 is co-located with the memory 7 and the digital integrator 1
0, so when the peak portion P1 of the first correlation output in FIG. 5(f) is written to the memory 7 and the next peak portion P2 is written to the memory 7, this peak portion P2 is Since this is added to the peak portion P+ currently written, the signal SE shown in FIG.
level increases. On the other hand, the threshold level rHHg5 of the first comparison circuit 11 is higher than the first peak portion PI in FIG.
2, the first comparison circuit 11 outputs a timing signal SF corresponding to the next peak portion P'2 in FIG. 5(g). register 12
When the timing signal SF is generated, the count value M of the counter q shown in FIG. 5 is stored. This count value M is outputted from the register 12 as shown in FIG. From the second comparison circuit 13i, the register 12
Each time the stored count value of the counter 8 matches the current count value of the counter 8, a signal SG as shown in FIG. 5(k) is generated. This signal SG is generated at a timing that coincides with the peak of the output SB of the correlator 12. The output signal SG of the second comparator 13 thus formed is sent to the sample circuit 15 as a sample timing signal. This signal S
At each falling timing of G, the sign of the peak value of the output signal SB of the correlator 2 at that time is read, and the data signal "H" is restored from the sample circuit 15 according to the value.

[Brief explanation of drawings]

Figure 1 is a diagram showing the signal processing of a conventional spread spectrum communication device, Figure 2 is a waveform diagram of the correlator output signal, and Figure 3 is a diagram showing the waveform of the correlator output signal in Figure 2. FIG. 4 is a circuit diagram showing the configuration of the spread spectrum communication device according to the present embodiment, and FIG. 5 is a timing chart of signals output from each part of the circuit shown in FIG. 4. 2...Correlator, 3...Averaging circuit, 4...Adder. Applicant: Tateishi Electric Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

[Claims] (1) Spread spectrum signal and PN of the same type as the transmitter side
A correlator that takes the correlation with the code, a sample circuit that reads the positive or negative of the peak of the output of this correlator in response to the sample timing, and a digital integral value of the output of the correlator for each cycle of the P/N code. and a sample timing generation circuit that generates the sample timing signal when the sample timing signal is greater than or equal to a predetermined value. By adding the output of the correlator and the output of the averaging circuit through the circuit, the output of the correlator whose level becomes zero at the time of non-correlation is digitally integrated and given to the sample timing generation circuit. Spread spectrum signal receiver.