JPH05175938A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To provide the system in which it is not required to increase the sampling frequency and the number of shift registers of a digital correlation device is not increased. CONSTITUTION:Noninverting and inverting sampling blocks ICLK, QCLK, the inverse of clock signals CLK, QCLK and either of PN code tip waveform of a COS or a SIN component from LPFs 14, 15 are given to steering gates 16-21 and A/D converters 22, 23, in which the code is subject to sampling and A/D- conversion. The level subjected to A/D-conversion and a prescribed reference level are given to correlators 24, 25, in which the correlation is obtained, there correlation output are processed through a subtractor, absolute value processing circuit 27 and when a comparator 28 discriminates it that a difference between the correlation values by the noninverting clock and the inverting clock does not reach a prescribed value, the noninverting clock and the inverting clock with a different phase from the noninverting clock and the inverting clock are switched by a command from a control circuit 30 to sample a PN code tip waveform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a spread spectrum communication device using a digital correlator.

[0002]

[Prior Art] Spread Spectrum Communication
m Communication (hereinafter referred to as SSC), in FIG.
As shown in, the pseudo noise code (Pseudo Noise c
ode (hereinafter referred to as PN code) is modulated, and the carrier signal is modulated by the modulated PN code and transmitted.

In FIG. 9A, 1 is data, 2 is a modulator,
3 is a PN code generator (hereinafter PN code)
G is referred to as G), 4 is a carrier signal generator, 5 is a modulator, and 6
Means antenna. On the receiving side, the signal is received as shown in FIG.
Data is demodulated by obtaining a correlation with the N code and processing an autocorrelation spike waveform having a relatively large amplitude that appears when both codes match and in the vicinity thereof.

In FIG. 9B, 7 is an antenna, 8 is a correlator, 9 is a reference PN code generator, 10 is a data demodulator, and 1 is a data demodulator.
1 means data. Here, as one of the correlators, there is a digital correlator. FIG. 10 shows a basic circuit configuration of the digital correlator. In the figure, S and R are shift _{registers, Ex-NOR 1 ~Ex-NOR} N is a NOR gate, ADD is an adder. The N-bit reference data REF is serially input to the N-bit shift register R in synchronization with the clock RCLK. Further, the information data DATA is serially input to the N-bit register S in synchronization with the clock SCLK. Then, the NOR gate detects the match / mismatch of the contents of the respective bits of the respective registers, and the total of the matched bits is obtained by the adder ADD.

FIG. 11 shows one of the constitutions when the digital correlator shown in FIG. 10 is applied to the SSC. In the figure, 1 and 2 are multipliers, 3 and 4 are low-pass filters (LPFs), 5 and 6 are A / D converters, 7 and 8 are digital correlators, and 9 is an adder. FIG. 12 shows Bi-Phase Shift Keying (BPS).
A modulated SS signal (hereinafter referred to as K) (hereinafter referred to as SS-BPSK) is received and data demodulation is performed.

The asynchronous demodulation operation of the SS-BPSK signal according to FIG. 11 will be described below. The SS-BPSK signal is
It can be expressed as Equation 1.

[0007]

[Equation 1]

In FIG. 11, as shown in FIG. 12, SS-B
The COS component and the SIN component are obtained by multiplying COSωt and SINωt, which are equal to the modulation carrier frequency of the PSK signal and the SS-BPSK signal, by multipliers 1 and 2, and a cutoff frequency equal to the PN code clock frequency is obtained from each component. Data is demodulated by extracting PN code chips by the low-pass filters LPF3 and 4 provided therein, A / D converting them with A / D converters 5 and 6, and then performing baseband processing with digital correlators 7 and 8. ..

That is, the digital data of the COS component and the SIN component is, for example, by the digital correlators 7 and 8 in which reference data equal to the result of the exclusive OR of the data "1" at the time of transmission and the PN code is set. The correlation value is calculated. Then, data demodulation is performed based on the value obtained by adding the correlation value by the adder 9.

[0010]

However, the above conventional digital correlator has the following problems. That is, when A / D converting the PN code chip waveforms obtained from the low-pass filters LPF5 and 6 of FIG. 11, ideally, it is the point where the PN code chip waveform has the most stable level as shown in FIG. It is desirable to sample points P at intervals equal to the PN code clock period.
However, it is difficult to sample point P in FIG. 13 by the asynchronous SS-BPSK demodulation method as shown in FIG. As an alternative measure, there is usually a method of increasing the sampling frequency. In this method, however, the information corresponding to one chip of the PN code increases as the sampling frequency increases, so that the number of shift register stages of the digital correlator increases. There was a need. For example, in the case of FIG. 13B as compared with the case of FIG. 13A, the sampling period T is set to 1/4, so that the number of shift register stages of the digital correlator is required to be four times.

An object of the present invention is to enable A / D conversion in the vicinity of the point where the level of the PN code chip waveform is stable, thereby increasing the sampling frequency and increasing the number of shift register stages of the digital correlator. Is to provide a method that does not need to be increased.

[0012]

In order to achieve the above object, an SS receiver of the present invention divides a received signal, and each branched signal is a carrier signal having a frequency equal to the modulation frequency of the received signal. And a branching conversion means for converting the first carrier signal based on the second carrier signal having a phase difference of π / 2 to obtain the COS component signal and the SIN component signal, and the COS and SIN component signals respectively. C
The first and second filters for extracting the OSPN code chip signal and the SINPN code chip signal, and the COSPN code chip signal and the SINPN code chip signal are supplied, and the chip signals are selectively selected according to the first control signal. Output first and second steering gates, a positive phase first clock having a period equal to the PN code chip width, and the first
A second steering gate for inputting a second clock whose phase is shifted by π / 4 with respect to the clock and selectively outputting them in response to a second control signal, the first clock and the second clock. A third steering gate and a fourth clock, which are respectively opposite in phase to the clock, are input, and a fourth steering gate that selectively outputs the clocks according to the second control signal, and the third and fourth steering gates. The fifth and sixth steering gates, which are supplied with the output of the fourth steering gate and selectively output the outputs according to the third control signal, and the output of the first steering gate,
A / D converting means for A / D converting the steering gate output of the second steering gate using the sampling clock, and the A / D conversion of the output of the second steering gate using the output of the sixth steering gate for the sampling clock. 2 A / D conversion means, a first digital correlator that correlates the output of the first A / D conversion means with a first pattern signal, and the output of the second A / D conversion means. Second
Of the second digital correlator that correlates with the pattern signal, the output of the first digital correlator, and the output of the second digital correlator, and a signal corresponding to the subtraction result, and Based on the output of the subtraction means that outputs a borrow signal indicating the polarity of the result, the comparison means that determines whether the subtraction result is within a predetermined range and outputs a determination signal, the output of the comparison means, and the state of the borrow output. And a control means for controlling the tearing gate by controlling the control signal.

[0013]

In the apparatus of the present invention, the PN code chip waveform of either the COS component or the SIN component is sampled and A / D by using the sampling clocks of the positive phase and the negative phase.
The correlation between the converted and A / D converted value and a predetermined reference value is obtained, and when the difference between the correlation values of the positive phase clock and the negative phase clock does not reach the predetermined value, the sampling clock of the positive phase and the negative phase On the other hand, the PN code chip waveform is sampled by switching to the sampling clocks of the positive phase and the negative phase having different phases.

[0014]

Embodiments of the present invention shown in the drawings will be described below.
FIG. 1 shows an embodiment of an SS receiver according to the present invention. In the figure, 10 is an antenna, 11 is a high frequency amplifier, 1
2 and 13 are multipliers, 14 and 15 are LPFs, 16-2
1 is a steering gate, 22 and 23 are A / D converters, 24 and 25 are digital correlators, 26 is a subtractor,
27 is an absolute value converter, 28 is a comparator, 29 is a threshold generator, and 30 is a control circuit.

In FIG. 1, as described above, the PN code chip waveforms of the COS component and the SIN component are input to the steering gates 16 and 19, and the steering gates 20 and 21 serve as sampling clocks used for A / D conversion. As shown in FIGS. 2A and 2B, a positive phase clock ICL having a cycle equal to the PN code chip width TPN.
K and π / 4 shift positive phase clock QCLK and negative phase clock bar ICLK and π / 4 shift positive phase clock bar QCL
K is input to the steering gates 17 and 18, and the positive-phase clock I that is the output of the steering gates 20 and 21.
CLK or QCLK and anti-phase clock bar ICLK
Alternatively, the bar QCLK is input. PN of COS component
The outputs SIG1 and CLK1 of the steering gates 16 and 17 are input to an A / D converter 22 that A / D converts the code chip waveform. The outputs SIG2 and CLK2 of the steering gates SG18 and SG19 are input to the AD converter 23 for A / D converting the PN code chip waveform of the SIN component.

The steering gate is, for example, a NAND gate NAND1 and an inverter INV shown in FIG.
Can be realized by a configuration using. In FIG. 5, when the select signal S1 is "1", the PN code chip waveform COS of the COS component is selected and output as SIG1. Also,
When the select signal S1 is "0", the PN code chip waveform SIN of the SIN component is selected and output as SIG1.

Select signals S1 and S4 are input to the steering gates 16 and 19 from the control circuit 30. In the initial state, the select signals S1 and S4 are "1" to select the PN code chip waveform of the COS component. To do. And
It is assumed that the select signal S5 is "1" to select the positive phase clock ICLK and the negative phase clock bar ICLK. Select signals S2 and S3 are input to the steering gates 17 and 18 from the control circuit 30. In the initial state, the select signal S2 is "1" to select the positive phase clock ICLK, and the select signal S3 is "0" to reverse. Phase clock bar IC
It is assumed that LK is selected.

Therefore, the A / D converter 22 converts the PN code chip waveform SIG1 of the COS component into the positive phase clock CLK1,
That is, sampling is performed with the positive-phase clock ICLK and A / D conversion is performed. Similarly, the A / D converter 23 has a PN of COS component.
Code chip waveform SIG2 (at this point, SIG1 = S
IG2) is sampled by the anti-phase clock CLK2, that is, the anti-phase clock bar ICLK, and A / D converted.
Sampling is performed, for example, when the rising edges of the positive phase clock ICLK and the negative phase clock bar ICLK are performed, and when one rising edge is sampling the stable point V ₂ as shown in FIG. The rising edge will sample 0 point V ₁ .

Output ADOUT of A / D converters 22 and 23
1 and ADOUT2 are digital correlators 2
4, 25, and the correlation value with the reference data preset in each digital correlator is obtained.
Next, the correlation outputs C1, C of the digital correlators 24, 25
2 is input to the subtractor 26, and the subtractor 26 calculates C1-C2 (2), and the output S of the subtractor 28 obtained as a result
UBOUT is input to the absolute value converter 27.

When the result of the equation (2) becomes negative and a borrow occurs, a borrow signal BORROW is input to the control circuit 30. The output SUBOUT of the subtractor 26 is the absolute value converter 2
7 becomes the absolute value output ABSOUT, and the comparator 28
Is compared with the threshold TH.

Now, as shown in FIG. 4A, the threshold value TH is π / 4 with the difference between the sampling values of the positive phase clock ICLK and the negative phase clock bar ICLK of the PN code chip waveform.
Corresponding to the difference V between the sampling values of the respective positive-phase clocks and negative-phase clocks, which is obtained when the sampling values of the shift positive-phase clock QCLK and the π / 4 shift negative-phase clock bar QCLK have the same temporal positional relationship. It is assumed that the value is set equal to the difference between the correlation values. The comparator 28 is
When the result of the equation (2) reaches the threshold value, the control circuit 30
The trigger signal COMPOUT is output to. Trigger signal C
OMPOUT causes the control circuit 30 to change the state of the select signal S4 from "1" to "0" without changing the state of the select signal S5 unless the borrow signal BORROW is input from the subtractor 26, and the SIN component is changed. The code chip waveform is selected, the select signal S3 is changed from "0" to "1", and the positive phase clock ICLK is selected. As a result, the configuration becomes equivalent to that shown in FIG. That is, the comparator 28 sends the trigger signal COMPOU
When T is output, the vicinity of the stable point of the PN code chip waveform is captured.

On the contrary, the trigger signal COMP is output from the comparator 28.
When OUT is not output, the control circuit CONT outputs the π / 4 shift positive phase clock QCLK as shown in FIG. 4B.
Or π / 4 shift reverse phase clock bar QCLK is P
It is determined that the vicinity of the stable point of the N code chip waveform is sampled, and the state of the select signal S5 is changed from "1" to "0", and the π / 4 shift positive phase clocks QCLK and π /
Switch to select the 4-shift antiphase clock bar QCLK. Then, the positive phase clock ICLK described above
The same operation as when using the opposite-phase clock bar ICLK is performed. FIG. 6A shows a timing chart of the above operation.

When the comparator 28 does not output the trigger signal COMPOUT using either the I or Q clock, the modulation carrier phase of the received SS-BPSK signal and the modulation carrier of the SS-BPSK signal on the receiving side. The phases of COSωt and SINωt that are equal to the frequency are SIN
Since there is a possibility that the coincidence with respect to ωt continues, the control circuit CON performs S operation to perform the above operation on the PN code chip waveform of the SIN component shown in FIG.
1, S4 is set to change the state from "1" to "0" so that the PN code chip waveform of the SIN component is selected. FIG. 7 shows a timing chart of the above operation.

The comparator 28 sends a trigger signal COMP.
When OUT is output, the subtractor 26 outputs a borrow signal BO
Reverse phase clock bar IC when RROW is input
Since it can be determined that the vicinity of the stable point of the PN code chip waveform is being sampled by LK or QCLK, the control circuit 30 changes the state of the select signal S2 from "1" to "0" and the reverse phase clock bar ICLK or Set to select bar QCLK. FIG. 8 shows a timing chart of the above operation.

[0025]

As described above, according to the present invention, S
In the S receiver, when data demodulation is performed using a digital correlator, the sampling frequency is increased and the PN is not increased without increasing the number of shift register stages of the digital correlator.
A / D conversion can be performed near the point where the level of the code chip waveform is stable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the above embodiment.

FIG. 3 is a waveform diagram for explaining the operation of the above embodiment.

FIG. 4 is a waveform diagram for explaining the operation of the above embodiment.

FIG. 5 is a block diagram showing a configuration example of a steering gate.

FIG. 6 is a timing chart for explaining the operation of the embodiment.

FIG. 7 is a timing chart for explaining the operation of the embodiment.

FIG. 8 is a timing chart for explaining the operation of the embodiment.

FIG. 9 is a block diagram showing a conventional SS communication system.

FIG. 10 is a block diagram showing a configuration example of a digital correlator.

FIG. 11 is a block diagram showing a conventional SS receiver using a digital correlator.

FIG. 12 is a vector diagram for explaining the operation of the conventional device.

FIG. 13 is a waveform diagram for explaining the operation of the conventional device.

[Explanation of symbols]

 12, 13 Multiplier 16-21 Steering gate 22,23 A / D converter 24,25 Digital correlator 26 Subtractor 27 Absolute digitizer 28 Comparator 30 Control circuit

Claims (1)

[Claims] 1. A received signal is branched, and each branched signal is divided into a carrier signal having a frequency equal to the modulation frequency of the received signal and a second carrier having a π / 2 phase different from that of the first carrier signal. Converted based on carrier signal, COS
A branching and converting means for obtaining a component signal and a SIN component signal; and a first for extracting a COSPN code chip signal and a SINPN code chip signal from the COS and SIN component signals, respectively.
And a second filter, first and second steering gates which are supplied with the COSPN code chip signal and the SINPN code chip signal, and selectively output the chip signals according to a first control signal, and a PN code A positive-phase first clock having a cycle equal to the chip width and a second clock having a π / 4 phase shift with respect to the first clock are input and selectively output according to a second control signal. A third steering gate, and a third clock and a fourth clock having opposite phases with respect to the first clock and the second clock, respectively, are input, and those clocks are input according to the second control signal. And a fourth steering gate for selectively outputting, and a fifth steering gate for selectively outputting the outputs of the third and fourth steering gates in response to a third control signal. And the steering gate of 6, the output of the first steering gate, the steering gate output of the fifth as a sampling clock A
A / D conversion means for A / D conversion, and an output of the second steering gate is used as an output of the sixth steering gate as a sampling clock.
Second A / D conversion means for D / D conversion, a first digital correlator that correlates the output of the first A / D conversion means with a first pattern signal, and the second A / D The second digital correlator that correlates the output of the conversion means with the second pattern signal, the output of the first digital correlator, and the output of the second digital correlator are subtracted, and the subtraction result And a subtraction means for outputting a borrow signal indicating the polarity of the result, a comparison means for judging whether or not the subtraction result is within a predetermined range and outputting a judgment signal, and an output of the comparison means. A spread spectrum receiving apparatus, comprising: a control unit that controls the control signal by controlling the steering gate based on a borrow output state.