JP2528744B2 - Delay detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit used for differential detection of a digital phase-modulated received signal.

[0002]

2. Description of the Related Art Delay detection is a detection method that uses a received signal one time slot before as a reference phase signal, and is characterized in that the circuit is simpler than synchronous detection. It is widely used in communication equipment that requires.

Conventionally, the above-described delay detection circuit delays the waveform of the received IF signal itself by one symbol to obtain the original IF signal.
A method is used in which the phase difference is determined by comparing it with the signal and used for demodulation. FIG. 2 is a diagram showing a configuration example when a conventional differential detection method is used for QPSK. The operation will be briefly described.

First, reference numeral 21 is a delay circuit, which stores a sequential waveform while sampling an input received signal IF with CLK to generate a 1-symbol delayed signal IF 'signal. This circuit can be composed of an N-stage shift register synchronized with CLK. This 1-symbol delay signal IF 'is output to two circuits. One is sent to the 90 ° phase shift circuit 22 and the other is sent to the phase difference determination circuit 24 and used for phase comparison of the I phase. The 90 ° phase shift circuit 22 produces a 1-symbol delay signal IF ″ used for Q-phase comparison and outputs it to the phase difference determination circuit 23.

Reference numerals 23 and 24 denote phase difference determination circuits, which are IF
And 1-symbol delay signal IF ′ (or its 90 ° phase shift signal IF ″) are compared to obtain the phase difference between the two inputs, and demodulation data DEM-I (or DEM-Q) corresponding to that value is determined and output. To do.

[0006]

However, in such a conventional method, the sampling CL supplied to the delay circuit 21 is used.
K must be operated at a frequency about 10 times or more higher than the received signal IF, resulting in a large power consumption. IF
The number of stages of the shift register that delays
The ratio of the sampling frequency of K and the frequency of the received signal IF is set to M, and the number of cycles of IF of 1 symbol time length is set to N.
Therefore, (M × N) steps are required. Therefore, there is a disadvantage that the scale of the circuit becomes large.

The present invention solves the problems of power consumption and circuit scale in the above-mentioned conventional method, achieves miniaturization and economy, and can perform delay detection without delay in performance. The purpose is to provide.

[0008]

A differential detection circuit according to the present invention is characterized by using a differential between a phase angle of a received signal and its delay value. That is, inputs the reception IF signal and the local oscillation signal to detect the phase difference daisy a phase difference
And a phase difference detection circuit for outputting phase information φ1 consisting of an absolute value converted to a Tal voltage value and a 1-bit positive / negative sign added to the most significant digit, and the phase information φ1 is stored for one symbol time and delayed. The phase change amount Δφ is calculated from the delay circuit which outputs as the phase information φ2, the phase information φ1 from the phase difference detection circuit and the delay phase information φ2 from the delay circuit, and the phase change amount Δφ is calculated as Threshold
(3/4) π, (1/4) π, − (1/4) π, − (3
/ 4) π, and Δφ ≧ (3/4) π, Δφ <− (3
/ 4) When π, the 1-symbol phase difference is determined to be π (or −π).
Data that matches the phase difference π is output as demodulation data.
Force, and if (1/4) π ≦ Δφ <(3/4) π, 1 thin
The phase difference was determined to be π / 2 and the phase difference was adapted to π / 2
The data is output as demodulated data, and − (1/4) π ≦ Δ
When φ <(1/4) π, the 1-symbol phase difference is determined to be 0.
And output data that matches the phase difference of 0 as demodulation data
However, when − (3/4) π ≦ Δφ <− (1/4) π, 1 series
The phase difference is determined to be -π / 2 and the phase difference is suitable for -π / 2.
And a determination circuit for outputting the combined data as demodulated data .

## EQU2 ## _Δφ = [φ1-φ2 + 3π] _mod2π- π

[0009]

[ _Formula 2] _Δφ = [φ1-φ2 + 3π] _mod2π− π ...
(1)

[0010]

1 is a block diagram showing an example of the configuration of a differential detection circuit according to the present invention. In the figure, 11 is a phase difference detection circuit, 12 is a delay circuit, and 13 is a determination circuit. Further, FIG. 3 shows a phase difference detection circuit 1 which is an essential part of the present invention.
It is a structural example figure showing the details of 1.

First, a brief description of each circuit in FIG. 1 will be given.
Phase difference detection circuit 11 inputs the received signal IF and LOCAL signal to detect the phase difference theta, a phase difference theta to the voltage level
This is a circuit for converting and outputting phase information φ1 to which delay / advance information is added . The delay circuit 12 is a circuit which inputs the phase information φ1 and stores Φ1 for one symbol for one symbol by using CLK synchronized with one symbol speed as a trigger and outputs it as the delay phase information φ2. The determination circuit 13 uses the phase information φ1 and the delayed phase information φ2.
Input and, and obtain the amount of phase change Δφ by equation (1),
This is a circuit for outputting demodulated data in which the value of the phase change amount Δφ is determined by four threshold values.

[0012]

Next, the operation of the present invention based on the configuration example of FIG. 1 will be described. First, the phase difference detection circuit 11 will be described with reference to FIG. In FIG.
31 is an exclusive OR circuit (EXOR circuit), 32 is D-
F / F (flip-flop), 33 is a low-pass filter (LP
F) and 34 are analog / digital converters (A / D). FIG. 4 is a phase comparison characteristic diagram of each part of the circuit of FIG.
(A) shows the characteristics of the output a of the LPF 33, and (B)
Indicates the characteristic of the output b of the D-F / F 32. (A),
(B) both the horizontal axis, and LOCAL (local oscillator) based on the signal of the phase (theta = 0) to display the phase difference theta reception IF signal thereto. The vertical axis I in (A) represents the output voltage of the LPF 33.
It represents the normalized voltage with the maximum value as 1, and the vertical axis K of (B) is
For example, the H level of 5 V of the binary output of D-F / F32 is set to 1
Represents the normalized voltage as. Received signal IF and LOCA
The L (local oscillation) signal is input to the EXOR circuit 31, and 2
The signal phase difference θ is output as a binary voltage value . As shown in FIG. 4 (A), the signal a obtained by passing the phase difference θ through the LPF 33 is represented by the absolute value of the voltage in the range of I = 0 to 1. That is, the phase difference is converted into a voltage, and the EXOR circuit
When "1" continues as the output of 31, I = 1
Therefore, when "0" continues, I = 0 and "1",
When “0” is mixed, it becomes an intermediate value of I = 0 to 1.
It This analog voltage is quantized by the A / D converter 34 and converted into a digital value, which is a multi-bit electric signal corresponding to the phase difference θ.
The absolute value of pressure is used as one piece of phase difference information. On the other hand, the reception signal IF and the LOCAL signal are also input to the D-F / F (flip-flop) 32, and the output b of the D-F / F (flip-flop) 32 is shown in the phase comparison characteristic of FIG. As described above, when the phase difference θ is in the range of 0 to π, K =
1, and a K = 0 when the range of 0 to-[pi.
That is, the output b is the two values, the received signal IF is LOC
A positive or negative sign indicating whether it is behind or ahead of the AL signal is shown by 1 bit. Using this as another phase difference information, the above-mentioned output from the A / D converter 34 is performed.
The information added to the most significant digit (MSB) of the information indicating the multi-bit absolute value of is output as the phase information φ1. That is, the phase difference detection circuit 11 detects the phase difference θ between the reception signal IF and the LOCAL signal, and the 1-bit sign and the absolute value indicating positive or negative
And phase information φ1 including multi-bit information indicating

The difference from the conventional method of the present invention is that the LOC of the received signal IF has already been reached at the stage of passing through the phase difference detection circuit 11.
Absolute value of phase delay / lead and phase difference θ with respect to AL signal
And extracting phase information comprising (voltage level), the IF symbols as in the conventional circuit is that it does not use as is. In this way, the phase difference θ is converted to voltage
By performing the subsequent processing, the redundancy of the stored data can be omitted and the circuit can be simplified and downsized.

Returning to FIG. 1, the phase information φ1 is the delay circuit 12
, And as described above, φ1 is stored between symbols by using CLK as a trigger and output as delay phase information φ2. This circuit can be easily realized by a shift register having a data bit width of phase information φ1. Further, when the ratio of the frequency of CLK used as a trigger to the transmission rate is set to L, L may be about 10 or more, and the required number of shift register stages may be M. Therefore, about M times the reception signal IF frequency ( M ≧ 10) clock and (M
The frequency is considerably lower than that of a conventional circuit that requires (N) stage registers (N is the number of cycles of one symbol time length), which is a great advantage in terms of power consumption and circuit scale.

Next, the decision circuit 13 demodulates . Determine Teikairo 13 includes a phase information φ1 from the phase difference detecting circuit 11 and the delay phase information φ2 from the delay circuit 12 is input,
According to the equation (1), the phase information φ1 of the current symbol and the immediately preceding
The phase change amount Δφ with the phase information φ2 of the symbol
Domain by four thresholds the value of the phase variation Δφ
Is a circuit that outputs the demodulated data that has been determined. Here, the formula (1) will be described in detail. FIG. 6 is an explanatory diagram of the process of deriving the equation (1). (A) is the LOCAL signal
The relationship between the phase difference θ of the received IF signal and the phase difference information φ1 output from the phase difference detection circuit 11 is shown. The vertical axis is Fig. 4
The normalized voltage is shown in the same manner as . (B) is currently <br/> difference normalized voltage between the delay phase information .phi.2 outputted from the phase information, that the delay circuit 12 of the phase information .phi.1 and the immediately preceding symbol of the symbol a (φ1-φ2) and the horizontal axis, the Difference (φ1-φ2)
The relationship is shown with the corresponding phase difference Δφ as the vertical axis. That is, for the LOCAL signal of the current symbol
From the phase difference φ1 to the LOCAL signal of the immediately preceding symbol.
Of the LOCAL signal by subtracting the phase difference φ2
The phases of the current symbol and the immediately preceding symbol due to the cancellation of the components
It shows that the change amount Δφ can be obtained. This phase difference Δφ changes in the range of 4π from −2π to 2π, but in the case of phase modulation, the transmission data is always assigned in the range of 2π (−π to π), and the range beyond that is the range of 2π. Is repeated (mod2π). In the case of QPSK, -π
Since 4-valued data (0, ± π / 2, π or −π) is assigned to the range of up to π, 4 is required to make the demodulation determination.
Although one threshold value is sufficient, if the characteristics shown in FIG. 6B are to be determined, eight threshold values are required and the circuit configuration becomes complicated. Therefore, the normalized voltage in FIG.
Maintains the characteristic that Δφ passes the origin and rises constantly in the range of
Then, at the points where the normalized voltage is -1 and 1, Δφ changes from π to -π.
A phase jump occurs, and Δφ corresponding to −2 to 2 falls within the range of −π to π.
To obtain the characteristic of repeating a sawtooth shape,
Use Juro arithmetic. However, the modulo operation of 2π is performed.
Therefore, it is necessary to make the value of Δφ of the characteristic of (B) a positive value.
It Therefore, if 2π is added to Δφ, the phase jump point becomes
The normalized voltage is 0, and the Δφ characteristic in the range of −1 to 1 is
I can't keep up. Therefore, add 3π to the characteristic of (B)
The characteristic of the broken line in (C) is used, and the characteristic of the broken line is 2π.
After performing the uro operation, the characteristics of the solid line in (C), that is, the range of Δφ
Sawtooth-like properties with an enclosure between 0 and 2π are obtained. next,
Since the solid line characteristic is a characteristic that passes through the origin, π is subtracted to obtain the characteristic shown in FIG. The characteristics of this FIG.
Is the equation (1). The horizontal axis value in FIG. 5 is different from the horizontal axis value in FIG. 6C, but the relationship between the normalized voltage and the phase change amount is shown.
Are in a one-to-one correspondence as shown in FIG.
You may consider it the same.

FIG. 5 is a four-value judgment characteristic diagram used in the present invention, and shows the characteristic of the equation (1). Each of the four dash-dotted lines indicates a threshold value. As is clear from Fig. 5, (1)
Δφ obtained by the equation is the phase information φ1 of the current symbol.
The difference (φ1−φ2) of the delay phase information φ2, which is the phase information of the immediately preceding symbol, extends to the range of −2π to 2π, and the data area is determined by four threshold values in the range of −π to π. It means that you can do it. As described above, the determination circuit 13 first calculates the difference (φ1−φ2) between the two inputs of the phase information φ1 and the delay phase information φ2,
Next, Δφ is calculated by the equation (1), and the area of Δφ is determined by four threshold values to output demodulated data.

From the above, the structure of the present invention can be applied to, for example, four-phase P
When used for demodulating an SK signal, Δθ = 0, ± π / 2, π
(Or −π) for four types of phase changes, 0, ± π / 2, π (or −π) according to the threshold values shown by the one-dot chain line in FIG. 5, ± 1 / 4π, ± 3 / 4π It can be seen that the demodulation circuit can be easily configured by setting the determination region divided by.

As the decision circuit 13 for realizing the above-mentioned function, for example, ROM (φ1 and φ2 in FIG. 1 is used as an address input, and the decision value to which the phase change amount Δφ obtained by the equation (1) belongs is stored as ROM ( Read Only
It can be easily configured by Memory.

[0019]

As described in detail above, according to the present invention, it is possible to reduce power consumption, which is a problem in the conventional method, and it is possible to downsize the circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a differential detection circuit according to the present invention.

FIG. 2 is a diagram showing a configuration example of a conventional differential detection circuit.

FIG. 3 is a configuration example diagram of a phase difference detection circuit which is a main part of the present invention.

FIG. 4 is a phase comparison characteristic diagram at points a and b in FIG.

FIG. 5 is a diagram showing a four-value determination characteristic example when the present invention is used for QPSK.

FIG. 6 is an explanatory diagram of the derivation process of the equation (1) of the present invention.

[Explanation of symbols]

 11 phase difference detection circuit 12 delay circuit 13 determination circuit 21 delay circuit 22 90 ° phase shift circuit 23 phase difference determination circuit 24 phase difference determination circuit 31 EXOR circuit 32 D flip-flop 33 LPF 34 A / D converter

Claims (1)

(57) [Claims] 1. A received IF signal and a local oscillation signal are input, a phase difference between them is detected, and the phase difference is converted into a digital voltage value.
And a phase difference detection circuit for outputting phase information φ1 consisting of a 1-bit positive / negative sign added to the most significant digit thereof, and the phase information φ1 is stored for one symbol time and output as delay phase information φ2. a delay circuit for phase information φ1 and the calculated the number 1 phase variation Δφ from the delay phase information φ2 Prefecture from the delay circuit the phase variation Δφ the four threshold (3 from the phase difference detecting circuit / 4) π, (1
/ 4) π, − (1/4) π, − (3/4) π,
When Δφ ≧ (3/4) π and Δφ <− (3/4) π, 1 series
The phase difference is determined to be π (or −π) and suitable for the phase difference π.
The combined data is output as demodulation data, and (1/4) π
When ≦ Δφ <(3/4) π, the phase difference of one symbol is π / 2.
The data that is determined to be the phase difference π / 2 is demodulated data
Output as − (1/4) π ≦ Δφ <(1/4) π
When the 1-symbol phase difference is judged to be 0,
Output data as demodulated data, and − (3/4) π ≦
When Δφ <-(1/4) π, the phase difference of one symbol is -π /
2 and the data that matches the phase difference −π / 2 is demodulated and demodulated.
A differential detection circuit including a determination circuit that outputs the data. ## EQU1 ## _Δφ = [φ1-φ2 + 3π] _mod2π- π