JPH07221802A - Digital demodulator - Google Patents

Abstract

PURPOSE:To make the size small and to reduce power consumption by digitizing the entire demodulator and integrating it into one IC together with a signal processing circuit. CONSTITUTION:A modulation signal is given to an A/D converter 14, where the signal is sampled and converted into a digital signal, that is, modulation wave signal data. A phase of a carrier is controlled in a carrier wave phase control circuit 16 according to information from a tan<-1> conversion memory 18 and phase information is outputted from the control circuit 16. The digital signal from the A/D converter 14 as a high-order address and carrier phase information as a low-order address are given to 1st and 2nd multiplier memories 20, 22 respectively. Then the tan<-1> transformation memory 18 receiving data Ii, Qi from 1st and 2nd moving average digital filters 24, 26 provides an output of tan<-1> (Ii/Qi) based on a designated address and the entire circuit is integrated into one IC.

Description

Detailed Description of the Invention

[0001]

This invention relates to digital demodulators. More specifically, the present invention relates to a digital demodulator used in a digital transmission system and demodulating a modulated wave signal in which a carrier signal is modulated with a digital baseband signal.

[0002]

2. Description of the Related Art Conventionally, in a digital transmission system, digital information or data is transmitted by modulating a carrier signal with a digital baseband signal. As this modulation method, an amplitude modulation method (ASK: Amplitude Shift Ke) that changes the amplitude of a carrier signal according to a digital baseband signal (modulation signal) is used.
quadrature amplitude modulation method (QA) in which the amplitude and phase of the carrier signal are independently changed according to the modulation signal.
There are various modulation methods such as M: Quadrature Amplitude Modulation.

In such a modulation system, the modulated wave signal S (t) modulated by the modulated signal can be expressed as follows.

[0004]

[Number 1] S (t) = A (t ) · cos (ω c t + φ (t)) = I (t) · cosω c t + Q (t) · sinω c t here, I (t) = A ( t ) ・ Sin φ (t), Q (t)
= A (t) · cos φ (t), A (t) is the amplitude, ω _c is the frequency of the carrier signal, and φ (t) is the phase of the modulated wave signal.

As is clear from equation 1, the modulated wave signal is
It can be represented by the sum of two orthogonal components, and the first term is generally referred to as the in-phase (I phase) component of the modulated wave signal and the second term is referred to as the quadrature phase (Q phase) component of the modulated wave signal. Synchronous detection, differential detection, frequency detection, etc. can be used to demodulate the baseband signal from the modulated wave signal, but under conditions such as satellite communication and satellite broadcasting where the signal to noise ratio (C / N) is low. Generally, synchronous detection with good demodulation performance is used.

In the synchronous detection method, a reference signal having the same frequency and phase as the carrier wave of the modulated wave signal is generated from the received modulated wave signal (carrier wave reproduction), and the modulated wave signal is quadrature detected by this reference signal. , Retrieve the baseband signal. To regenerate the carrier wave,
Although various methods such as a multiplication method, a Costas method, and an inverse modulation method can be used, the Costas method is often used in consideration of the circuit scale and the performance at low C / N.

As shown in FIG. 26, the Costas system is composed of a quadrature detector, a low pass filter (LPF), a voltage controlled oscillator (VCO), a loop filter, and a multiplier. The I-phase and Q-phase baseband signals demodulated by the quadrature detector and the LPF are multiplied, and a low-pass component proportional to the phase difference between the carrier and the reference signal is extracted from the multiplied signal by a loop filter. The reference signal is synchronized with the carrier by controlling the VCO with the signal. Therefore, many analog circuits such as a filter and a VCO are used in the circuit forming the Costas system. For example, at present, Q for PCM audio of BS broadcasting is used.
In ICs and the like that are commercially available as PSK (Quadrature-PSK) demodulators, most of the ICs are configured by analog circuits. Also, these ICs generally require many external components.

[0008]

Since the conventional synchronous detection (Costas method) is mainly composed of analog circuits, many external parts are required even if the circuits are integrated into an IC.
Not suitable for miniaturization. In addition, since a bipolar process is used in manufacturing an IC, it is technically and economically difficult to put it in one IC together with a signal processing unit composed of a digital circuit connected to the subsequent stage of the IC. Difficult to do.

[0009]

A first invention is an analog / digital conversion means for sampling a modulated wave signal and converting it into modulated wave signal data, a first phase data output means for outputting phase data of a carrier wave signal, A multiplication result data storage unit that stores the multiplication result of the modulation wave signal and the carrier wave signal and outputs the multiplication result data from the address specified by the modulation wave signal data and the carrier wave phase data, and is included in the modulation wave signal from the multiplication result data. It is a digital demodulator provided with a modulation signal data output means for extracting data of a modulation signal and a second phase data output means for outputting phase data of a modulation wave signal from the modulation signal data.

A second invention is an analog / digital conversion means for sampling a modulated wave signal and converting it into modulated wave signal data, a first phase data output means for outputting phase data of a carrier wave signal, a modulated wave signal and a carrier wave signal. Multiplication result data storage means for storing the multiplication result with and for outputting the multiplication result data from the address designated by the modulated wave signal data and the carrier phase data, the sign changing means for changing the sign of the multiplication result data, and the sign changing means. Modulation signal data output means for extracting the data of the modulation signal included in the modulation wave signal based on the output multiplication data having the changed sign, and the second phase data for outputting the phase data of the modulation wave signal from the modulation signal data. It is a digital demodulator having output means.

[0011]

The modulated wave signal data from the analog / digital converting means is applied to, for example, the upper address of the multiplication memory, and the phase data of the carrier signal from the first phase data output means is applied to the lower address of the multiplication memory. Accordingly, the multiplication result data obtained by multiplying the amplitude value data of the modulated wave signal and the amplitude value data of the carrier wave signal is output from this multiplication memory.

In the first invention, the multiplication result data is unchanged, and in the second invention, the code is changed by the code changing means and is given to the modulation signal data output means such as a moving average type digital filter. The modulation signal data output means extracts the modulation signal data by removing unnecessary components from the multiplication result data. Therefore, the modulation signal (digital baseband signal) can be reproduced or demodulated based on the modulation signal data.

The second phase data output means, which is, for example, a tan ⁻¹ conversion memory, outputs the phase data of the modulated wave signal based on the modulated signal data. Therefore, the first phase data output means controls the phase of the carrier wave signal to match the phase of the modulated wave signal according to the phase data of the modulated wave signal.

[0014]

According to the present invention, since all the demodulators can be digitized, the size and power consumption can be reduced, and the demodulators can be incorporated in one IC together with the signal processing unit, thereby achieving high reliability. be able to. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Digital demodulator 10 of the embodiment shown in FIG.
Includes an input terminal 12 to which a modulated wave signal is supplied. The modulated wave signal is supplied to an analog / digital converter 14, where it is sampled and converted into a digital signal, that is, modulated wave signal data. In the carrier wave phase control circuit 16, the phase of the carrier wave is controlled according to the information (phase information of the modulated wave signal) from the tan ⁻¹ conversion memory 18,
Carrier wave phase information is output from the carrier wave phase control circuit 16.

The first multiplication memory 20 is provided with a digital signal from the analog / digital converter 14 as an upper address and carrier phase information as a lower address. From the first multiplication memory 20, data obtained by multiplying the sampled modulated wave signal by the sine wave (carrier wave) based on the designated address, that is, the phase information supplied from the carrier wave phase control circuit 16 is shown. The multiplication result data obtained by multiplying the amplitude of the sine wave (carrier wave) and the amplitude of the sampled modulation wave signal in the phase to be read is read. The second multiplication memory 22 is provided with the digital signal from the analog / digital converter 12 as an upper address and the carrier phase information as a lower address. From the second multiplication memory 22, based on the specified address, the amplitude of the modulated wave signal sampled,
Data (multiplication result data) obtained by multiplying the sine wave of the first multiplication memory 20 by the amplitude of the sine wave whose phase is shifted by π / 2 is read.

First moving average type digital filter (FIR digital filter in which all tap constants are 1) 2
Reference numeral 4 includes a shift register that shifts and delays the multiplication result data from the first multiplication memory 20, and a configuration that adds the data from the shift register and outputs the addition result. The second moving average type digital filter 26 includes a shift register for shifting and delaying the multiplication result data from the second multiplication memory 22 and a configuration for adding the data from the shift register and outputting the addition result.

First moving average type digital filter 24
Data (modulated signal data) from tan ^-1 conversion memory 1
8 is given as the upper address, and the data (modulation signal data) from the second moving average type digital filter 26 is given as the lower address. This tan ^-1
The conversion memory 18 stores the data (Ii) from the first moving average type digital filter 24 and the second moving average type digital filter 26 based on the designated address.
It outputs tan ^-1 (Ii / Qi) from the data (Qi) from.

In the multiplication processing section of the analog quadrature modulator shown in FIG. 2A, in order to convert the multiplication signal into a digital signal (I component is MI and Q component is MQ), each mixer or multiplication unit is used. The analog / digital converter is used after the converter. 2B is a circuit in which the circuit of FIG. 2A is realized by a digital circuit. A digital multiplier is used instead of the mixer, and a sine wave data generation circuit is used instead of the analog oscillator. This Figure 2
In the configuration of (B), since it is necessary to input a digital signal to each digital multiplier, the modulated signal is directly converted into a digital signal by the analog / digital converter.
Since the circuit of FIG. 2 (B) only digitally achieves the processing of the circuit of FIG. 2 (A), the digital signal output from each digital multiplier is analog / digital converted in FIG. 2 (A). Data MI obtained from the instrument
And MQ are exactly the same.

In the circuit shown in FIG. 2B, the output of the sine wave data generation circuit applied to each digital multiplier becomes the data shown in FIG. FIG. 3 shows FIG.
An example in which the sampling frequency of the analog / digital converter in (B) is set to four times the center frequency of the modulation signal is shown. Such a sine wave data generation circuit outputs a digital signal representing a sine wave having the center frequency of the modulation signal at the same timing as when the modulation signal is converted into a digital signal in the analog / digital converter. That is,
If the sampling frequency of the analog / digital converter in FIG. 2B is N times the modulation signal (referred to as N times oversampling), the sine wave data generation circuit has a phase of 2
The amplitude value data of the sine wave at positions separated by π / N may be sequentially output. In the example of FIG. 3, since N = 4,
The amplitude value data of the sine wave at the position where the phase is separated by π / 2 is output. Further, since it is necessary to change the phase of the sine wave applied to the first digital multiplier and the second digital multiplier of FIG. 2B by π / 2, the phase of π / 2 is generated when the sine wave data is generated. Different sine wave data may be generated independently and given to each digital multiplier. In this way, the carrier signal is modulated by the digital baseband signal (modulation signal), but demodulation is the reverse of modulation,
The modulated wave signal data may be multiplied by the carrier wave (sine wave) data.

Returning to FIG. 1, the multiplication operation for quadrature detection in this embodiment will be described. The modulated wave signal input from the input terminal 12 is converted into a digital signal (modulated wave signal data) by the analog / digital converter 14 at a sampling frequency N times that of the modulated wave signal, and then the first multiplication memory 20 and the first multiplication memory 20 It is supplied as each upper address of the multiplication memory 22. The phase information or data of the sine wave (carrier wave) output from the carrier wave phase control circuit 16 is supplied to each lower address of the first multiplication memory 20 and the second multiplication memory 22.

The first multiplication memory 20 and the second multiplication memory 22 have different structures from each other, for example, as shown in FIG. Note that FIG. 4 shows data when the phase data of the sine wave (carrier wave) output from the carrier wave phase control circuit 16 is 5 bits (data obtained by dividing the sine wave by 2 ⁵ = 32). At this time, if the modulated wave signal is quantized by n bits, 2 ⁿ for each phase of the carrier signal
There are x multiplication results. Therefore, if the carrier phase information is m bits, each of the multiplication memories 20 and 22 has 2 bits.
^m × 2 ⁿ = 2 ^{m + n} sets of multiplication result data are stored in advance.

Assuming that the carrier phase data is "1" represented by a decimal number and the modulated wave signal data from the analog / digital converter 14 at that time is "A", this modulated wave is obtained. The multiplication result data (A × d1) stored in advance corresponding to the signal data A (upper address) and the carrier wave phase data “1” (lower address) is the first
It is read from the multiplication memory 20. On the other hand, the upper address and the lower address are also supplied to the second multiplication memory 22, and the sine wave (carrier wave) in the first memory 20 stored in advance in the second multiplication memory 22 is π /
The multiplication result data (A × d9) between the amplitude value of the sine wave and the modulation wave signal data A, which are out of phase by 2, is the second multiplication memory 2
It is read from 2. In this way, the multiplication process (quadrature detection) is performed using the multiplication memories 20 and 22.

Next, the filter processing will be described. Figure 1
In the embodiment, as the low pass filter, a digital filter as shown in FIG. 5 is used instead of the conventional analog filter. This digital filter is composed of a plurality of stages and shift registers for sequentially shifting data to each stage,
And an adder for adding the output of each stage of the shift register. When new data is input to this digital filter one after another, the data is sequentially shifted to each stage of the shift register, the adder adds the outputs of each stage for each shift operation, and the addition result is It is the output of the digital filter. Since this addition result is the average value of M data, it is also called a moving average. When the number of addition data of the digital filter is M, the frequency characteristic of this digital filter is such that the attenuation becomes infinite every ft / M (ft: transfer frequency of shift register) (that is,
Knot) is formed. For example, in this embodiment, since the transfer frequency ft of the shift register is the sampling frequency fs, as shown in FIG. 6, there can be a node every fs / M.

FIG. 7 shows a state in which the multiplication data obtained by the above-described multiplication processing is input to this digital filter. In this example, the sampling frequency fs is four times as high as the frequency of the input signal (modulated wave signal).
As in (A), an unnecessary component of the multiplication result data is generated at a half of the sampling frequency. Since this unnecessary component is located in the section of the moving average type digital filter when M = 4 = N (N is the number of oversampling of the modulated wave signal described above), the moving average type digital filters 24 and 26 have the first component. When the multiplication result data output from each of the multiplication memory 20 and the second multiplication memory 22 is input, an unnecessary component included in each multiplication result data is attenuated and only necessary modulation signal data (digital baseband signal data) is extracted. be able to. Generally, when the input signal is sampled at a frequency of N times and the above-mentioned multiplication processing is performed, an unnecessary component is generated at a position of 2 · fs / N.
Therefore, in order to remove this with the moving average type digital filter, a digital filter having addition data of K times N / 2 (K is an integer) may be used as shown in FIG. In the above description, N = 4 and M = 2 · N /
This is the case when 2 = 4.

Next, digital filters 24 and 26
The I component data (Ii) of the baseband signal extracted by is given to the upper address of the tan ⁻¹ conversion memory 18 (FIG. 1), and the Q component data (Qi) is given to the lower address of the tan ⁻¹ conversion memory 18. To be Correspondingly, the phase data (θi = tan that has been calculated and stored in advance from the memory area indicated by the address of the tan ⁻¹ conversion memory 18
^-1 (Qi / Ii)) is read. In this way
The instantaneous phase of the modulated wave signal is detected. The tan ^-1 conversion memory 18 is configured as shown in FIG. That is, Q
When i is positive, θi is 0 to π, and when Qi is negative, θi is a value of 0 to −π, and 8-bit quantized data is assigned to this θi as shown in FIG.

Next, the operation of the carrier wave phase control circuit 16 will be described by taking QPSK (four phase modulation), which is one of the phase modulation systems, as an example. The digital demodulator of the present invention can be applied to other modulation systems, but other modulation systems will be described later. QPSK has 2 data
As shown in FIG. 10, it is a method of allocating one set for each bit to each phase, and each signal point is arranged on the circumference at equal intervals of π / 2. The actual modulated wave signal is
As shown in FIG. 11, data (I) corresponding to the I axis is multiplied by a carrier wave, and data (Q) corresponding to the Q axis is multiplied by a sine wave having a phase difference of 90 ° from the carrier wave. It is composed by adding the ingredients together. Therefore, in order to accurately detect the phase of the modulated wave signal,
In the demodulator, it is necessary to perform the above-mentioned quadrature detection using a sine wave whose frequency and phase match the carrier wave of the modulated wave signal.

In the digital demodulator 10 of FIG. 1 embodiment, the carrier phase control circuit 16 causes the multiplication memories 2
The carrier wave phase information (data) given to the lower addresses of 0 and 22 is controlled so that the carrier wave contained in the modulated wave signal has the same frequency and phase. That is, since the carrier phase information is generated from the demodulator reference oscillator,
In the uncontrolled state, the carrier wave of the modulated wave signal is slightly different in frequency and phase. Here, assuming that the phase from the carrier wave phase control circuit 16 leads the phase of the carrier wave included in the modulated wave signal, the coordinate system (I'-Q ') based on this carrier wave phase is included in the modulated wave signal. As shown in FIG. 12, the coordinate system is rotated leftward by the phase difference (θ) with respect to the coordinate system (I-Q) based on the transmitted carrier wave. Therefore, the signal point phase detected by this carrier wave phase is the normal signal phase (π /
It becomes smaller than 4). On the contrary, when the carrier wave phase lags the carrier wave phase included in the modulated wave signal (coordinate system I ″ -Q ″), the detected signal point phase is as shown in FIG.
As shown in, the signal phase becomes larger than the normal signal phase.

Considering the relationship between the phase data output from the tan ^-1 conversion memory 18 of FIG. 9 and the signal point phase, FIG.
As shown in (A), the most significant bit (MS
A quadrant in which a signal point exists is indicated by a total of 2 bits including B) and the following 1 bit. The 3rd bit from the MSB has a signal point phase larger or smaller than π / 4 in the quadrant (of “1”). When it is "0", it is smaller than π / 4). FIG. 13B is a diagram in which all the quadrants are overlaid on the first quadrant. In all the quadrants, when the signal point phase is larger than π / 4, the third bit from the MSB is “1”. On the contrary, when the signal point phase is smaller than π / 4, it becomes “0”. That is, when it is in one of the four shaded areas in FIG. 13A, the third bit from the MSB is "1", and when it is outside the shaded area, it is "0". Applying the above relationship to the relationship between the carrier wave phase and the carrier wave included in the modulated wave signal, when the third bit from the MSB is “1” (that is, within the shaded area), the carrier wave phase becomes the modulated wave signal. When it is behind the phase of the carrier wave included therein and is “0” (that is, outside the shaded range), the carrier wave phase is ahead of the phase of the carrier wave included in the modulated wave signal. In the carrier wave phase control circuit 16, 3 is obtained from the MSB of this phase data.
The carrier phase is controlled by using the bit number to identify the lead / lag between the carrier phase and the phase of the carrier included in the modulated wave signal.

FIG. 14 shows the configuration of the carrier wave phase control circuit 16 of this embodiment. The adder 28 and the adder 28 are shown in FIG.
Selector 30 for selecting the addition data to be input to three, and three memories 32, 34 and 3 storing the addition data
Including 6. Consider the case where the carrier phase information is 5 bits (see FIG. 4) and the modulated wave signal is sampled by 4 times oversampling (see FIG. 3). The adder 28 is
It is a cumulative adder that adds the addition data output from the selector 30 to the previous carrier phase information to generate the next carrier phase information, and the addition data output from the selector 30 indicates the phase increase amount of the carrier. In the case of 4 times oversampling, the carrier phase information interval is π as shown in FIG.
/ 2 and since, if the carrier information is 5 bits, the sum data falls phase increment may be a 2 ^5/4 = 8. Generally, if the carrier phase information is m bits and N times oversampling is performed, the addition data may be 2 ^m / N.

Now, the carrier phase and the phase of the carrier contained in the modulated wave signal are equal, and II in FIG.
As shown in, the carrier phase data is 0 → 8 → 16 → 24.
When the carrier wave phase lags the phase of the carrier wave included in the modulated wave signal from the state of outputting → 0 → (Fig. 1
5), in order to advance the carrier phase, the carrier phase information sequence may be changed from II to I as shown in FIG. At this time, the carrier phase information may be 24 → I at the time of advancing the phase. Therefore, only at this time, “9” is output as the addition data, and from then on, “8” is output as usual. .

On the contrary, when the carrier phase advances with respect to the phase of the carrier wave included in the modulated wave signal, the carrier wave phase is delayed so that "7" is output as the addition data at the time of changing the phase. Good. In this way, FIG.
The addition data memories 32, 34 and 36 of 6 output "8", "9" and "7", and output them to the terminal 38.
The carrier wave phase control circuit 16 changes the addition data and selects the carrier wave phase from the modulated wave signal by selecting it by the selector 30 according to the switching signal (the third bit from the MSB of the phase data) given by The phase of the carrier wave can be followed.

The third bit from the MSB of the phase data is directly used as the phase lead / lag identification information given to the carrier wave phase control circuit 16. However, for example, this phase data can be used as the input of the digital PLL circuit and the output of the digital PLL circuit can be used as the identification of the phase lead or lag. Furthermore, the phase data after inputting the phase data to a digital filter or the like and performing signal processing such as band limitation can also be used as the identification of the lead or lag of the phase.

Generally speaking, the analog / digital converter 14 oversamples the modulated wave signal by N (N is an integer of 2 or more) times, and the first and second multiplication data memories 20 and 22 are used. When modulated wave signal data is given as the lower address of
In accordance with the delay information, the carrier phase control circuit 16 outputs the first phase data K · (2 ^M / N) + C1 (M is an integer of 2 or more in the number of output bits of the tan ⁻¹ conversion memory 18, K is 0 to N). , C1 is an integer from 0 to 2 ^M −1) or the second phase data K · (2 ^M / N) + C1 ± C2 (C2 is a positive integer of 2 ^M −1 or less). It is given as a lower address of each of the first and second multiplication data memories 20 and 22. At this time, from one of the first multiplication data memories 20 and 22, the amplitude sin {2π · (A / 2 ^M of the sine wave (carrier wave) at the phase represented by the modulated wave signal data and the above-mentioned first phase data. ) + C
3} (A is the output data of the tan ⁻¹ conversion memory 18 and C3 is a real number between −2π and 2π) and outputs the multiplication result data from the second multiplication data memory 22 to the modulated wave signal data. Amplitude sin {2π · (A / 2 of the sine wave (carrier wave) in the phase represented by the above-mentioned second phase data
^M ) + C3 + 1 / 2π} is output as the multiplication result data.

A digital demodulator 10 'of another embodiment of the present invention shown in FIG. 17 is the same as the corresponding one of the embodiment of FIG.
2, an analog / digital converter 14 for converting the modulated wave signal supplied from the input terminal 12 into a digital signal, moving average type digital filters 24 and 26, and ta
An n ^-1 conversion memory 18 is included. However, the first and second multiplication memories 20 'and 22' and the carrier phase control circuit 16 'are different from those of the embodiment of FIG. 1, and the first and second multiplication memories 20' and 22 'and tan are used. ^Encoders 40 and 42 are newly added between the ^-1 conversion memory 18 and the ^-1 conversion memory 18.

In the digital demodulator 10 'of this embodiment, the first and second multiplication memories 20' and 22 'are provided.
Are exactly the same. This multiplication memory 20 '(22')
Is shown in FIG. That is, the configuration in which the multiplication result of the modulated wave signal data given to the upper address and the amplitude value data shown by the carrier wave phase data given to the lower address is stored in the addresses indicated by these addresses is the same as in the embodiment of FIG. However, in the embodiment shown in FIG.
In this embodiment, the phase data for one cycle is supplied with the phase data for one quarter cycle of the sine wave. Therefore, as shown in FIG. 18, when the lower address is 4 bits, the phase difference per counter value is π /
2 ÷ 2 ⁴ = π / 32. Further, the carrier phase control circuit 16 'independently supplies carrier phase information to the two multiplication memories 20' and 22 '.

Next, the carrier phase control circuit 1 of this embodiment
6'is shown in FIG. Carrier wave phase control circuit 16 '
Is an up / down counter that increases / decreases the counter value by the symbol clock of the data supplied from the terminal 46 according to the lead / lag identification information between the carrier phase information supplied from the terminal 44 and the phase of the carrier contained in the modulated wave signal. Down counter 48, buffer 50 that outputs a fixed value, subtracter 52 that subtracts the value of up / down counter 48 from the fixed value, selector 54 that selects the subtraction result or the count value of up / down counter 48, and multiplication memory 2
Switching signal generator 5 for applying a switching signal to encoder 40 (42) for inverting the sign of the multiplication data from 0 '(22')
Including 6.

The operation of the carrier wave phase control circuit 16 'is shown in FIG.
It will be described with reference to FIG. Here, the modulation wave signal is sampled by 4 times oversampling as in the embodiment of FIG. FIG. 21 shows the amplitude value of each sine wave (carrier wave) in each quadrant, and sequentially shows the amplitude value when one quadrant is divided into M equal parts. At this time, assuming that the amplitude values of the first quadrant are d ₀ , d ₁ , ..., d _K in order, the amplitude values of the second quadrant are exactly in the opposite order to those of the first quadrant, and d _M , d _M-1 , ..., D _K. Further, in the third quadrant, the sign is inverted with respect to the amplitude value of the first quadrant, and in the fourth quadrant, the arrangement order is opposite to that of the first quadrant, and the sign is inverted. It has been done. In this way, by using the amplitude value of one quadrant, the amplitude values of the other quadrants can be represented only by sign inversion.

In the case of 4 times oversampling, the carrier level
Since the phase will be output at π / 2 intervals, it will now be transferred.
Assuming the wave phase is the Kth in the first quadrant, the next phase is
This is the Kth of the second quadrant, and the next is the third quadrant.
It becomes the Kth phase of. That is, 4 times oversample
In the case of the carrier, the carrier phase is the same position of each quadrant in order.
It will move. Therefore, the amplitude of the first quadrant
Value d_KThen, d _K→ d_MK→ -d_K→ d_MKAnd
Will be transferred.

Next, considering the case of advancing or delaying the carrier phase, this can be done by changing the position of the amplitude value in each quadrant. That is, regarding the first quadrant, d _{K + 1} is used to advance the phase with respect to the current value d _K , and d _K−1 is used to delay the phase. At this time, 4
Double oversampling is performed on the changed phase.
Now, assuming that the carrier phase is advanced from d _K to d _{K + 1} , the 4 × oversampling operation is performed on d _{K + 1} , and d _{K + 1} → d _{M- (K + 1)} → −d _{(K + 1)} → −d
_{Let it be M- (K + 1 )} . In addition, the advance / retard operation of the carrier phase is a vertical movement in the table of FIG. 20, and a horizontal movement of the amplitude value of each quadrant in FIG. Indicates the horizontal movement of the table of FIG. 20, and the vertical movement of FIG.

A circuit that achieves such an operation is carrier wave phase control circuit 16 'shown in FIG. That is, the counter value of the up / down counter 48 is changed according to the carrier phase lead / lag information from the terminal 44 (the carrier phase lead / lag operation described above), and this counter value and this are subtracted from the fixed value. And the value are alternately selected by the selector 54 and given to the lower address of the multiplication memory 20 '(22'), and the sign of the multiplication result data from the multiplication memory 20 '(22') is given by the encoder 40 (42). Thus, switching is performed at a cycle twice as long as the switching cycle of the selector 52.

Further, in the embodiment of FIG. 1 and the embodiment of FIG.
Tan to obtain the phase information^-1Use conversion memory 18
However, the information actually needed is the carrier phase and the modulated wave.
Lead / lag between the phase of the carrier contained in the signal
It Here, in the modulated wave signal of the carrier phase in each quadrant
The relationship between lead / lag with respect to the phase of the included carrier is shown in the figure
As shown in the table of 22,_iAnd Q_i(The I component of the signal point
I_i, Q component is Q_iIf the signs of
When | Q_i｜ ＞ ｜ I_i｜ 、 In case of delay ｜ Q_i| <| I
_i| And I_iAnd Q_iIf the signs of are different,
Ki | Q_i| <| I _i｜ 、 In case of delay ｜ Q_i｜ ＞ ｜ I_i｜
Becomes Therefore, it is included in the modulated wave signal of the carrier phase.
The circuit that identifies the lead / lag with respect to the phase of the carrier wave
It can also be realized by the circuit shown in FIG. That is,
I from the moving average type digital filters 24 and 26
Amplitude information and sign excluding sign bit of signal and Q signal
Bit and. Exclusive OR of sign bits
The EXOR gate 58 calculates the
Sign bit of the subtraction result of the output and the amplitude signal by the subtractor 60
If EXOR62 finds the exclusive OR with
Lead / lag information can be obtained from the XOR 62.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a concept of a multiplication processing unit.

FIG. 3 is a waveform diagram showing an example of sine wave data.

FIG. 4 is an illustrative view showing one example of contents of a multiplication memory of the first embodiment.

FIG. 5 is a block diagram showing a digital filter.

FIG. 6 is an illustrative view showing frequency characteristics of a digital filter.

FIG. 7 is an illustrative view showing an input and an output of a digital filter.

FIG. 8 is an illustrative view showing an output of a digital filter.

FIG. 9 is an illustrative view showing one example of contents of a tan ⁻¹ memory.

FIG. 10 is an illustrative view showing signal points of a QPSK signal.

FIG. 11 is a block diagram showing a configuration of a quadrature modulator.

FIG. 12 is an illustrative view showing signal points of a modulated wave signal.

FIG. 13 is an illustrative view showing a relationship between signal points and phase data.

14 is a block diagram showing a carrier wave phase control circuit of the embodiment of FIG.

FIG. 15 is an illustrative view showing an operating principle of a carrier wave phase control circuit.

FIG. 16 is an illustrative view showing an operating principle of a carrier wave phase control circuit.

FIG. 17 is a block diagram showing another embodiment of the present invention.

FIG. 18 is an illustrative view showing one example of contents of the multiplication memory of the embodiment in FIG. 17;

FIG. 19 is a block diagram showing a carrier phase control circuit of the embodiment of FIG.

FIG. 20 is a diagram showing an example of sine wave data in each quadrant.

FIG. 21 is a diagram showing the operating principle of the carrier phase control circuit of the second embodiment.

FIG. 22 is an illustrative view showing a relationship between a carrier wave phase and a carrier wave phase included in a modulated wave signal.

FIG. 23 is a block diagram showing an example of a lead / lag decision circuit for the phase of the carrier wave included in the modulated wave signal of the carrier wave phase.

FIG. 24 is a block diagram showing a conventional technique.

[Explanation of symbols]

10, 10 '... Digital demodulator 14 ... Analog / digital converter 16, 16' ... Carrier phase control circuit 18 ... Tan- ¹ conversion memory 20, 20 ', 22, 22' ... Multiplication memory 24, 26 ... Moving average type Digital filter 28 ... Adder 30, 54 ... Selector 32, 34, 36 ... Addition data memory 38, 44 ... Lead / lag information input terminal 40, 42 ... Encoder 46 ... Symbol clock input terminal 48 ... Up-down counter 50 ... Fixed Value buffer 52, 60 ... Subtractor 56 ... Sign switching signal generator 58, 62 ... EXOR gate

Claims (7)

[Claims] 1. An analog / digital conversion means for sampling a modulated wave signal and converting it into modulated wave signal data, a first phase data output means for outputting phase data of a carrier wave signal, and a multiplication of a modulated wave signal and a carrier wave signal. Multiplication result data storage means for storing a result and outputting multiplication result data from an address designated by the modulation wave signal data and the carrier wave phase data, the data of the modulation signal included in the modulation wave signal from the multiplication result data Modulation signal data extraction means for extracting, and second phase data for outputting phase data of the modulated wave signal for controlling the phase of the carrier wave signal in the first phase data output means based on the modulation signal data. A digital demodulator having output means. 2. The digital demodulator according to claim 1, wherein the first phase data output means includes phase control means for controlling the phase of the carrier wave signal based on the phase data of the modulated wave signal. 3. When the modulated wave signal is a modulated wave signal having a 2 ^N phase phase modulation (N is a positive integer), data of the N + 1th bit from the most significant bit of the phase data of the modulated wave signal or the data thereof The phase of the carrier wave signal is controlled according to phase relationship information indicating a relationship between a phase of the carrier wave signal obtained based on data related to the phase data and a phase of a carrier wave included in the modulated wave signal. The described digital demodulator. 4. A first and a second modulation signal data extracting means for respectively outputting a first and a second modulation signal data are provided, and the first and the second modulation signal signals for the four-phase phase modulation are provided. First comparing means for comparing the absolute values of the two modulated signal data, comparing the comparison result of the first comparing means with one of the signs of the first and second modulated signal data, A second comparison unit that outputs phase relationship information indicating a relationship between the phase and the phase of the carrier wave included in the modulated wave signal, and the phase control unit controls the phase of the carrier wave signal according to the phase relationship information. The digital demodulator according to claim 2, wherein 5. The analog / digital conversion means oversamples the modulated wave signal by N (N is an integer of 2 or more) times, and uses as a first address of each of a pair of first and second multiplication result data storage means. Modulated wave signal data is provided, and the first and second multiplication result data are a pair of first data.
And second modulation signal data extraction means, respectively, and further from the first phase data output means K · (2 ^M / N) + C1 (M is the second phase data according to the phase relationship information). An integer of 2 or more in the number of bits of the output means,
K is an integer from 0 to N, C1 is an integer from 0 to 2 ^M −1) or K · (2 ^M / N) + C1 ± C2 (C2 is 2)
^M- 1 or less positive integer) phase data is given as a second address of each of the first and second multiplication result data storage means, and one of the first and second multiplication data storage means is provided,
The modulated wave signal data and sin {2π · (A / 2 ^M ) +
C3} (A is output data of the second phase data output means, C3 is a real number between −2π and 2π) and outputs the result data, and the other of the first and second multiplication data storage means From the modulated wave signal data and sin {2π ·
5. The digital demodulator according to claim 1, which outputs multiplication result data with (A / 2 ^M ) + C3 + 1 / 2π}. 6. An analog / digital conversion means for sampling a modulated wave signal and converting it into modulated wave signal data, a first phase data output means for outputting phase data of a carrier wave signal, and a multiplication of the modulated wave signal and the carrier wave signal. Multiplication result data storage means for storing a result and outputting multiplication result data from an address designated by the modulated wave signal data and the carrier phase data, a sign changing means for changing the sign of the multiplication result data, and a sign changing means. Modulation signal data extracting means for extracting data of a modulation signal included in the modulation wave signal based on multiplication data having a changed sign output from, and outputting phase data of the modulation wave signal from the modulation signal data A digital demodulator comprising two phase data output means. 7. A first and second multiplication result data storage means, wherein the first and second multiplication result data storage means have the same configuration, and are included in the modulated wave signal of the phase of the carrier wave signal. A phase-up information counter indicating a relationship with the phase of the carrier wave to be output, the first phase data output means is an up-down counter whose count operation is switched according to the phase-relation multiplication, and a predetermined value from the up-down counter. Subtraction means for subtracting the count value of the counter, and switching means for alternately switching the count value of the up / down counter and the subtraction result of the subtraction means and outputting to the address of the first and second multiplication result data storage means. 7. A digital signal according to claim 6, further comprising: and the sign changing means changes only the sign of the first and second multiplication result data. Modulator.