JP2518860B2 - Phase synchronization circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit used in a demodulator of a digital phase modulated wave, etc., and a single circuit can easily cope with various input signal frequencies and is small in size. In order to enable high-speed operation, the phase comparator that receives the input signal, the loop filter that receives the phase detection signal from the phase comparator, and the oscillation output that changes the oscillation frequency according to the output signal of the loop filter are generated. A phase-locked loop circuit including a control oscillator for providing a phase comparator with a phase detection signal according to the advance or delay of the phase between the input signal and the oscillation output of the control oscillator. The loop filter is configured to output as, and the loop filter includes an up-down count unit that up-counts or down-counts a clock having a constant period according to the phase detection signal, and Configured comprises computing unit for counting the output of the up-down counter unit is changed with a constant width in accordance with a phase detection signal as an output signal of the loop filter.

[Industrial applications]

The present invention relates to a phase locked loop (PLL: phase locked loop). The phase locked loop circuit of the present invention can be used as a reference carrier wave recovery circuit in a demodulator for demodulating a digital phase modulated wave, for example.

The data transmission method using digital phase modulation is widely used in fields such as wireless communication and satellite communication. Especially in satellite communication, since the satellite repeater has input / output nonlinearity, BPSK (two-phase phase modulation) or QP that is strong against this nonlinear distortion is used.
Modulation methods such as SK (4-phase phase modulation) have been put to practical use. The capacity that can be transmitted by satellite relay is determined by the scale of the earth station, for example, the antenna diameter, the output power of the high output amplifier, or the capacity of the satellite repeater. Generally, a small earth station has a small transmission capacity, but a large station can increase the transmission capacity. In the case of digital phase modulation, this change in transmission capacity results in a change in modulation rate. Therefore, in order to support various transmission capacities, various speed modulator / demodulators are required. Generally, when implementing a modulator / demodulator by analog technology, it is difficult to greatly change the modulation speed with one modulator / demodulator. Therefore, a modulator / demodulator designed individually for each modulation speed is used.

On the other hand, if digital technology is used, there is a possibility that one device can handle various modulation rates. The phase locked loop circuit of the present invention can be used as a demodulation reference carrier wave reproduction circuit for realizing such a variable speed modulator / demodulator.

[Conventional technology]

A conventional example of a demodulation circuit for a digital phase modulated wave using a phase locked loop circuit is shown in FIG. In the figure, 10 is a quadrature synchronous detector to which a QPSK wave is input, and 11 and 12 are quadrature synchronous detectors.
An A / D converter for A / D converting the in-phase signal I and the quadrature signal Q of 10, and 50 is a product for performing the product operation of the amplitude bit of the A / D converter 11 and the polarity bit A of the A / D converter 12. Arithmetic circuit, 51 is A / D converter 12
2 is a product operation circuit for performing a product operation of the amplitude bit of the above and the polarity bit B of the A / D converter 11, and 52 is an adder circuit for adding the outputs of the product operation circuits 50 and 51. A / D converters 11 and 12 and adder circuit 52
Constitutes a non-linear phase comparator 5. Polarity bit A, B
Are used as demodulated data outputs. Reference numeral 6 is a loop filter, which is addition circuits 60 and 61, and a multiplication circuit 6 which multiplies a constant α.
2. It includes a delay circuit 63 for giving a unit delay. Three
Is a D / A converter, and 4 is a voltage controlled oscillator.

The operation of this conventional device is described below. In this device, a quadrature phase demodulation signal (QPSK) is quadrature demodulated by a quadrature synchronous detector 10 with reference to an output signal of a voltage controlled oscillator. Quadrature demodulation signals I and Q are A / D converted by A / D converters 11 and 12, respectively.
It is converted, and in the non-linear phase comparator 5, it is 9 in the 360 ° phase range.
It is calculated so as to have four stable points every 0 °. This calculation is realized by the product calculation circuits 50 and 51 and the addition circuit 52.

The loop filter 6 filters the phase detection signal,
The constant α of the multiplication circuit 62 is related to the time constant. The output of the loop filter 6 is D / A converted by the D / A converter 3, and the entire loop is configured so as to control the voltage controlled oscillator 4.
The demodulated output data becomes output polarity bits A and B of the A / D converters 11 and 12.

[Problems to be solved by the invention]

In the conventional demodulator, when the modulation speed of the input QPSK wave changes, the constant of the loop filter that constitutes the phase locked loop must be changed, and this change cannot be easily made. Therefore, in order to cope with various modulation rates, it is necessary to individually prepare a device for each modulation rate. In addition, although a product operation with a constant is required in the loop filter, the product operation circuit has a larger hardware scale than the summing circuit and requires a long operation time, which is a major obstacle to speeding up.

Therefore, an object of the present invention is to provide a phase locked loop circuit which can easily cope with various input signal frequencies with a single circuit and which is small in size and can operate at high speed.

[Means for solving problems]

FIG. 1 is a principle diagram of a phase locked loop according to the present invention. The phase locked loop circuit according to the present invention, the phase comparator 101,
A loop filter 102 and a control oscillator 103 are provided, and the phase comparator 101 outputs a binary signal as a phase detection signal according to the advance or delay of the phase between the input signal and the oscillation output of the control oscillator 103. The loop filter 102 up-down count section 1020 for up-counting or down-counting a clock of a constant cycle according to the phase detection signal, and the count output of the up-down count section 1020 according to the phase detection signal. It is configured to include a calculation unit 1021 that changes the output value of the loop filter by a constant value width.

[Work]

The up / down count unit 1020 of the loop filter 102 functions as an integrator for the input signal, and the calculation unit 1021
Functions to give a constant value transfer function to the loop filter as the frequency of the input signal increases. As a result, the loop filter 102 functions as a lag lead filter having a transfer function characteristic as shown in FIG. Second
In the figure, the vertical axis represents the transfer function of the loop filter, and the horizontal axis represents the input signal frequency. The transfer function gradually decreases due to the function of the up / down count unit 1020 as the frequency of the input signal increases, and when the frequency becomes higher than a certain level, the transfer function having a constant value with respect to the loop filter is next provided by the function of the calculation unit 1021. To give. Such a transfer function gives the phase lag lead characteristic.

In the loop filter having such a configuration, it is possible to easily cope with various frequencies of the input signal by changing the frequency of the clock source of the up / down counting unit 1020 and the magnitude of the constant value given by the arithmetic unit 1021. It is possible with.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a phase locked loop circuit according to an embodiment of the present invention.
It is a block diagram showing an example applied to a reference carrier wave recovery circuit in a phase-modulation wave (QPSK wave) demodulation device. In the figure,
1 is a phase comparator, 2 is a loop filter, 3 is a D / A converter, and 4 is a voltage controlled oscillator. The received QPSK wave is input to the quadrature synchronization detector 10 and demodulated into the in-phase signal I and the quadrature signal Q. The in-phase signal I and the quadrature signal Q are A / D converters 11 and 1
After being input to 2 and A / D converted to natural binary numbers, they are further input to bit converters 13 and 14 and folded 2
Converted to base.

FIG. 4 shows a detailed configuration of the bit converters 13 and 14 when the number of A / D conversion bits is 3 bits. As shown, this circuit can be constructed using two exclusive NOR circuits. It goes without saying that the A / D conversion bit number can be expanded to any bit number. The conversion from natural binary numbers to folded binary numbers is performed as shown in FIG. The MSB (most significant digit bit) of the converted folded binary number after conversion is called a polarity bit, and the remaining lower digit bits are called amplitude bits.

The polarity bits A and B of the bit converters 13 and 14 are used as demodulated data outputs and are input to the exclusive OR circuit 16. The amplitude bits of the bit converters 13 and 14 are input to the amplitude comparator 15, respectively. Exclusive OR circuit 16
And the output signal of the amplitude comparator 15 are further input to the exclusive logical division circuit 17.

As will be described later, the phase detection signal of the phase comparison unit 1 has a phase lead / advanced phase between the input signal and the oscillation output of the voltage controlled oscillator 4.
It becomes a binary signal corresponding to the delay. This phase detection signal is input to the up / down counter 21 and the addition / subtraction circuit 22. A clock having a constant cycle is input from the clock source 20 to the up / down counter 21, and the clock is up-counted or down-counted according to the binary state of the phase detection signal, that is, the lead / lag state. The count output signal is input to the adder / subtractor circuit 22. A constant constant β is input to the adder / subtractor circuit 22 from the loop constant setting circuit 23, and the constant β of the loop constant setting circuit 23 is added from the count output signal of the up / down counter 21 according to the binary state of the phase detection signal. Or subtract.

The output signal of the adder / subtractor circuit 22 is input to the D / A converter 3 as the output signal of the loop filter 2 and D / A converted, and the oscillation frequency of the voltage controlled oscillator 4 is controlled by the D / A converted output signal. The oscillation output of the voltage controlled oscillator 4 is supplied to the quadrature synchronization detector 10 as a reference carrier.

The operation of the embodiment device will be described below. The quadrature synchronization detector 10 uses the oscillation output signal of the voltage controlled oscillator 4 as a reference carrier to detect the received QPSK wave in quadrature synchronization. The baseband signal of the detection output is filtered by a low-pass filter (not shown) to obtain an in-phase signal I and a quadrature signal Q, which are A / D converter 1
1 and 12 perform analog / digital conversion into digital signals of natural binary numbers, and bit converters 13 and 14 respectively convert the signals into folded binary numbers.

The exclusive OR circuit 16 performs an exclusive OR between the polarity bits of the in-phase signal I and the quadrature signal Q, and the amplitude comparator 15 performs the advance and decrease of the advance width between the advance bits.
Comparison result of amplitude comparator 15, output signal and exclusive OR circuit
The output signal of 16 is exclusive ORed again by the exclusive OR circuit 17, and the output signal of the exclusive OR circuit 17 becomes the phase detection signal.

The state of this phase detection signal is shown in FIG. FIG. 6 shows the phase comparison characteristics, where the horizontal axis is the phase difference Δθ between the received QPSK wave and the reference carrier from the voltage controlled oscillator 4, and the vertical axis (a) is the quadrature detection output voltage of the quadrature synchronization detector path 10. The vertical axis (b) represents the phase detection signal of the phase comparison unit 1. As shown in the figure, as the phase detection signal, logical outputs are obtained with four phase leads / lags every 90 ° in the range of the input phase difference Δθ of 360 °. In the synchronization stable state of this loop, control is performed so that the lead / lag logic determinations are equal at the time rate, and the position marked with a circle in FIG. 6 is the stable point. In this way, in the phase comparison unit 1 of the apparatus of the present embodiment, the lead / lag of the phase is represented by a 1-bit binary signal, for example, "1" for lead and "0" for delay.

The comparison detection signal is input to the loop filter 2. In the loop filter 2, the up / down count control of the up / down counter 21 is performed according to the lead / lag state of the phase detection signal from the phase comparator 1. For example, it is controlled to count up in the advanced state and to count down in the delayed state. As described above, the up / down counter 21 counts the clock pulse sent from the clock source 20 by incrementing the count value by 1 each time the pulse is input in the up control state and decrementing the count value by 1 in the down control state. Then, the obtained count value is output as a count output signal.

The addition / subtraction circuit 22 performs addition / subtraction / subtraction of the count output signal from the up / down counter 21 and the constant β from the loop constant setting circuit 23 according to the lead / lag state of the phase detection signal. For example, when the phase is advanced, the count output signal has a constant β
Is added, and when there is a delay phase, a constant β is obtained from the count output signal.
Works like subtracting. As a result, the count output signal of the up / down counter 21 changes within a constant value width of ± β according to the lead / lag state of the phase detection signal,
As a result, the transfer function of the loop filter always has a constant value even when the input signal frequency increases to some extent or more, as shown in FIG.

In such a loop filter, the up / down counter 21 operates as an integrator, and together with the functions of the adder / subtractor circuit 22 and the loop constant setting circuit 23 that give a constant value fluctuation to the count value of the up / down counter 21, the loop filter 2 The transfer function is made to have a lag lead characteristic as shown in FIG. In this case, the constant value for adding and subtracting the constant determines the pull-in frequency range.

The output signal of the loop filter 2 is applied to the control voltage terminal of the voltage controlled oscillator 4 via the D / A converter 3 to control the oscillation frequency of the voltage controlled oscillator 4, and the oscillation output from the voltage controlled oscillator 4 is the reference carrier wave. Is supplied to the quadrature synchronization detector 10.

In such an embodiment apparatus, when the modulation speed of the input QPSK wave changes, it can be easily dealt with by changing the oscillation frequency of the clock source 20 of the loop filter 2 and the constant β of the loop constant setting circuit 23.

Further, since the phase comparison unit 1 and the loop filter 2 do not have to perform the product calculation, the circuit can be downsized and the high speed operation can be performed.

Various modifications are possible in carrying out the present embodiment. FIG. 7 is a block diagram showing such a modification, showing another embodiment of the loop filter. In this modification, the count output signal of the up / down counter 21 is input to the adder circuit 25 and the selector 26, respectively. Adder circuit
25 has a constant constant γ input from the constant value circuit 24,
This constant γ is added to the count output signal of the up / down counter 21, and the added output signal is sent to the selector 26.
The selector 26 selects either the count output signal of the up / down counter 21 or the addition output signal of the adder circuit 25 according to the lead / lag state of the phase detection signal and sends it as the output signal of the loop filter. With such a configuration, the count value of the up / down counter 21 can be changed with a constant value width according to the lead / lag state of the phase detection signal, and the characteristic as shown in FIG. 2 can be obtained.

As another modification, in the above-described embodiment, an analog type voltage control oscillator is used, but of course a digital type voltage control oscillator may be used, and in this case, the D / A converter 3 becomes unnecessary. . Further, regarding the configuration of the phase comparison unit, the bit converters 13 and 14 are not necessary when the A / D converters 11 and 12 are originally configured to output a folded binary number. The configuration of the circuit for obtaining the exclusive OR of the polarity bits A and B and the output signal of the amplitude comparator 15 is not limited to that shown in FIG. Of course, for example, the exclusive OR of the polarity bit A and the output signal of the amplitude comparator 15 may be obtained, and then the exclusive OR of the result and the remaining polarity bit B may be obtained.

〔The invention's effect〕

According to the present invention, it is possible to easily cope with various speeds (frequency) of the input signal by changing the clock frequency and the constant in the loop filter. Further, since it is possible to eliminate a portion for performing the product operation from the inside of the circuit, it is possible to reduce the size of the hardware and increase the operation speed. Furthermore, the main constituent elements of the circuit are the counter and the gate logic circuit, which is advantageous for LSI implementation.

[Brief description of drawings]

1 is a principle diagram of a phase locked loop circuit according to the present invention, FIG. 2 is a characteristic diagram showing a transfer function of a loop filter of the phase locked loop circuit of the present invention, and FIG. 3 is a phase locked loop as an embodiment of the present invention. FIG. 4 is a block diagram showing an example in which the circuit is used for a QPSK wave demodulation device, FIG. 4 is a block diagram showing a detailed configuration of a bit converter of the embodiment device, and FIG. 5 is a diagram showing a conversion state into a folded binary number. FIG. 6 is a diagram showing a phase comparison characteristic, FIG. 7 is a block diagram showing a modified example of the present invention, and FIG. 8 is a block diagram showing a QPSK wave demodulation device using a conventional phase synchronization circuit. 1 ... Phase comparator, 2 ... Loop filter, 3 ... D / A converter, 4 ... Voltage controlled oscillator, 10 ... Quadrature synchronization detector, 11, 12 ... A / D converter, 13, 14 …… bit converter, 15 …… amplitude comparator, 16,17 …… exclusive OR circuit, 20 …… clock source, 21 …… up / down counter, 22 …… addition / subtraction circuit, 23 …… loop constant setting Circuit, 24 …… Constant value circuit, 25 …… Adding circuit, 26 …… Selector.

Claims (2)

(57) [Claims] 1. A phase comparator (10) to which an input signal is input.
1), a loop filter (102) to which a phase detection signal of the phase comparator (101) is input, and an oscillation output whose oscillation frequency changes according to an output signal of the loop filter (102) to generate the phase comparator. A phase locked loop circuit comprising a controlled oscillator (103) provided to (101), wherein said phase comparator (101) comprises an input signal and said controlled oscillator (1
03) is configured to output a signal indicating a phase lead or lag between the oscillation output and the oscillation output as a phase detection signal, and the loop filter (102) increases a clock of a constant cycle according to the phase detection signal. An up / down counting unit (21) for counting or down counting, a loop constant setting circuit (23) for holding and outputting a set loop constant (β), and a count output of the up / down counting unit (21) , The loop constant (β) output from the loop constant setting circuit (23) is added or subtracted in accordance with the phase detection signal, and the result is added to the loop filter (10).
A phase locked loop circuit comprising: an adder / subtractor circuit (22) which outputs the output signal of 2) to the controlled oscillator (103). 2. The phase synchronization circuit according to claim 1, which is used as a reference carrier recovery circuit in a demodulator for demodulating a digital phase modulated wave, wherein the phase comparator (101) is a digital phase converter. A quadrature synchronous detector for quadrature synchronously detecting a modulated wave and outputting an in-phase signal and a quadrature signal, and converting the in-phase signal and the quadrature signal of the quadrature synchronous detector into a folded binary number composed of polarity bits and amplitude bits, respectively. A converter, an amplitude comparator for comparing the amplitude bit of the in-phase signal and the amplitude bit of the quadrature signal converted by the converter, and a polarity bit of the in-phase signal and a polarity bit of the quadrature signal converted by the converter , And 3 of the comparison output signal of the amplitude comparator
A phase-locked circuit comprising an arithmetic circuit that obtains an exclusive OR between two parties.