JP2756965B2 - Demodulator for high transmission rate modulated signal - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a numerical processing type demodulator applied to a high-speed data transmission rate modulated signal.

(Prior Art) Conventionally, in a general demodulator for a digital modulation signal, numerical processing for carrier wave reproduction and clock reproduction has been performed in units of data time slots (1 / baud rate).

(Problems to be Solved by the Present Invention) Therefore, when the data transmission rate is high, the required operation time for the time slot becomes relatively long, and the processing cannot be performed in time, and the demodulation loop does not operate normally. there were.

(Means for Solving the Problems) In order to solve these drawbacks, in the present invention, the time period of the numerical processing of carrier wave recovery and clock recovery based on received data in units of time slots of transmission data is set to the time slot By setting it to an integer multiple of 2 or more, it is possible to perform a demodulation operation on a higher-speed data transmission rate modulated signal. Hereinafter, embodiments will be described in detail with reference to the drawings.

(Embodiment) FIG. 1 shows a configuration diagram when the present invention is applied to a QPSK synchronous quadrature demodulator. The principle and operation will be described. Operations such as the correction of the clock generation timing of the demodulator and the correction of the phase of the carrier wave are well known, and therefore, only the portions related to the present invention will be described here.

The QPSK modulated wave input from the terminal 1 is compared in phase with the oscillating wave of the VCO 2 whose phase is controlled by the phase detectors 4 and 5, and is decomposed into an in-phase component and a quadrature component, respectively.
The signal waveforms appear at 0 and 11 as shown in FIG. 2 (I indicates an in-phase component and Q indicates a quadrature component). The signals are both (e) by the samplers 12 and 13,
Sampled at the timing of (o), Ie and Qe of the positive and negative peak values of the signal are output from the terminals 14 and 15 as demodulated data.

The clock regenerator 8 can be realized in various ways.
Here, the constituent circuit of FIG. 3 is cited as an example. When the data code at the timing (e) that is continuous on the I-sequence or the Q-sequence changes, the clock error function et of the deviation from the zero-crossing point from the value of the (o) timing data at the intermediate point. Are detected and added, and each time the value exceeds the threshold value 810, the frequency division ratio τ of the frequency divider 814 is updated to correct the timing of generating the sampling clock. If the data transmission rate is high and the time required for this series of processing exceeds the data time slot 2T in FIG. 2, the frequency division ratio N of the frequency divider 800 of the sampling clock is set to an appropriate value of 2 or more in advance. The period of the operation from the sampler 801 to the comparator 809 in the figure for clock recovery is set to an integer value, and the cycle of the operation is set to N times the data time slot (2T), so that the processing for each time is 2T · N. To end within. The sampling data used here is 2T
It is not necessary that all data is stored in a memory or the like within the time N, and one or several sets of data at appropriate time positions may be used.

The carrier wave regenerator 9 can be realized in various ways, but the Costas loop in FIG. 4 is cited as an example.
This circuit detects and adds the phase error function ef corresponding to the phase shift of the carrier from the sample data values of Ie and Qe, and adds the set value of the reproduction frequency every time the value exceeds the threshold value 911. And the value (F ±
f) and the control signal C for correcting the phase from the phase error function ef
This is to calculate φ. If the data transmission rate is high and the time required for this series of processing exceeds the data time slot 2T in FIG. 2, the frequency division ratio M of the frequency divider 900 of the sampling clock is set to an appropriate value of 2 or more in advance. Samplers 901 and 9 in the figure for carrier recovery are set to integer values.
The cycle of the operation from 02 to the adder 916 is set to M times the data time slot (2T) so that each processing is completed within the time of 2T · M. The sampling data used here does not need to be all data stored in a memory or the like within the time of 2T · M, and may be one or several sets of data at appropriate time positions.

Generally, the longer the processing time required for clock recovery or carrier wave recovery or the higher the data transmission rate, the larger the value of the division ratio N or M can be dealt with. Is likely to be large, so keep it within the compatible range.

In the above description, one type of QPSK demodulator is taken as an example, but the present invention is also applicable to various demodulators such as BPSK, offset QPSK, and GMSK.

(Effect of the Invention) As described above, by setting the cycle of the numerical processing for carrier recovery and clock recovery based on a part of the received signal to an integral multiple of the data time slot,
A demodulation operation can be performed on a modulated signal having a relatively high data transmission rate. Further, the present invention can be easily applied to a demodulator using a digital signal processing technique which is advantageous for miniaturization and stable operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronous quadrature demodulator for a QPSK signal showing one embodiment of the present invention, and I and Q in FIG.
FIG. 3 is a time waveform diagram observed at the monitor terminals 10 and 11, FIG. 3 is a block diagram showing an embodiment of the clock regenerator 8 in FIG. 1, and FIG. 4 is a transport diagram in FIG. FIG. 2 is a configuration diagram illustrating an embodiment of a regenerator 9. 6, 7 ... low-pass filter for removing intersymbol interference, 80
0: Divider for setting the clock regeneration processing cycle, 900: Divider for setting the carrier regeneration processing cycle, 803, 805, 808, 90
9, 913 …… Delay device, 809, 910… Comparator with threshold value,
816... Input terminals for the calculated values from the Q-sequence which are the same as those on the I-sequences 801 to 808 in FIG.

Claims (1)

(57) [Claims] 1. A demodulator that performs numerical processing in units of time slots (1 / baud rate) of transmission data and realizes clock recovery and carrier recovery of a received signal, and sets a cycle of one or both of the numerical processings to a time slot. A demodulator for a high-speed transmission rate modulated signal, comprising means for setting an integer multiple of 2 or more.