JPS6331985B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides an A/D converter for converting a received analog signal into a data demodulator or the like using digital signal processing.
The present invention relates to a sampling phase synchronization circuit for synchronizing the sampling phase of a received analog signal when converting it into a digital signal with a converter.

Technical background of the invention and its problems In recent years, as seen in data transmission modems using voice band telephone lines, waveform transmission is performed to satisfy the Nyquist roll-off characteristic, and this is converted to a baud rate (symbol) on the receiving side. There are many cases where digital signal processing operations such as automation are performed based on transmission speed). When roll-off spectra overlap in this way, when converting the received analog signal into a digital signal using the A/D conversion circuit, if sampling is not performed at the correct phase in synchronization with the received analog signal, subsequent digital signal processing calculations will be affected. It has been pointed out that this is not carried out stably. For this reason, the sampling phase in the A/D conversion circuit is synchronized with the received analog signal.
What is called a sampling phase synchronization circuit is required.

FIG. 1 shows the configuration of a conventional sampling phase synchronization circuit, and FIG. 2 shows its timing chart. Received analog signal 2 given to input terminal 1
is sampled by the sampling pulse 4 in the A/D conversion circuit 3, converted to a digital signal 5, and inputted to the sampling phase error detection circuit 6. In the sampling phase error detection circuit 6,
First, it passes through a narrow band digital filter 7 whose passband is set to 1/2 of the baud rate frequency _B of the received analog signal 2, and then is multiplied by a multiplier 8. For example _, if the digital signal 5 is a sample value 21 of a waveform with a baud rate frequency _B = 1/T as _shown in FIG. ), and the output of the multiplier 8 is S ₁ ² =A ² cos ² π _B t =A ² (1+coszπ _B t)/2 (2). The output of this multiplier 8 passes through a narrowband digital filter 9 whose passband is set to the baud rate frequency _B , as shown in FIG. 2b.

S ₂ =A′cos2π _B t (3) The sample value 22 of the cosine wave is given to the phase comparison circuit 10. The phase comparator circuit 10 is further provided with the sample value ₂₃ of _{the reference signal S 3 shown} in FIG. ₄ = BsinΔθ ……(5) A phase error signal S ₄ is generated.This error signal S ₄
becomes the control input of the oscillation circuit 12 via the low-pass filter 11. The phase comparison circuit 10, the low-pass filter 11, and the oscillation circuit 13 constitute a digital PLL circuit 13, which operates so that the reference signal _S3 is phase-synchronized with the output _S3 of the digital filter 9. As a result, the phase of the sampling pulse 4 output from the variable frequency divider circuit in the oscillation circuit 12 is synchronized with the baud rate of the received analog signal 2.

By the way, the digital PLL circuit 13 in FIG.
Since the phase at which S ₃ is synchronized is 90° shifted from S ₂ , the sample value 23 in Figure 2c is t =
Stabilizes at position nT+T/4 (n: integer). Therefore, the sample values 21 and 22 in Fig. 2 a and b are also t = nT.
Since it is stabilized at ±T/4, there is a problem in that the sampling phase, that is, the phase of sampling pulse 4, deviates from the optimum sampling point t=nT by ±T/4. In other words, the phase error detection characteristic of the sampling phase error detection circuit 6 is as shown by the curve 30 in FIG. 3, where the deviation of the sampling phase from the optimum phase is Δ, which is π/2 in phase angle conversion. This leaves a phase error Δ of .

Conventionally, the sampling phase T/
In order to remove a deviation of 4 (π/2), a method has been used in which sampling is performed at a frequency 4N times the baud rate frequency (N is an integer), as shown at 21 and 21' in FIG. 2a. However, increasing the sampling rate in this way increases the number of calculations,
This is not preferable because it involves an increase in the hardware circuit scale.

OBJECT OF THE INVENTION An object of the present invention is to provide a sampling phase synchronization circuit that can control the sampling phase to an optimum phase without increasing the sampling rate more than necessary.

Summary of the Invention The present invention provides a sampling phase error detection circuit that essentially converts an input digital signal into a quadrature signal and performs nonlinear arithmetic processing on these two orthogonal signals, thereby converting the point at which the sampling phase error is zero into the sampling phase. It is characterized in that it is configured to generate a phase error signal that makes it a stable phase point.

Effects of the Invention According to the present invention, even when the sampling rate is, for example, twice the baud rate frequency, the sampling phase is stabilized at a point where the phase error is zero, making it possible to lower the sampling rate than before. Therefore, the number of arithmetic operations and hardware can be significantly reduced.

Embodiment of the Invention FIG. 4 shows a schematic configuration of a sampling phase synchronization circuit according to an embodiment of the present invention. analog signal 4
2 is given. This received analog signal 42 is sampled by a sampling pulse 44 in an A/D conversion circuit 43, converted into a baseband digital signal 45, and input to a sampling phase error detection circuit 46. This detection circuit 4
6 is an A/D conversion circuit 43 from the digital signal 45
Detects the sampling phase error at and outputs a phase error signal. This phase error signal is given to a variable frequency divider circuit 48 via a noise suppression circuit 47. The variable frequency divider circuit 48 divides the frequency of the reference clock signal 49 and outputs the sampling pulse 4 to the A/D converter circuit 43.
Generate 4. Then, the variable frequency divider circuit 4 uses the phase error signal given via the noise suppression circuit 47
By controlling the frequency division ratio of
Controlled to synchronize with.

The sampling phase error detection circuit 46 includes a digital filter 50 and an arithmetic circuit 60. The digital filter 50 is, for example, a 90° phase division narrowband filter, and a specific example of its configuration is shown in FIG.

In Figure 5, 51, 55, 56, 57, 5
8 is a coefficient multiplier, 52 is a synthesis circuit composed of adders (subtractors), 53 and 54 are word memories for one sample delay, and 59 is a subtracter. 51~
56 constitutes a second-order cyclic digital filter, and its transmission function F(z) is as follows with b, c, and d as coefficient parameters: F(z) = b/1 + cz ^-1 + dz ^-2 ...(6) The passband can be set arbitrarily by designing the coefficient parameters. For example, if this second-order cyclic digital filter is operated at twice the baud rate of the received analog signal 42, by setting c=0 and d≦1, _B /2
A narrowband filter with a passband of ( _B : baud rate frequency) is realized.

When the two outputs x ₁ and x ₂ in Fig. 5 are obtained using equation (6), x ₁ = z ^-1・F ...(7) Also, x ₂ is the coefficient value of the coefficient multipliers 57 and 58. 1/2
Then, x ₂ = 1/2(z ^-2 -1)・F(z) = 1/2z ^-1・F(z)・(z ^-1 −z) =X ₁・z ^-1 −z/ 2...(8) becomes. Substituting z = e ^j 〓 (where j = √-1, θ is the phase angle normalized by the sampling frequency) into equation (8) and looking at the difference in the frequency characteristics of x ¹ and x ² , we get x ₂ /x ₁ = −jsinθ...(9). Here, the passband of the second-order cyclic digital filter is _B /2, that is, θ=±π/2.
It can be seen that for the output of such a filter, the characteristic of equation (9) is a good approximation to the 90° phase shift filter characteristic (Hilbert transform characteristic). Therefore, the configuration shown in Figure 5 realizes a 90° phase split narrowband filter, and the output x ₂ is
It has an orthogonal relationship with x ₁ . In addition, the coefficient value 1/2
Since the coefficient multipliers 57 and 58 can be realized by simple bit shifting, no special hardware is required for this purpose.

In general, a 90° phase splitting filter is applied in parallel to the input, for example, with a transfer function of _N 〓 ^j=1 (a _ij −z ^-1 )/(1
-a _ij z ^-1 ) (where i=1, 2, J=1, 2,...
...N, z ^-1 is a z-transform operator for a one-sample delay) All-pass filters for phase correction are installed, and parameters a _ij are set so that the outputs of these filters have a phase difference of 90° from each other. It is known that it is possible to design Therefore, the 90° phase splitting narrowband filter used as the digital filter 50 in FIG. 4 can also be realized by, for example, providing the above-mentioned all-pass filter in parallel with a narrowband filter whose passband is _B /2. can.

On the other hand, the arithmetic circuit 60 in FIG. 4 performs nonlinear arithmetic processing on two orthogonal signals x ¹ and x ² provided from the digital filter 50, which is a 90° phase splitting narrow band filter, to stabilize the point where the sampling phase error is zero. It generates a phase error signal that can be used as a phase point, and specifically, it uses a multiplier 61, a polarity switching circuit 62, or an exclusive OR (EX) as shown in FIGS. -OR) circuit 63
This is realized by etc.

Next, the operation of this embodiment will be explained using FIGS. 7 and 8. FIG. 7a shows an example of the waveform of the digital signal 45, which consists of two sample values 71 and 72 per baud rate T=1/ _B . This digital signal 45 is processed by the digital filter 50, which is a 90° phase splitting narrow band filter, into an in-phase signal of x ₁ =A cosπ _B t(A=±1)...(10), and x ₂ =A cosπ _B t(A ±1) ...(11) It is converted into two orthogonal signals consisting of the orthogonal phase signals. These two orthogonal signals x ₁ and x ₂ are input to the arithmetic circuit 60. Assuming that the arithmetic circuit 60 is a multiplier 61 as shown in FIG. 6a, its output, viewed as a temporally continuous waveform, is x ₃ = x ₁ x ₂ = A ² /2 sin2π _B t...( 12), and looking at the sample values corresponding to 71 and 72 in FIG. 7a, they become 73 and 74 in FIG. 7b. Here, if the multiplier 61 constituting the arithmetic circuit 60 performs the arithmetic operation by thinning out once per baud rate T, the sample value of x ₃ will be one of the values 73 and 74 in FIG. 7b, i.e. As shown in the phase error detection characteristic 81 in FIG. 8a, a constant value proportional to sinΔ is taken for the sampling phase error Δ.

Therefore, the phase error signal x ₃ obtained at the output of the arithmetic circuit 60 is transmitted once per baud rate to a variable frequency dividing circuit via a noise suppression circuit 47 constituted by, for example, an ordinary low-pass digital filter. 4
8 to control the phase of the sampling pulse 44, according to the phase error detection characteristics shown in FIG.
The sampling phase becomes stable with its phase error Δ being zero, and becomes synchronized with the received analog signal 42. For example, as a phase error signal x ₃ , Fig. 7b,
Taking the sample value of 73 in Figure 8a, the loop operates to advance the sampling phase and the 8th
73 in Figure a becomes stable when Δ=0. In this case, 71 in FIG. 7a is the sample value at the optimum sampling phase points T, 2T, . . . . on the other hand,
When adopting the sample value 74 in Figures 7b and 8a as the phase error signal _x3 , the loop operates to delay the sampling phase, and 74 becomes Δ=
Since it becomes stable near 0, 72 in FIG. 7a becomes the sample value at the optimum sampling phase point.
In this manner, the arithmetic circuit 60 may use either of the sample values 71 and 72 output from the digital filter 50 twice per baud rate to obtain the phase error signal _x3 .

In the above explanation, the multiplier 61 shown in FIG. 6a is used as the arithmetic circuit 60, but as described above,
polarity switching circuit 62 or EX-OR circuit 6 of c
3 may be used. For example, when using the polarity switching circuit 62, the orthogonal _phase signal
The phase error signal may be obtained by inverting the polarity of x ₂ , and the phase error detection characteristic in that case will be as shown at 82 in FIG. 8b. In addition, EX-OR circuit 6
If 3 is used, the result will be as shown in 83 in FIG. 8c. In both cases of FIGS. 8b and 8c, the sampling phase can be stabilized at the optimum phase point of Δ=0, as in FIG. 8a.

Note that the noise suppression circuit 47 in FIG. 4 uses a baud rate frequency _B instead of a low-pass digital filter.
It is also possible to use a narrowband fast-pass digital filter with a passband of . In that case, input the sample values 73 and 74 in FIG. 7b as the phase error signal x ₃ to the filter at twice the baud rate to suppress noise components other than the baud rate frequency,
It is clear that the variable frequency divider circuit 48 can be controlled once per baud rate as described above. The noise suppression circuit 47 is configured with an up-down counter in which the positive and negative of the input phase error signal are made to correspond to the up signal and down signal, respectively, instead of being configured with a normal low-pass or high-pass digital filter. It can also be realized by

Furthermore, in the above description, the sample value of the phase error signal that is finally given from the arithmetic circuit 60 to the variable frequency divider circuit 48 via the noise suppression circuit 47 is once per baud rate, but it is also possible to sample it twice. In this case, the outputs of the arithmetic circuit 60 or the noise suppression circuit 47 are both sample values 73 and 74 in FIG. Therefore, the polarity of the output of the arithmetic circuit 60 or the noise suppression circuit 47 may be alternately inverted. That is, for example, the arithmetic circuit 60 may be configured to include a polarity inversion circuit, and its output may be input to the noise suppression circuit 47 consisting of a low-pass digital filter at twice the baud rate, or the noise suppression circuit 47 may be configured to include a polarity inversion circuit. It may be constructed from a band pass digital filter and a polarity inversion circuit. In this case, although the number of arithmetic processing and hardware increases slightly, the number of times the sampling phase is controlled increases, so the initial pull-in speed of phase synchronization can be increased.

The present invention can be implemented with various other modifications. For example, instead of directly adopting the form of a 90° phase splitting narrowband filter as the digital filter 50 in FIG. It is clear from the nature of digital signal processing technology that similar functions can be provided. FIG. 9 shows another example of the configuration of the sampling phase error detection circuit 46, in which the digital filter 50 is a secondary cyclic filter that is a part of the 90° phase splitting narrowband digital filter shown in FIG. It consists only of type digital filters. That is, 91, 95 and 96 are coefficient multipliers, 92 is a synthesis circuit, and 93 and 94 are word memories. On the other hand, the arithmetic circuit 60 in this case consists of two multipliers 97 and 98 and a subtracter 99.

As mentioned above, the phase error signal x ₃ is two orthogonal signals
Since it can be obtained by multiplying x ₁ and x ₂ , (8)
From the formula, x ₃ ∝x ₁・x ₂ = 1/2F ² (z) z ^-1 (z ^-2 -1) = 1/2 {H ₁ (z) - H ₂ (z)} ... (13) Here, H ₁ (z)=z ^-1 F(z)・z ^-2 F(z) ...(14) H ₂ (z)=P(z)・z ^-1 F(z) ...( 15) is given by. F(z), z ^-1 F in formulas (14) and (15)
(z) and z ^-2 F(z) are respectively x ₂₁ and
Since it corresponds to x ₁ and x ₂₂ , these are processed by the arithmetic circuit 60.
It is clear that by multiplying each other by multipliers 97 and 98 and subtracting the result by subtractor 99, a phase error signal similar to that in the previous case can be obtained.

Figure 10 shows this invention in PM, quadrature AM, AM-
This is an embodiment applied to a quadrature modulated signal using a modulation method such as PM, and only the sampling phase error detection circuit is shown. In the figure, baseband orthogonal digital signals obtained by passing a received analog signal through an A/D conversion circuit are input to terminals 101 and 102, and these are respectively input to terminals 101 and 102.
The signals are combined by an adder 107 through digital filters 103, 104 and arithmetic circuits 105, 106 having the same configuration as shown in FIG. 6 or 9. As a result, a phase error signal 108 indicating the sampling phase error of the orthogonal digital signal is obtained at the output of the adder 107.

As explained in detail above, according to the present invention, the sampling rate can be lowered to, for example, twice the baud rate frequency, which is less than half of the conventional rate, and the number of calculation processes and hardware can be reduced. . Further, by adopting a configuration in which the phase error signal is output only once per baud rate as in the embodiment described above, it is possible to further reduce the number of arithmetic operations and the number of components.

Note that this invention is not only applicable when the sampling rate is twice the baud rate frequency, but also applicable when the sampling rate is set higher due to the design of the entire system such as a modem. In that case, it can be easily accommodated by changing the passband of a digital filter, noise suppression circuit (in the case of a high-pass filter), etc. in accordance with the speed of the input digital signal.

Also, if the analog signal input to the A/D conversion circuit is a passband signal, the sampling rate must be higher than twice the baud rate frequency, but in that case, the demodulated output of the passband signal The sampling phase synchronization circuit of the present invention may be applied by converting the sampling frequency to a lower sampling frequency.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional sampling phase synchronization circuit, Fig. 2 is a time chart for explaining its operation, Fig. 3 is a diagram also showing phase error detection characteristics, and Fig. 4 is an embodiment of the present invention. FIG. 5 is a diagram showing a specific configuration example of a digital filter used in the sampling phase error detection circuit according to the present invention, and FIG. 6 is a diagram showing a specific configuration example of the arithmetic circuit used in the present invention. 7 is a time chart for explaining the operation of the embodiment, FIG. 8 is a diagram showing the sampling phase error detection characteristics, and FIG. 9 is a sampling phase error detection circuit according to the present invention. FIG. 10 is a diagram showing another specific example of the configuration of the digital filter and arithmetic circuit used, and is a schematic configuration diagram of a sampling phase error detection circuit in another embodiment of the present invention. 41... Reception analog signal input terminal, 43...
A/D conversion circuit, 46...Sampling phase error detection circuit, 47...Noise suppression circuit, 50, 10
3,104...Digital filter, 60,10
5,106...Arithmetic circuit, 48...Variable frequency dividing circuit.

Claims (1)

[Claims] 1. A sampling phase error detection circuit that generates a phase error signal indicating a sampling phase error in the A/D conversion circuit from a digital signal obtained by passing a received analog signal through an A/D conversion circuit. In the sampling phase synchronization circuit that controls the sampling phase to be synchronized with the received analog signal based on the phase error signal, the phase error detection circuit substantially converts the digital signal into two orthogonal signals; A sampling phase synchronization circuit characterized in that a phase error signal is generated that causes a point at which the sampling phase error is zero to be a stable phase point of the sampling phase by performing nonlinear arithmetic processing on two orthogonal signals. 2. The sampling phase error detection circuit includes a 90° phase-splitting narrowband digital filter that receives the digital signal as input and obtains two orthogonal signals, and performs nonlinear arithmetic processing on the two orthogonal signals obtained by this filter to obtain a phase error signal. 2. The sampling phase synchronization circuit according to claim 1, wherein the sampling phase synchronization circuit is comprised of an arithmetic circuit. 3 90° phase split narrowband digital filter is
Claim 2, characterized in that it includes a second-order cyclic digital filter, and obtains orthogonal two signals by performing linear transformation on the output of this filter.
Sampling phase synchronization circuit described in section. 4 The arithmetic circuit is a multiplier that multiplies two orthogonal signals from a 90° phase split narrowband digital filter, or a polarity switching circuit that inverts the polarity of one of these two orthogonal signals depending on the sign of the other signal, or this orthogonal circuit. 3. The sampling phase synchronization circuit according to claim 2, wherein the sampling phase synchronization circuit is an exclusive OR circuit having two signals as both inputs. 5. The sampling phase synchronization circuit according to claim 1, wherein the A/D conversion circuit performs sampling at a frequency twice the baud rate frequency of the received analog signal. 6. The sampling phase synchronization circuit according to claim 1 or 2, wherein the sampling phase error detection circuit outputs the phase error signal once per baud rate of the received analog signal.