JPH01274548A - Demodulator - Google Patents

Abstract

PURPOSE:To facilitate the large scale circuit integration and the change in the bit rate by employing the digital circuit to all components except the pre- stage of an A/D converter and a sampling clock generator. CONSTITUTION:An orthogonal frequency converter comprising a local oscillator 10, a pi/2 phase shifter 20 and mixers 31, 32 applies orthogonal quasi synchronizing demodulation to a reception signal to convert it into a 2-series zero beat signal. The signal is converted into digital time series data D11, D12 via a sampling clock SC at A/D converters 51, 52 via low pass filters 41, 42. The data D11, D12 are demodulated at a complex number multiplier 70 via FIR filters 61, 62 applying main band limit by using time series data D21, D22 to form a data 50 representing a phase by a phase detector 80 and the signals D21, D22 are outputted via a loop filter 90, a phase generator 100 and a waveform generator 110. On the other hand, the data D41, D42 become the signal SC via a clock phase detector 120, a loop filter 130, a D/A converter 140 and a VCXO 150.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulator, and particularly to a demodulator for digital phase modulation signals.

[Conventional technology]

A conventional demodulation device for demodulating a digital phase keyed signal (PSK signal) includes a synchronous demodulation circuit, a reference carrier recovery loop,
It was constructed using a large number of analog circuits such as the clock regeneration loop.

[Problem to be solved by the invention]

The above-mentioned conventional demodulation device has the disadvantage that it is not suitable for LSI integration because it includes a large number of analog circuits, and analog circuits also have characteristics deterioration due to temperature and temporal fluctuations, and are unstable due to power supply voltage fluctuations, etc. Circuit design becomes difficult
There is a drawback.

An object of the present invention is to provide a demodulator that is suitable for LSI implementation and can easily accommodate changes in bit rate.

[Means to solve the problem]

The demodulator of the present invention includes an orthogonal frequency converter that converts the frequency of the digital phase modulation signal to a lower frequency band using two series of mutually orthogonal local oscillation signals having a frequency substantially equal to the carrier frequency of the digital phase modulation signal; A pair of A/D converters that sample and quantize two series of signals output by the frequency converter using a clock at the symbol center point and a sampling clock consisting of a clock at the center point of this clock, and this pair of A/D converters. A pair of digital filters band-limiting the two series of first time series data outputted by the D converter, and a pair of digital filters representing two series of mutually orthogonal reference carrier wave signals.
a complex multiplier that synchronously demodulates the two series of third time series data outputted by the pair of digital filters using the second time series data of the series; and a complex multiplier that synchronously demodulates the two series of third time series data outputted by the complex multiplier. a first phase detector that detects a phase error of the reference carrier signal from a time series of each data corresponding to the clock of the symbol center point among each data of the series data; and a digital first loop filter inputting fifth time series data;
a reference carrier generator that digitally generates the second time series data of the two series under the control of the sixth time series data outputted by the first loop filter; and a fourth time series data of the two series. a second phase detector that detects the phase error of the sampling clock from data; a digital second loop filter that receives seventh time-series data output from the second phase detector; and a sampling clock generator that generates the sampling clock under the control of the eighth time series data outputted from the second loop filter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment shown in FIG. 1 includes a local oscillator 10 that generates a local oscillation signal with a frequency approximately equal to the carrier number of a received signal S, which is a four-phase PSK signal in an intermediate frequency band, and a π/2 input local oscillation signal. A phase shifter 20, a mixer 31 that frequency-converts the received signal S to a low frequency range using a local oscillation signal, a mixer 32 that frequency-converts the received signal S to a low frequency frequency based on the output signal of the π/2 phase shifter 20; A low-pass filter 41.42 inputs the signal outputted by the low-pass filter 41, 42, and a sampling clock SC consisting of a clock at the symbol center point and a clock at the center point of this clock.
2 samples and quantizes the output signal to create time series data D.
I 1. A/D converter 51 outputting as Di2,
52, and the time series data D11°Di2 are band-limited and the time series data D31. FIR (fin) output as D32
ite impulse response) filters 61, 62, and time series data D21.62 representing two sequences of mutually orthogonal reference carrier signals. Time series data D by D22
31. D32 is synchronously demodulated and time series data D41. D42
The complex multiplier 70 outputs the time series data D41 as
．． A phase detector 80 detects the phase error of the reference carrier signal from the time series of each data corresponding to the clock at the symbol center point among the data D42 and outputs it as time series data D50; type loop filter 90 and a phase generator 100 that outputs time series data representing the instantaneous phase of the reference carrier signal under the control of the time series data D60 outputted by the loop filter 90.
Based on the time series data outputted by the phase generator 100, the time series data D21. Waveform generator 11 outputting D22
0 and time series data D41. A clock phase detector 120 that detects the phase error of the sampling clock SC from D42 and outputs it as time series data D70, and a digital loop filter 130 that inputs the time series data D70.
and the time series data D8 outputted by the loop filter 130.
A D/A converter 140 that converts 0 into a voltage signal;
A VCXO (voltage
controlledcry3iBl □sci! I
ator).

Local oscillator 10, π/2 phase shifter 20 and mixer 31.3
2 constitutes an orthogonal frequency converter, which makes the angular frequency ω of the local oscillation signal approximately equal to the carrier angular frequency ω6 of the received signal S, so this orthogonal frequency converter converts the received signal S into orthogonal quasi-synchronous It is demodulated and converted into two series of zero beat signals. The received signal S is S=P cos ω, t + Q sin ω,
t (1), and if the local oscillation signal output by the local oscillator 10 is cos ω, t, then the π/2 phase shifter 20
Since the output signal of is sin ω,t, mixer 31,
32 output signals A and B are A = (P CO3 (IJ, t + Q sin
ω, t)/2 (2) B= (-P sin
ωIt + Q cos ω, t)/2 (3). However, ω, = ω, −ω.

The output signals of mixers 31 and 32 are filtered by low-pass filters 41 and 42.
are sampled by the sampling clock SC in A/D converters 51 and 52, and converted into time series data Dll and D12 having the required number of bits. This sampling is performed at the symbol center point (the center point of the time slot of the received signal S) and at two points per symbol at the boundary between the time slots. The reason why double sampling is performed in this way is for clock synchronization, which will be explained later.

The time series data D11, D12 are band-limited by the FIR filters 61, 62 that limit the main band of the demodulator as a whole, and become time series data D31, D32, and the complex multiplier 70 converts the time series data D21. D22 synchronously demodulates the time series data D41. D42 is obtained. Time series data D21. Reference carrier signal C represented by D22
Considering the state before phase synchronization is established for 2D, C:C
03((17,t-θ-(t)) (4)D=s
When in(ω, is expressed as -θ(t)) (5), the complex multiplier 70 performs AC-BD and AD+BC operations. Therefore, the signals E and F represented by the time series data D41°D42 are E=(Pcosθ(t)+Qsinθ(t))
/ 2 (6) F=(-Psinθ(t)+Qco
sθ(t))/2 (7).

The phase detector 80 detects time series data D41. D42EE-
Perform the calculation 8GN (F)-F-8GN (E),
It is output to the loop filter 90 as time series data D50 representing the phase error.

The phase generator 100 and waveform generator 110 correspond to vCO of an analog circuit. The phase generator 100 is
Time series data of the instantaneous phase (ωft-θ(t)) of the reference carrier signals C and D is output so that the value represented by the time series data D60 output by the loop filter 90 approaches O.

The waveform generator 110 is a ROM table that outputs time series data D21°D22 of the reference carrier signals C and D in response to the time series data input from the phase generator 100.

Once synchronization of the carrier phase-locked loop from complex multiplier 70 to waveform generator 110 and back to complex multiplier 70 is established,
θ(1) in Equations 4 and 5 is O2π/2. π or 3π
/2, and as seen in equations 6 and 7, the time series data D41. Of the data of D42, each data corresponding to the clock at the symbol center point is obtained as demodulated data (including four-phase phase uncertainty). In addition, time series data D
Among the data of 41°D42, each data corresponding to the clock at the boundary of time slots does not necessarily include valid information for carrier phase synchronization and disturbs the operation of the loop, so the phase detector 80 uses time series data D41. Of the data in D42, only the data corresponding to the clock at the symbol center point is used, the others are discarded, and the operation is performed in a single sampling state.

Also, in principle, the FIR filters 61 and 62 can be placed after the complex multiplier 70, but if such an arrangement is used, the carrier phase-locked loop becomes unstable due to the large delay of the FIR filters 61 and 62. Because it is easy, FI
R filters 61 and 62 are placed before the complex multiplier 70.

When the sample values of two consecutive symbols have different signs, if the sampling points of both sample values are too early, the clock phase detector 120 detects the sign of the sample value at the center point of both sampling points and the sample immediately before that. The time series data D41. This is a well-known phase error detector that detects the lead or lag of the sampling clock SC from D42. The detected lead and lag are output to the loop filter 130 as time series data D70. Time series data D80 output by the loop filter 130
is converted into a voltage signal by the D/A converter 140, and by controlling the oscillation phase of the VCXO 150 with this voltage signal, the phase of the sampling clock SC is kept optimal.

〔Effect of the invention〕

As explained above, the present invention has the effect that the demodulation device can be easily integrated into an LSI by realizing it with digital circuits, which are all the constituent elements except for the part before the A/D converter and the sampling clock generator. , it has the effect of being able to respond to changes in the bit rate of the PSK signal by simply replacing the sampling clock generator, and furthermore, the first method detects the phase error of the reference carrier signal by double sampling with the A/D converter. By operating the phase detector as a single sampling, the operating performance of the carrier phase-locked loop can be improved while digitally controlling the phase of the sampling clock.Furthermore, the digital filter for main band limiting can be operated by complex multiplication. Placing it in front of the carrier has the effect of stabilizing the operation of the carrier phase-locked loop.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10...Local oscillator, 20...π/2
Phase shifter, 31.32...Mixer, 41.42.
...Low pass filter, 51.52...A/
D converter, 61.62...FIR filter, 7
0...Complex multiplier, 80...Phase detector, 90...Loop filter, 100...
... Phase generator, 110 ... Waveform generator, 12
0...Clock phase detector, 130...
・Loop filter, 140...D/A converter,
150...vcxo. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] an orthogonal frequency converter that converts the frequency of the digital phase modulation signal to a lower frequency band using two mutually orthogonal local oscillation signals having a frequency substantially equal to the carrier frequency of the digital phase modulation signal; A pair of A/D converters that sample and quantize a series of signals using a clock at the symbol center point and a sampling clock consisting of a clock at the center point of this clock, and this pair of A/D converters.
A pair of digital filters that band limit the two series of first time series data output by the D converter, and two digital filters that are orthogonal to each other.
a complex multiplier that synchronously demodulates the two series of third time series data output by the pair of digital filters using the two series of second time series data representing the series of reference carrier wave signals;
A first phase for detecting the phase error of the reference carrier signal from the time series of each data corresponding to the clock at the symbol center point among the two series of fourth time series data output by the complex multiplier. a digital type first loop filter into which the fifth time series data outputted by the first phase detector is input; and a control circuit for controlling the sixth time series data outputted by the first loop filter. a reference carrier generator that digitally generates the second time series data of the two series, and a second phase detector that detects a phase error of the sampling clock from the fourth time series data of the two series. A digital second loop filter receives the seventh time series data output from the second phase detector, and is controlled by the eighth time series data output from the second loop filter. A demodulation device comprising: a sampling clock generator that generates the sampling clock.