JP2837914B2 - AFC device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an automatic frequency control (AFC) device for π / 4 shift QPSK signal differential detection.

(Conventional technology) Conventionally, as an AFC device of a receiving unit of a communication device, a received signal is converted into an intermediate frequency signal by an oscillation output of a local oscillator, and a deviation of the intermediate frequency is detected by a frequency discriminator. A device which corrects the deviation of the intermediate frequency by controlling the oscillation frequency by feeding back to the local oscillator has been widely used (for example, "Microwave Communication Engineering" edited by Microwave Technology Research Group (Showa 47-3). -20) Telecommunications Association of Japan, p356-361).

(Problems to be Solved by the Invention) However, since the spectrum of a modulation signal based on a digital signal such as a π / 4 shift QPSK modulation signal may be deviated with respect to the center frequency due to the pattern of the digital signal, the above-described configuration is used. The AFC device has a drawback that the difference between the frequency difference between the oscillation output of the local oscillator of the receiving unit and the received signal cannot always be detected correctly.

The present invention has been made in order to eliminate the above-described drawbacks, and performs signal processing based on two signals of an in-phase component and a quadrature component obtained by delay-detecting a π / 4-shifted QPSK signal, and adjusts the phase of the modulated signal. An object of the present invention is to provide an AFC device capable of obtaining an irrelevant AFC control signal.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an input π / 4 shift QP.
The SK signal is shifted by a first and second base frequency band π / 4 having a quadrature phase relationship by an output signal of a variable frequency oscillator.
Frequency converting means for converting the frequency into a QPSK signal;
And a delay detection processing circuit that outputs two delay detection signals having a quadrature phase relationship obtained by delay detection of a π / 4 shift QPSK signal of a second base frequency band, and an amplitude based on the two delay detection signals. It is a function of the frequency shift between the input π / 4 shifted QPSK signal and the output signal of the variable frequency oscillator
It has AFC detection means for outputting an AFC signal, and integration means for integrating the AFC signal, wherein the output of the integration means is fed back to the variable frequency oscillator to control the oscillation frequency.

(Operation) The input π / 4 shift QPSK signal is converted into two base frequency band π / 4 shift QPSK signals having a quadrature phase relationship by frequency conversion means, and then delayed detection is performed by a delay detection processing circuit. Two differential detection signals having a quadrature phase relationship are output.

However, when the frequency of the input π / 4 shift QPSK signal does not match the frequency of the output signal of the variable frequency oscillator of the frequency conversion means, a component of the frequency difference due to the frequency mismatch is present in the differential detection signal, and the delay detection is performed. The signal deteriorates.

Therefore, the frequency difference component included in the differential detection signal is detected by the AFC detection unit, and the component of the frequency difference included in the differential detection signal is fed back to the variable frequency oscillator via the integration unit, and subjected to AFC. The difference component is suppressed. Here, in order to apply stable AFC, it is necessary that the AFC is not affected by the modulation signal component of the π / 4 shift QPSK signal. Therefore, focusing on the fact that the phase of the differential detection signal, that is, the phase difference between the input signal and the input signal one symbol time before, always becomes an integral multiple of 2π (rad) when multiplied by 8, the AFC detection means The phase difference component is skillfully erased to extract only the frequency difference component. This realizes a stable AFC that is not affected by the modulation component of the input signal.

(Embodiment) FIG. 1 is a configuration diagram of an embodiment of the present invention. Hereinafter, the first
This will be described in detail with reference to the drawings.

Apply a π / 4 QPSK signal x from the terminal. Where π / 4QPSK
The signal x is represented by Expression (1).

x = cos (ω ₁ t + θ _N ) (1) where ω ₁ ; angular frequency θ _n ; o, π / 4, π / 2,3π / 4,5π / 2,3π / 2,7π / 4 in phase / 4QPSK signal x is split into two, one of which is multiplier 2
, And the other is applied to a first input terminal of the multiplier 4. Also, the output y of the variable frequency oscillator 5 is branched into two, and one of them is passed through the π / 2 (rad)
And the other is applied to the second input terminal of the multiplier 2. Here, the output y of the variable frequency oscillator 5 is represented by Expression (2).

y = cos (ω ₂ t + φ) (2) where ω ₂ ; angular frequency φ; phase multipliers 2 and 4 calculate the product of both signals input to the first and second input terminals, and calculate the result. It is applied to the input terminals 8 and 9 of the differential detection processing circuit 100 through the low-pass filters 6 and 7. The signals a and c at the input terminals 8 and 9 are expressed by Expressions (3) and (4), respectively. This is a QPSK signal in the base frequency band.

a = cos ｛Δωt + θ _n -φ｝ (3) where Δω = ω ₁ -ω ₂ c = cos ｛Δωt + θ _n -φ-π / 2｝ (4) In the delay detection processing circuit 100, The signal a is branched and applied to the first input terminals of the multipliers 12 and 14 and to the delay element 10. Similarly, the signal C applied to the input terminal 9 is branched, and the signals are applied to the multipliers 13 and 1.
5 as well as to the first input terminal and to the delay element 11. Since the delay elements 10 and 11 each provide a delay (τ) of one time slot, signals b and d represented by Expressions (5) and (6) are obtained at the output.

_{b = cos {Δωt + θ n} -1 -Δωt-φ} (5) where θ _n-1; θ _n in a time slot phase of the previous signal to, ± respect _{θ n π / 4, ± 3π} / 4 Has the following phase difference.

d = cos {Δωt + θ _n−1 Δωt−φ−π / 2} (6) The signal b is input to the second input terminal of the multiplier 12 and is multiplied by the signal a input to the first input terminal. Ask for. As a result, a signal g shown in Expression (7) is obtained at the output of the multiplier 12.

g = a * b = 1 / 2cos ｛2Δωt-2φ + θ _n + θ _n-1 -Δωt｝ + 1 / 2cos ｛θ _n -θ _n-1 + Δωt｝ (7) The product is input to the input terminal and is multiplied by the signal a input to the first input terminal. As a result, a signal e shown in Expression (8) is obtained at the output of the multiplier 14.

e = a * d = 1 / 2cos ｛2Δωt + 2φ + θ _n + θ _n-1 −Δωt-π / 2｝ + 1 / 2cos ｛θ _n -θ _n-1 + Δωt + π / 2｝
(8) The signal d is input to the second input terminal of the multiplier 13 and the product of the signal d and the signal c input to the first input terminal is obtained.
As a result, a signal h shown in Expression (8) is obtained at the output of the multiplier 13.

h = c * d = -1 / 2cos {2Δωt-2φ + θ n -θ n-1 -Δωt} + 1 / 2cos {θ n -θ n-1 + Δωt} (9) Further, the multiplier 15 the signal b The product of the signal c input to the second input terminal and the signal c input to the first input terminal is obtained. As a result, a signal f shown in Expression (10) is obtained at the output of the multiplier 15.

f = b * c = 1 / 2cos {2Δωt + θ n + θ n-1 -Δωt-2φ-π / 2} + 1 / 2cos {θ n-1 -θ n + Δωt-π / 2} (10) subtracting the signal e The signal f is applied to a first input terminal of the detector 16 and to a second input terminal, respectively, and the difference between the two signals is obtained. As a result, a signal i shown in Expression (11) is obtained at the output of the subtractor 16.

i = fe = cos {θ _n −θ _n−1 + Δωt−π / 2} (11) Further, the signal g is supplied to a first input terminal of an adder 17, and the signal h is supplied to a second input terminal. , And both signals are added. As a result, a signal k shown in Expression (12) is obtained at the output of the adder 17.

k = g + h = cos {θ _n −θ _n−1 + Δωt} (12) The signals k and i are output to the output terminals 32 and 33 of the differential detection processing circuit 100.
Output terminals, and output terminals as differential detection output signals
Output from 20,21 to outside.

The signal k from the output terminal 32 is input to first and second input terminals of the multiplier 23, and the signal k is squared. As a result, a signal n shown in Expression (13) is obtained at the output of the multiplier 23.

^{n = k 2 = 1/2} + 1 / 2cos {2 (θ n -θ n-1) + 2Δωt}
(13) Similarly, the signal i from the output terminal 33 is input to the first and second input terminals of the multiplier 24, and the signal i is squared.
As a result, a signal O shown in Expression (14) is obtained at the output of the multiplier 24.

o = i ² = 1 / 2−1 / 2cos {2 (θ _n −θ _n−1 ) + 2Δωt}
(14) Further, the signals n and o are input to the subtractor 25, and the difference between the two signals is obtained. As a result, the expression (15) is output to the output of the arithmetic unit 25.
Is obtained.

p = no = -cos {2 ([theta] _{n- [} theta] _{n -1} ) +2 [Delta] [omega] t} (15) On the other hand, the signals i and k are input to the multiplier 22, and the product of both signals is obtained. As a result, the output of the multiplier 22 is given by the equation (1)
The signal m shown in 6) is obtained.

m = k * i = 1 / 2cos {2 ([theta] _{n- [} theta] _{n -1} ) +2 [Delta] [omega] t- [pi] / 2} (16) The signals m and p are input to the multiplier 26, and the product of both signals is obtained. As a result, a signal g shown in Expression (17) is obtained at the output of the multiplier 26.

g = m * p = 1 / 4cos {4 ([theta] _{n- [} theta] _{n -1} ) +4 [Delta] [omega] t- [pi] / 2} (17) The signal m is input to the first and second input terminals of an adder, and is equivalent. Then, the amplitude of the signal m is doubled. This allows
A signal j shown in Expression (18) is obtained at the output of the adder 18. In addition,
It is needless to say that the same result can be obtained by replacing the adder 18 with a multiplier, adding the signal m to one input terminal of the multiplier, and adding a constant 2 to the other terminal.

j = m + m = cos {2 ([theta] _{n- [} theta] _{n -1} ) +2 [Delta] [omega] t- [pi] / 2} (18) The signal j is input to the first and second input terminals of the multiplier 19, and the square of the signal j is calculated. Ask for. As a result, a signal 1 shown in Expression (19) is obtained at the output of the multiplier 19.

l = j ² = 1 / 2−1 / 2cos {4 (θ _n −θ _n−1 ) + 4Δωt}
(19) Further, the signal p is input to the first and second input terminals of the multiplier 27, and the square of the signal p is obtained. This allows
The signal r shown in equation (20) is obtained at the output of the multiplier 27.

r = p ² = 1 / 2−1 / 2cos {4 (θ _n −θ _n−1 ) + 4Δωt}
(20) Further, the signals r and l are input to a subtractor 28, and the difference between the two signals is obtained. As a result, the expression (21) is output to the output of the arithmetic unit 28.
Is obtained.

s = r−l = cos {4 (θ _n −θ _n−1 ) + 4Δωt} (21) Since both signals input to the subtractor 28 need only have the same amplitude coefficient, To multiplier 19
A circuit for increasing the amplitude coefficient by four times may be inserted in the subsequent stage,
Furthermore, it is equivalent to insert a circuit to increase the amplitude coefficient by a factor of 1/2 before the multiplier 27, or insert a circuit to increase the amplitude coefficient by a factor of 1/4 after the multiplier 27. Needless to say.

The signals q and s are further input to a multiplier 29, where a product of the two signals is obtained. As a result, a signal t shown in Expression (22) is obtained at the output of the multiplier 29.

t = q * s = cos ｛8 (θ _n -θ _n-1 ) + 8Δωt-π / 2｝ (22) (θ _n -θ _n-1 ) of this signal t is ± π / 4 or ± 3
Since it takes four values of π / 4, when it is multiplied by 8, it becomes an integral multiple of 2π, and Expression (24) can be expressed by Expression (25).

t = cos (8Δωt−π / 2) (23) From the equation (23), it can be seen that the magnitude of the signal t is a function of the frequency error Δω without depending on the modulation signal.

Therefore, AFC can be performed by feeding back the signal t to the frequency control terminal 31 of the variable frequency oscillator 5 through the integrator 30 including an up-down counter and a low-pass filter.

(Effects of the Invention) As described above in detail, according to the present invention, the AFC signal fed back to the variable frequency oscillator is irrelevant to the modulation signal of the input π / 4 shift QPSK signal. Stable AFC can be applied even if a spectrum deviation occurs in the π / 4 shift QPSK signal.

In addition, AFC, which is usually used in the receiver of a communication device, etc.
A discriminator is unnecessary, and a frequency control signal can be obtained by multiplication and addition in the base frequency band, so that digital signal processing integrated circuits can be easily used, and an AFC device can be economically realized. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention. 1 ... Input terminal, 2,4,12-15,19,22-24,26,27,29 ...
Multiplier, 3 ... Phase shifter, 5 ... Variable frequency oscillator, 6,7
…… Low-pass filter, 8,9 …… Input terminal, 10,11 …… Delay element, 16,25,28 …… Subtractor, 17,18 …… Adder, 20,21,3
2,33 output terminal, 30 integrator, 31 frequency control terminal, 100 delay detection processing circuit

Claims (2)

(57) [Claims] An input π / 4 shift QPSK signal is frequency-converted into a base frequency band π / 4 shift QPSK signal by an output signal of a variable frequency oscillator, and the base frequency band π / 4 shift QPSK signal is converted for one symbol time. The phase value of the delayed signal is π
A first differential detection signal having a phase value obtained by subtracting the value obtained by adding / 2 from the phase value of the base frequency band π / 4 shift QPSK signal, and a second differential detection signal having a quadrature phase relationship with the first differential detection signal.
Delay detection means for outputting a differential detection signal of the following, first means for squaring each of the two delay detection signals, and calculating and outputting the difference between them, and a second means for outputting a product of the two delay detection signals Means for obtaining a product of the output signals of the first means and the second means, and outputting the product; and a fourth means for doubling and squaring the amplitude of the output signal of the second means. Means for squaring the output signal of the first means to obtain the difference between the output signal of the fourth means and outputting the difference, and output means for the third means and the fifth A sixth means for obtaining a product of the output signals of the means and outputting the result as an AFC signal; and an integrating means for integrating and outputting the AFC signal. The output of the integrating means is fed back to the variable frequency oscillator. An AFC device characterized by controlling the oscillation frequency by using an AFC device. 2. The delay detection means according to claim 1, wherein said delay detection means comprises an input π / 4 shift QPSK.
Π / 4 shift QP of the first and second base frequency bands having a quadrature phase relationship by the output signal of the variable frequency oscillator
Frequency conversion means for converting the frequency to an SK signal; first delay means for delaying the π / 4 shift QPSK signal of the first base frequency band by one symbol time; π / 4 of the second base frequency band A second delay means for delaying the shifted QPSK signal by one symbol time; a product of an output signal of the first delay means and a π / 4 shifted QPSK signal in the second base frequency band; Means for obtaining a product difference between the output signal of the means and the π / 4-shifted QPSK signal of the first base frequency band and outputting one of the differential detection signals; and the output signal of the first delay means and the second A product of the first base frequency band π / 4 shift QPSK signal, the output signal of the second delay means, and the π / 4 shift QPSK signal of the second base frequency band
2. The AFC apparatus according to claim 1, further comprising means for obtaining a sum of products of the signals and outputting the other differential detection signal.