JP3462277B2 - Carrier recovery circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is required when a signal transmitted by QPSK (quadrature phase shifkeying) is demodulated on a receiving side in a communication satellite or microwave communication. And a technique for reproducing a carrier wave. [0002] In communication satellites and microwave communications, QP
In recent years, a method of transmitting data by SK has become popular. In general, when demodulating a phase-modulated signal such as QPSK on the receiving side, it is necessary to generate a reference carrier by some method. For example, in a demodulation method called Costas Loop, which is generally used for demodulating a phase-modulated wave, a received phase-modulated wave is shifted from a reference carrier by a reference carrier and a phase shifted by π / 2. Demodulation is performed by multiplying (mixing) with a carrier. The above-mentioned Costas loop demodulation method is shown in FIG.
This will be briefly described with reference to FIG. The input phase modulated wave supplied to the input terminal 1 is branched into two systems. One of them is multiplied by a reference carrier outputted from a voltage controlled oscillator (hereinafter referred to as VCO) 2 in a multiplier 4 and the other is multiplied by a VCO 2
Are multiplied in the multiplier 5 by the π / 2 phase shifter 3 with the phase shifted by π / 2, and the signals Yc (t) and Ys ( t). The output signals Yc (t) and Ys (t) of the multipliers 4 and 5 are respectively passed through low-pass filters 6 and 7 to extract only the difference component, and the difference component signals Zc (t) and Zs (t) ). Here, if the phase tracking error of the loop is φ, the difference component signal
Zc (t) and Zs (t) have this phase tracking error
Appears in the form of s φ and sin φ. Therefore, the signal obtained by obtaining the product of the difference component signals Zc (t) and Zs (t) by the multiplier 8 has a phase tracking error of cos φ.
Since it appears in the form of sin φ = sin 2 φ / 2, this is supplied as a control signal to the VCO 2 via the loop filter 9. In this way, an error discrimination function is realized, and the loop control system performs a tracking operation so that the phase tracking error φ becomes zero. [0004] The feature of the Costas loop demodulation system described above is that the phase is equivalently multiplied, and the output thereof controls the phase of an oscillator that generates a reference carrier. That is, since there is basically no frequency comparison characteristic, if the frequency of the phase modulated wave and the reference carrier do not match, there is a drawback that the phase lock is not activated and the carrier cannot be reproduced. Conventionally, in order to reduce such a drawback, it is necessary to use components having high frequency stability for the transmission side and the reception side equipment, and there is a drawback that the cost increases. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional disadvantages and to lock the phase of a reference carrier even when a large frequency shift occurs between an input phase modulation wave and a reference carrier in microwave relaying or the like. Therefore, it is an object of the present invention to provide a carrier recovery circuit which can realize a radio with simple and inexpensive components. According to the present invention, there is provided a phase error detecting means for detecting a phase error between a modulated carrier included in quadrature detection output signals I and Q and a reference carrier for performing quadrature detection. And a voltage-controlled oscillator for generating a reference carrier whose frequency is controlled in accordance with the phase error output from the phase error detection means. Frequency shift direction detecting means for detecting the direction of the frequency shift with respect to the carrier, control signal generating means for outputting a control signal based on the output signal of the frequency shift direction detecting means, and frequency control in accordance with the control signal Variable oscillating means for generating a corrected signal, multiplying the correction signal generated from the variable oscillating means and the carrier generated from the voltage controlled oscillator Multiplying means for outputting a reference carrier whose frequency has been corrected, wherein the frequency shift direction detecting means multiplies quadrature detection output signals I and Q by first multiplying means; and quadrature detection output signals I and Q Second multiplying means for multiplying the sum and the difference, third multiplying means for multiplying output signals of the first and second multiplying means, and sum of output signals of the first and second multiplying means Multiplying means for multiplying the difference between the first and second multiplying means, a first low-pass filter for extracting a low-frequency component of the output signal of the third multiplying means, and a low-frequency component of the output signal of the fourth multiplying means. A second low-pass filter for extracting the following, and a first phase difference detecting means for detecting a phase difference between an output signal of the first low-pass filter and an output signal of the second low-pass filter And extracting the low frequency component of the output signal of the first phase difference detecting means. A third low-pass filter, a first comparator that compares an output signal of the third low-pass filter with a first reference value, and a third comparator that outputs an output signal of the third low-pass filter. And a second comparator for comparing the output signal of the second comparator with a reference value of 2. The control signal generation means uses the output signal of the first comparator as a count start / stop command and outputs the output signal of the second comparator. , A counter for counting clock signals of a predetermined frequency using count up / down commands, a variable frequency divider whose frequency division ratio is controlled according to the count value of the counter, a fixed oscillator, and an output of the fixed oscillator. A fixed frequency divider for dividing a signal; second phase difference detecting means for detecting a phase difference between an output signal of the variable frequency divider and an output signal of the fixed frequency divider; A fourth low-pass for extracting a low-pass component of the output signal of the phase difference detection means An over-filter, wherein the variable oscillating means includes a second voltage-controlled oscillator that receives the output signal of the fourth low-pass filter as a control signal and generates the correction signal. It is. According to the carrier recovery circuit of the present invention, the frequency of the correction signal output from the variable oscillation means is controlled in accordance with the direction of the frequency shift between the modulated carrier and the reference carrier. Therefore, the frequency lock can be performed in a wide frequency range. As a result, the voltage controlled oscillator does not require much frequency stability, and therefore can be realized with inexpensive components, and the cost can be reduced. FIG. 2 is a block diagram showing a basic configuration of a carrier recovery circuit according to the present invention. The phase modulation signal supplied to the input terminal 11 is supplied to the demodulation means 12. This demodulation means
12 is also supplied with a reference carrier generated by a voltage controlled oscillator 13. The quadrature detection output signals I and Q output from the demodulator 12 are supplied to the phase error detector 14 to detect the phase error between the modulated carrier and the reference carrier. This phase error is supplied to the voltage controlled oscillator 13 as a control signal, and the oscillation frequency of the voltage controlled oscillator is controlled. In the steady state in which the phase is locked, the phase of the reference carrier output from the voltage-controlled oscillator 13 changes following the phase of the input modulated carrier.
For example, when the phase lock is released for some reason in the initial state or during communication, it is necessary to perform troublesome synchronization pull-in. For this reason, conventionally, the transmitter and the receiver are configured using components having high frequency stability so as not to lose the phase lock. An object of the present invention is to provide a carrier recovery circuit that can eliminate the need to use expensive components having high frequency stability. In the present invention, the quadrature detection output signals I and Q output from the demodulator 12 are supplied to the frequency shift direction detector 15 to detect the direction of the shift between the frequency of the modulated carrier and the frequency of the reference carrier. The detection output signal is supplied to the control signal generation means 16 to generate a control signal for correcting the frequency shift. This control signal is sent to the variable oscillation means 17
To generate a correction signal controlled according to the control signal. The variable oscillating means 17 can be constituted by a voltage-controlled oscillator similar to the VCO 13, but can be constituted by other means. For example, it is also possible to provide a plurality of oscillators having different oscillation frequencies, switch these by a control signal, and selectively output an output signal of an oscillator which oscillates at a desired frequency. The correction signal generated from the variable oscillation means 17 is supplied to the multiplication means 18 in this way. The multiplying means 18 is also supplied with a reference carrier generated from the VCO 13. Now, assuming that the frequency of the reference carrier generated from the VCO 13 is f ₁ and the frequency of the correction signal generated from the variable oscillating means 17 is f ₂ , the reference having the frequency of f ₁ ± f ₂ is obtained from the multiplying means 18. A carrier will be output. Now, consider the case where the frequency of the modulated carrier and the frequency of the reference carrier are shifted for some reason and the phase lock is lost. At this time, the frequency of the carrier wave generated from the VCO 13 changes according to the phase error detected by the phase error detecting means 14, but the frequency variable range is narrow, so that the phase lock may not be applied in some cases. In the present invention, the frequency shift direction detecting means 15 detects the direction of the frequency shift between the modulated carrier and the reference carrier, and accordingly, the control signal generating means
A control signal is generated at 16 and supplied to the variable oscillating means 17 to generate a correction signal having a frequency so as to eliminate the above-mentioned frequency deviation, and this is supplied to the multiplying means 18 together with the output signal of the VCO 13 to perform correction. A reference carrier whose frequency is corrected by the signal is generated.
Since the frequency of this correction signal can be changed over a larger frequency range than the output signal of the VCO 13, the frequency of the reference carrier can be quickly matched to the frequency of the modulated carrier, and phase locking can be easily achieved. Can be done. Therefore, the VCO 13 does not need to be formed of components having high frequency stability, and can be formed at low cost. FIG. 3 is a block diagram showing the configuration of an embodiment of the carrier recovery circuit according to the present invention. In this example,
It is assumed that a reference carrier used for demodulating a phase modulated signal by QPSK is reproduced. An input terminal 21 is supplied with a phase modulation signal S _RF (t), which is a reference carrier signal whose phase is shifted by π / 2 with respect to each other in a QPSK demodulator 22.
Demodulated by S _LO1 (t) and S _LO2 (t), quadrature detection output signals I and Q are obtained. Obtaining these quadrature detection output signals I and Q is not the object of the present invention, but supplies these signals to output terminals 23 and 24, respectively.
Now, the angular frequency of the QPSK modulated signal is ω _RF , the angular frequency of the reference carrier is ω _LO , K = 0, 1, 2, 3, the initial phase of the QPSK modulated signal is φ _RF , the initial phase of the reference carrier is φ _LO , Assuming that the time is t, the above-described phase modulation signal and reference carrier signal are expressed as follows. S _RF (t) = cos (ω _RF t + ((2K + 1) / 4) π + φ _RF ) --- (1) S _LO1 (t) = cos (ω _LO t + φ _LO ) --- (2) S _LO2 (t) = sin (ω _LO t + φ _LO )-(3) The demodulation means 12 shown in FIG. 2 is, for example, the π / 2 phase shifter 3 and the multiplier 4 shown in FIG. , 5, and the low-pass filters 6, 7, etc. The signals given by the equations (2) and (3) are signals appearing inside the demodulator 22, and their phases are shifted from each other by π / 2. Things. As shown in FIG. 2, assuming that the quadrature detection output signal I output from the QPSK demodulator 22 is Y ₁ (t), these are expressed as follows. Y ₁ (t) = S _RF (t) ・ S _LO1 (t) = 1/2 cos ｛(ω _RF + ω _LO ) t + ((2K + 1) / 4) π + (φ _RF + φ _LO )｝ + cos ｛ (ω _RF −ω _LO ) t + ((2K + 1) / 4) π + (φ _RF −φ _LO )｝ --- (4) The first term on the right side of this equation is the second low-pass filter 34. If the coefficient is attenuated and the coefficient is omitted, the above equation (4) is rewritten as follows. Y ₁ (t) = cos ｛(ω _RF −ω _LO ) t + ((2K + 1) / 4) π + (φ _RF −φ _LO )｝ --- (5) Similarly, output from QPSK demodulator 22. If the quadrature detection output signal Q is Y ₂ (t), it is expressed by the following equation. Y ₂ (t) = sin ｛(ω _RF −ω _LO ) t + ((2K + 1) / 4) π + (φ _RF −φ _LO )｝ --- (6) where θ (t) = (ω _RF − ω _LO ) t + ((2K + 1) / 4) π + (φ _RF −φ _LO ) --- (7), Y ₁ (t) and Y ₂ (t) become Y ₁ (t) = cos ｛ θ (t)｝ --- (8) Y ₂ (t) = sin ｛θ (t)｝ --- (9) These quadrature detection output signals Y ₁ (t) and Y ₂
(t) is supplied to a first multiplier 25 to generate a signal Y ₃ (t). This signal Y ₃ (t) is expressed as follows. Y ₃ (t) = Y ₁ (t) ・ Y ₂ (t) → sin ｛2 θ (t)｝ --- (10) Further, the quadrature detection output signals Y ₁ (t) and Y ₂ (t) are The signals are supplied to a first sum circuit 26 and a first difference circuit 27 to generate sum signals and difference signals Y ₄ (t) and Y ₅ (t). The sum signal and the difference signal are as follows. Y ₄ (t) = Y ₁ (t) + Y ₂ (t) → cos ｛θ (t)｝ + sin ｛θ (t)｝ --- (11) Y ₅ (t) = Y ₁ (t) −Y ₂ (t) → cos ｛θ (t)｝ − sin ｛θ (t)｝ --- (12) The output signals of the first sum circuit 26 and the difference circuit 27 are
To generate the following signal Y ₆ (t). Y ₆ (t) = Y ₄ (t) · Y ₅ (t) → cos ｛2θ (t)｝-(13) The output signals Y ₃ (t) of the first multiplier 25 and The output signal Y ₆ (t) of the second multiplier 28 is supplied to the third multiplier 29 to generate the next signal Y ₇ (t). Y ₇ (t) = Y ₃ (t) · Y ₆ (t) → sin ｛4 θ (t)｝ --- (14) Further, the output signal Y ₃ (t) of the first multiplier 25 is The output signal Y ₆ (t) of the multiplier 28 is supplied to a second sum circuit 30 and a second difference circuit 31 to generate the following signals Y ₈ (t) and Y ₉ (t). Y ₈ (t) = Y ₆ (t) + Y ₃ (t) → cos ｛2 θ (t)｝ + sin ｛2 θ (t)｝ --- (15) Y ₉ (t) = Y ₆ (t) −Y ₃ (t) → cos ｛2 θ (t)｝ −sin ｛2 θ (t)｝ --- (16) The output signal Y ₈ (t) of the second sum circuit 30 and the output of the difference circuit The signal Y ₉ (t) is supplied to the fourth multiplier 32 to obtain the following signal
Create Y ₁₀ (t). Y ₁₀ (t) = Y ₈ (t) Y ₉ (t) → cos ｛4 θ (t)｝ --- (17) Equations (14) and (15) above give equation (7) And the initial phase is set to 0, the following equation is obtained. Y ₇ (t) = sin ｛4 (ω _RF −ω _LO ) t｝ --- (18) Y ₁₀ (t) = cos ｛4 (ω _RF −ω _LO ) t｝ --- (19) From (18) and (19), the following is obtained by comparing ω _RF and ω _LO . i) When ω _RF > ω _LO , Y ₇ (t) = sin ｛4 | ω _RF -ω _LO | t｝ --- (20) Y ₁₀ (t) = cos ｛4 | ω _RF -ω _LO | t｝ --- (21) ii) When ω _RF <ω _LO , Y ₇ (t) = −sin ｛4 │ω _RF −ω _LO │t｝ --- (22) Y ₁₀ (t) = cos ｛4 | ω _RF −ω _LO | t｝ --- (23) iii) When ω _RF = ω _LO , Y ₇ (t) = 0 --- (24) Y ₁₀ (t) = 1 --- (25) From Equations (20), (21), (22) and (23), Y ₇ (t) and
By comparing the phase with Y ₁₀ (t), the direction of the shift between the frequency of the modulated carrier and the frequency of the reference carrier can be detected. That is, the phase of Y ₁₀ (t) is π / 2 based on Y ₇ (t).
When leading, ω _RF > ω _{LO When} the phase of Y ₁₀ (t) is delayed by π / 2 with respect to Y ₇ (t), ω _RF <ω _LO . In other words, the phase lock is established by detecting the phase difference between Y ₇ (t) and Y ₁₀ (t) and controlling the frequency according to the phase difference. Therefore, in the present embodiment, the output signal Y ₇ (t) of the third multiplier 29 is supplied to the first phase difference detector 35 via the first low-pass filter 33 and the fourth The output signal Y ₁₀ (t) of the multiplier 32 is supplied to a first phase difference detector 35 via a second low-pass filter 34, and a signal indicating the direction of a shift between the modulated carrier frequency and the reference carrier frequency is obtained. The output signal of the first phase difference detector 35 is supplied to the first and second comparators 37 and 38 constituting the control signal generating means 16 via the third low-pass filter 36. These first and second comparators 37 and 38 are also supplied with first and second reference values, respectively. The first comparison circuit 37 is the third comparison circuit.
The signal output from the low-pass filter 36 is compared with a first reference value for determining whether to correct the frequency of the reference carrier, and a count start / stop command is output to the counter 38. The second comparator 38 outputs a count up / down command. This counter 39 has a clock generator
Supply clock from 40. Further, the count value of the counter 39 is set to a fixed value in advance according to the frequency of the carrier. The count value of the counter 39 is changed by a variable oscillation means.
Supply to 17. The variable oscillating means 17 of this example is constituted by a PLL circuit for determining final data to be corrected. That is, the first voltage controlled oscillator 41 is provided, the output clock thereof is counted down by the prescaler 42, and the output is supplied to the variable frequency divider 43. The frequency division ratio of the variable frequency divider 43 is
Control is performed by the count value of the above-described counter 39, and the output is supplied to one input terminal of the second phase difference detector 44. The other input terminal of the second phase difference detector 44 is supplied with a signal obtained by dividing the clock generated by the fixed oscillator 45 by the fixed divider 46. The output signal of the second phase difference detector 44 is supplied as a control signal to the first VCO 41 via the fourth low-pass filter 47. In this way, the first VCO 41 can generate a correction signal having a frequency corresponding to the direction of the shift between the frequency of the modulated carrier and the frequency of the reference carrier. On the other hand, the output signal Y ₇ (t) of the third multiplier 29 is supplied as a control signal to a second voltage-controlled oscillator (VCO) 49 through a fifth low-pass filter 48, VC
The O oscillation output signal is supplied to the fifth multiplier 50 as a reference carrier. The fifth multiplier 50 has the first V
The correction signal output from the CO 41 is also supplied. Now, if the frequency of the modulated carrier is 130 MHz, the second VCO
The frequency of the signal output from 49 is 120 MHz, and the first V
By setting the frequency of the correction signal output from the CO 41 to 10 MHz, a 130 MHz reference carrier can be output from the fifth multiplier 50, and this reference carrier is supplied to the QPSK demodulator 22. Here, the control voltage vs. oscillation frequency characteristic of the first VCO 41 is set to, for example, 10 MHz ± 1 MHz, and the second VCO 41
Assuming that that of 49 is 120 ± 10 KHz, if the phase lock is lost, the frequency of the reference carrier is changed by changing the frequency of the correction signal generated from the first VCO 41 over a wide range. By quickly matching the frequency, the phase lock can be quickly applied,
Thereafter, by slightly changing the oscillation frequency of the second VCO 49, the frequency of the reference carrier can be made to accurately follow the frequency of the modulated carrier. That is, when the angular frequency of the input modulation signal is higher than the angular frequency of the reference carrier, the counter 39 counts up, and the frequency division ratio of the variable frequency divider 43 increases.
The frequency of the correction signal generated from the first VCO 41 increases, and the frequency of the reference carrier also increases. On the contrary,
When the angular frequency of the input modulation signal is lower than the angular frequency of the reference carrier, the counter 39 counts down, the frequency division ratio of the variable frequency divider 43 decreases, and the frequency of the correction signal generated from the first VCO 41 And the frequency of the reference carrier also decreases. When the angular frequency of the input modulation signal is equal to the angular frequency of the reference carrier, the operation of the counter 39 stops and the state is maintained. The present invention is not limited to the above-described embodiment, and many modifications and variations are possible. For example, in the above-described embodiment, an analog signal is processed. However, a digital signal can be processed. Further, in the above-described embodiment, the variable oscillation means changes its output frequency stepwise, but it may change continuously. According to the carrier recovery circuit of the present invention described above, even if the frequency of the input modulated carrier and the frequency of the reference carrier are shifted, the phase can be locked over a wide frequency range. . Therefore, even in a radio device that required a high degree of frequency stability in the past, what could not be realized without using expensive components due to the expansion of the phase lock range on the receiving side, the present invention allows even inexpensive components. It can be realized and cost performance can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a conventional Costas loop type QPSK demodulation circuit. FIG. 2 is a block diagram showing a basic configuration of a carrier recovery circuit according to the present invention. FIG. 3 is a block diagram showing a configuration of a QPSK receiving side including an embodiment of a carrier recovery circuit according to the present invention. [Description of Signs] 12 Demodulation means 13 Voltage controlled oscillator 14 Phase difference detection means 15 Frequency shift direction detection means 16 Control signal generation means 17 Variable oscillation means 25 First multiplier 26 First sum circuit 27 First difference circuit 28 Second Multiplier 29 Third multiplier 30 Second sum circuit 31 Second difference circuit 32 Fourth multiplier 33, 34 First and second low-pass filters 35 First phase difference detector 36 Third low-pass filter 37, 38 First and second comparators 39 Counter 40 Clock generator 41 First voltage controlled oscillator 42 Prescaler 43 Variable frequency divider 44 Second phase difference detector 45 Oscillator 46 Fixed frequency divider 47 Fourth low-pass filter 48 5 low-pass filter 49 2nd voltage controlled oscillator 50 5th multiplier

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (1)

(57) Claims: 1. A phase error detecting means for detecting a phase error between a modulated carrier included in quadrature detection output signals I and Q and a reference carrier for performing quadrature detection. A carrier recovery circuit comprising a voltage-controlled oscillator that generates a reference carrier whose frequency is controlled according to the phase error output from the phase error detection means, wherein the modulated carrier and the reference carrier are processed by processing the quadrature detection output signal. Frequency shift direction detecting means for detecting the direction of the frequency shift direction, control signal generating means for outputting a control signal based on an output signal of the frequency shift direction detecting means, and a frequency controlled in accordance with the control signal. A variable oscillating means for generating a correction signal, and a reference carrier corrected by multiplying the correction signal generated from the variable oscillating means by a carrier generated from the voltage controlled oscillator. Multiplying means for outputting a wave, wherein the frequency shift direction detecting means multiplies the sum and difference of the first and second quadrature detection output signals I and Q by the first multiplying means for multiplying the quadrature detection output signals I and Q. A second multiplying means, a third multiplying means for multiplying output signals of the first and second multiplying means, and a second multiplying means for multiplying a sum and a difference between output signals of the first and second multiplying means. 4, a first low-pass filter for extracting a low-frequency component of the output signal of the third multiplying means, and a second low-frequency filter for extracting a low-frequency component of the output signal of the fourth multiplying means. A low-pass filter;
A first phase difference detecting means for detecting a phase difference between the output signal of the low-pass filter and the output signal of the second low-pass filter; A third low-pass filter for extracting a band component;
A first comparator for comparing the output signal of the low-pass filter with a first reference value, and a second comparator for comparing the output signal of the third low-pass filter with a second reference value. With
The control signal generation means counts a clock signal of a predetermined frequency using the output signal of the first comparator as a count start / stop command and the output signal of the second comparator as a count up / down command. Counter, variable frequency divider whose frequency division ratio is controlled according to the count value of the counter, fixed oscillator, fixed frequency divider for dividing the output signal of the fixed oscillator, and variable frequency divider A second phase difference detecting means for detecting a phase difference between the output signal of the fixed frequency divider and an output signal of the fixed frequency divider, and a fourth means for extracting a low-frequency component of the output signal of the second phase difference detecting means. With a low-pass filter,
The carrier recovery circuit according to claim 1, wherein said variable oscillation means includes a second voltage-controlled oscillator that receives an output signal of said fourth low-pass filter as a control signal and generates said correction signal.