JP3029394B2 - FSK demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an FSK (Frequency
The present invention relates to an FSK demodulation device that demodulates modulated data by an orthogonal demodulation method from an FSK modulated wave signal modulated by a -Shift keying (frequency shift keying) method.

[0002]

2. Description of the Related Art As an FSK demodulator of this type, an FSK demodulator is known.
A modulated wave signal and two orthogonal to each other at the same frequency
The two local oscillation signals are mixed to generate an in-phase component signal and a quadrature component signal, which are baseband signals, and both component signals are input to a D-type flip-flop, so that the modulation data is either binary data. There is known a device for determining whether or not the above is true. In this conventional FSK demodulator, the generated quadrature component signal is waveform-shaped and input to the data input terminal of the D-type flip-flop, and the in-phase component signal is waveform-shaped and input to the clock input terminal of the D-type flip-flop. Has been entered. In this case, since the phase of the in-phase component signal is shifted by 周期 cycle with respect to the phase of the quadrature component signal, if the quadrature component signal is sampled in synchronization with the rise of the in-phase component signal, the sampled voltage level becomes , FSK-modulated wave signal is at a low level when the frequency shift is + Δf, and is high when the FSK-modulated wave signal is -Δf frequency shifted. As a result, it is possible to determine whether the modulation data is binary data.

[0003]

However, this conventional FSK demodulator has the following problems. That is,
When the transmission rate of the modulated data is high, the pulse width of the waveform-shaped quadrature component signal is inevitably narrow. However, the conventional FSK demodulator samples the quadrature component signal in synchronization with the rise of the in-phase component signal. Therefore, when noise is superimposed on one or both of the two component signals, there is a problem that the in-phase component signal cannot be reliably sampled. Further, when the frequency of the carrier in the FSK modulated wave signal is shifted, the pulse width of the in-phase component signal may be extremely short, or the in-phase component signal may become a DC component signal.
In such a case, since the in-phase component signal does not function as a clock signal, there is a problem that the sampling itself cannot be performed. Furthermore, when the frequency shift of the carrier wave is large, the phases of both component signals may be reversed, and in such a case, there is a problem that erroneous determination of data occurs.

[0004] The present invention has been made in view of such a problem, and even when FSK modulation is performed at a high transmission rate, it is possible to reliably determine modulation data.
It is a main object to provide an SK demodulator. Also, F
It is an object of the present invention to provide an FSK demodulator capable of reliably determining modulated data even when the carrier frequency of an SK modulated wave signal fluctuates.

[0005]

According to a first aspect of the present invention, there is provided an FSK demodulator for mixing an in-phase component signal and a quadrature component signal by mixing two local oscillation signals and an FSK modulated wave signal which are orthogonal to each other. Respectively, and a FSK demodulator for demodulating modulated data from an FSK modulated wave signal based on both component signals. Means for multiplying the value of the sampled in-phase signal by the value of the sampled quadrature component signal and the value of the quadrature component signal sampled immediately before the first multiplier; A second multiplier for multiplying each other by the value of the in-phase component signal sampled immediately before A subtractor for subtracting the multiplied value of the first multiplier from the multiplied value of, a reference value generating means for generating a reference value for determining the modulation data based on the subtracted value of the subtractor, Reference value storage means for storing a value,
Determining means for determining the modulation data by comparing the reference value and the subtraction value.

In this FSK demodulator, the first multiplier multiplies the value of the sampled in-phase component signal by the value of the quadrature component signal sampled immediately before this, and the second multiplier generates The value of the sampled quadrature component signal is multiplied by the value of the in-phase component signal sampled immediately before this. Then, the subtractor subtracts the multiplied value of the first multiplier from the multiplied value of the second multiplier. This subtraction value means the cross product of the vector synthesized from the latest sampled in-phase component signal and quadrature component signal, respectively, and the vector synthesized from the in-phase component signal and quadrature component signal sampled immediately before this. .
In this case, if both vectors are positioned on polar coordinates, for example, if the modulation data is binary data and the cross product value is positive, the vector corresponding to the latest sampled both component signals is sampled immediately before Means that it is rotating counterclockwise with respect to the vector corresponding to both component signals, and in such a case, the FSK modulated wave signal is + Δf
Has been shifted. On the other hand, if the outer product value is negative, it means that it is rotating clockwise, and in such a case, FS
The K modulated wave signal is shifted by -Δf.

The reference value generating means generates a reference value for judging modulation data by averaging, for example, the subtraction value output from the subtractor, and the reference value storing means generates the reference value. The obtained reference value is stored. On the other hand, the determination means
By comparing the reference value stored by the reference value storage means with the subtraction value, it is determined whether the modulation data is binary data. As a result, even when the transmission rate of the modulated data is high, the outer product value can be always obtained, so that the determining unit can reliably determine the modulated data. In this case, when the modulation data is multi-valued, a plurality of reference values are provided, and by comparing with each reference value, it is possible to reliably and easily determine which of the multi-valued data is the modulation data.

According to a second aspect of the present invention, there is provided an FSK demodulator according to the first aspect, further comprising a local oscillation signal generating means for generating a local oscillation signal, and a local oscillation signal generating means for setting a reference value within a predetermined allowable range. Local oscillation frequency control means for controlling the oscillation frequency of the signal generation means.

For example, when the frequency of the carrier of the FSK modulated wave signal changes, the value of the subtraction value changes accordingly, and the reference value generated by the reference value generating means also changes accordingly. In this case, in this FSK demodulation device, the local oscillation frequency control means controls the oscillation frequency of the local oscillation signal generation means so that the reference value falls within a predetermined allowable range.
Therefore, the value of the changed subtraction value returns to the original value, and the reference value also returns to the predetermined value accordingly. Accordingly, the value of the subtraction value does not reverse the sign due to the frequency fluctuation of the carrier, and the determination unit can reliably determine the modulation data.

According to a third aspect of the present invention, there is provided the FSK demodulator according to the second aspect, wherein the sampling signal frequency is set such that the subtraction value falls within a predetermined setting range with respect to the reference value. It is characterized by comprising setting means.

In this FSK demodulator, even if the transmission rates are different, it is possible to determine whether the modulated data is binary data by the same configuration. That is, for example, when the transmission rate of the modulated data is increased while the sampling frequency is kept constant, the value of θ in the calculation of the cross product value decreases, and the subtraction value decreases. Therefore, if the frequency of the sampling signal is set so that the subtraction value falls within a predetermined setting range with respect to the reference value, the sampling frequency automatically follows the transmission rate of the modulated data, and as a result, θ Increases, the value of the subtraction value also increases. As a result, the judgment by the judging means becomes possible and the judgment becomes easy, so that the error rate in the judgment of the modulation data can be reduced.

According to a fourth aspect of the present invention, in the FSK demodulation apparatus according to the third aspect, the sampling signal frequency setting means changes the sampling signal frequency of the sampling signal generation means from a preset frequency to a sequentially lower frequency. It is characterized by making it.

In this FSK demodulator, for example, FSK
When the modulation degree of the modulated wave signal is constant and the transmission rate of the modulated data is unknown, the sampling signal frequency setting means sets the sampling signal frequency of the sampling signal generation means to a frequency that is sequentially lower from a preset frequency. To change. In this case, if the sampling signal frequency setting means sets the frequency of the sampling signal such that the subtraction value falls within a predetermined setting range with respect to the reference value, a sampling signal having a frequency suitable for the transmission rate is generated. Thus, the determination unit can reliably determine the modulation data. In this case, by adding the subtraction values within one modulation section, the difference between the sum of the subtraction values and the reference value becomes larger, so that the modulation data can be determined more reliably. At the same time, if the reference value updating means updates the reference value based on the added subtraction value, the reference value is updated earlier.

According to a fifth aspect of the present invention, in the FSK demodulator according to the third or fourth aspect, the local oscillation frequency control means sets the sampling signal frequency when the reference value is out of a predetermined allowable range. Prior to the setting of the frequency of the sampling signal by the means, the oscillation frequency of the local oscillation signal generating means is controlled.

In this FSK demodulator, when the reference value is out of a predetermined allowable range, the local oscillation frequency setting means sets
To set the oscillation frequency of the local oscillation signal generation means,
The carrier frequency of the SK modulated wave signal matches the frequency of the local oscillation signal. Next, the sampling signal frequency setting means sets the frequency of the sampling signal. As a result, the reference value also falls within the predetermined allowable range, and the determination of the modulation data is reliably performed by the determination unit.

According to a sixth aspect of the present invention, there is provided an FSK demodulation apparatus according to any one of the first to fifth aspects,
A reference value updating unit that updates the reference value of the reference value storage unit based on the latest subtraction value output from the subtractor and the reference value stored in the reference value storage unit. .

In this FSK demodulator, the reference value updating means integrates the latest output subtraction value into the subtraction value stored in the reference value storage means and averages the reference value. Update. As described above, the determination unit updates the reference value for determination based on the newly output subtraction value one after another, so that the determination unit can accurately determine the modulation data.

According to a seventh aspect of the present invention, in the FSK demodulator according to any one of the first to sixth aspects,
Modulation section detection means for detecting one modulation section of the modulation data, wherein the determination means determines the modulation data based on an added value obtained by adding the subtracted values within the detected one modulation section to each other. .

In this FSK demodulator, the judging means judges the modulation data based on a value obtained by adding a subtraction value in one modulation interval of the modulation data detected by the modulation interval detecting means. In this case, since all of the added subtraction values are either positive or negative, the absolute value of the added value is larger than each individual subtracted value. Therefore, for example, when comparing with a reference value or the like, the determination means has a larger margin, so that it is possible to make an accurate determination. Further, the noise superimposed on the subtraction value is canceled by each other, so that the C / N ratio of the subtraction value is improved.

An FSK demodulator according to claim 8 is the FSK demodulator according to any one of claims 1 to 7,
While passing the in-phase component signal and the quadrature component signal,
A low-pass filter configured to be able to set a cutoff frequency based on the sampling frequency.

In this FSK demodulator, the cutoff frequency of the low-pass filter is set based on the sampling frequency. This means that the band of the low-pass filter is limited in accordance with the transmission rate of the modulated data, thereby removing unnecessary noise and improving the C / N ratio of the in-phase component signal and the quadrature component signal. As a result, the error rate of the determination means decreases.

According to a ninth aspect of the present invention, in the FSK demodulating apparatus according to the eighth aspect, the cutoff frequency of the low-pass filter is set to be equal to or less than 1/2 of the sampling frequency.

In this FSK demodulator, since the band of the low-pass filter is the so-called Nyquist band, the error rate of the judgment means can be further reduced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the FSK demodulator according to the present invention will be described below with reference to the accompanying drawings.

The FSK demodulator 1 shown in FIG.
One configuration for demodulating the original binary data from a high-frequency signal (FSK modulated wave signal) fR obtained by FSK-modulating a carrier wave in the Hz band based on binary modulation data of "1" and "0" with a frequency shift Δf. It is. Hereinafter, in the present embodiment, the high-frequency signal fR is represented as Cos (ωc + Δωi) t, and when the modulation data has the value “1”, fR = (ωc−Δω) t
When the modulation data is a value “0”, fR = (ωc +
Δω) t. In this case, the amplitude value of the FSK wave is set to the value “1”.

Next, a specific configuration will be described with reference to FIGS.

As shown in FIG. 1, the FSK demodulator 1
Receiver 2, two LPFs (low-pass filters) 3, 4, 2
S / H parts (sampling means) 5, 6, two A / H
D conversion units 7 and 8, PLL unit (Pase-Locked Loop, local oscillation signal generation means) 9, AFC processing unit 10, cross product operation unit 1
1, a determination control unit (determination unit) 12 and a setting control unit (sampling signal generation unit) 13. Hereinafter, each component will be specifically described.

The receiving unit 2 generates an in-phase component signal Si and a quadrature component signal Sq from the FSK-modulated high-frequency signal f R having the shift frequency Δf by quadrature demodulation by synchronous detection.
Explaining a specific operation, the amplifier 21 shown in FIG.
The input high-frequency signal fR in the 900 MHz band is amplified and output to the first and second mixers 23 and 24. Next, the first mixer 23 generates the in-phase component signal Si by mixing the local oscillation signal fL output from the PLL unit 9 with the high-frequency signal fR. On the other hand, the local oscillation signal fL is output to the second mixer 24 after the phase is shifted by π / 2 by the π / 2 phase shifter 22. The second mixer 24 mixes the local oscillation signal fL1 and the high-frequency signal fR to generate a quadrature component signal Sq. here,
The outline of the quadrature demodulation will be described below. In this case, fR = Cos (ωc + Δω) t, where, when the high-frequency signal fR is shifted by + Δω frequency, fL = 2Cosωct and fL1 = 2Sinωct, the in-phase component demodulated by the first mixer 23 Signal Si
Is: Si = fL × fR = (Cos (2ωc + Δω) t + CosΔ
ωt), and the quadrature component signal Sq demodulated by the second mixer is: Sq = fL1 × fR = (Sin (2ωc + Δω) t + SinΔ
ωt).

Similarly, the high-frequency signal fR becomes -Δ
When the ω frequency is shifted, Si = fL × fR = (Cos (2ωc + Δω) t + CosΔ
ωt), Sq = fL1 × fR = (Sin (2ωc + Δω) t−SinΔ
ωt). Thus, the receiving unit 2 generates the in-phase component signal Si and the quadrature component signal Sq by quadrature demodulation, and outputs these to the LPF units 3 and 4, respectively.

The LPF units 3 and 4 use cut-off frequencies that are equal to or less than 1/2 the sampling frequency and higher than the modulation frequency (Δω / 2π), and pass in-phase and anti-phase component signals Si and Sq, respectively. With both component signals S
local oscillation frequencies fL and fL1 included in i and Sq, respectively.
Cos (2ωc + Δω) t and Sin (2ωc + Δω) t, which are twice the frequency components of the above, are removed. Thereby, both signals Si and Sq output from LPF sections 3 and 4 are output.
Are expressed as Si = Cos Δωt and Sq = Sin Δωt when the modulation data is “0”, and are expressed as Si = Cos Δωt and Sq = −Sin Δωt when the modulation data is “1”. . The LPF units 3 and 4 are configured such that their cutoff frequencies are varied based on the band control signal of the setting control unit 13.

The S / H (sample hold) units 5 and 6
The in-phase and quadrature component signals Si and Sq are sampled in synchronization with the sampling clock output from the setting control unit 13. In this case, in the present embodiment, although not particularly limited, the frequency of the sampling clock is normally set to about four times the transmission rate frequency of the modulated data. Specifically, the transmission rate is 48
At 00 bps, the sampling clock frequency is
It is set to 19200 Hz. On the other hand, when the transmission rate of the modulated data fluctuates, the setting control unit 13 appropriately changes the sampling clock frequency.

The A / D converters 7 and 8 are respectively S / H
The in-phase and quadrature-component signals Si and Sq sampled by the units 5 and 6 are converted into digital Si data and digital Sq data (hereinafter simply referred to as “Si data and Sq data”) by quantizing them. 11 is output.

The PLL section 9 has a configuration of a known technology.
A local oscillation signal fL is generated based on an oscillation control signal output from the AFC processing unit 10. The AFC processing unit 10
A decision control unit 1 including a D / A conversion unit and a low-pass filter;
2 converts the threshold data (which will be described later) into an analog signal by a D / A converter, removes a frequency component of a sampling clock included in the converted analog signal, and outputs the analog signal to a PLL unit 9. Output.

As shown in FIG. 4, the outer product calculation unit 11
Two multipliers 31 and 32 and two one-sample delay circuits 3
3 and 34 and a subtractor 35. Cross product operation unit 1
In step 1, an outer product operation is performed based on the Si and Sq data converted by the A / D converters 7 and 8, respectively. Specifically, the horizontal axis and the vertical axis represent the Cos component and Sin, respectively.
When Si data and Sq data are plotted on the polar coordinates corresponding to the components as Cos components and Sin components, respectively, and the plotted points are connected to the center of the polar coordinates, the sampled Si and Sq data can be displayed as a vector. it can. Specifically, the Si data sampled most recently and immediately before via the A / D conversion unit 7 are respectively designated as b1 and a1, and the A / D conversion unit 8
Sampled most recently through S
Assuming that the q data is b2 and a2, the components of the latest sampled b vector and the immediately preceding sampled a vector are (b1, b2) and (a1,
a2), and can be plotted on polar coordinates as shown in FIG. Then, the locus of both a and b vectors rotates on an arc having the same distance from the center of the polar coordinate on the polar coordinate. Therefore, by calculating the cross product of the a vector and the b vector, the rotation direction of the b vector with respect to the a vector can be known. Thus, the high-frequency signal fR is shifted by + Δf when the b vector is rotated counterclockwise with respect to the a vector (hereinafter, referred to as “CCW direction”), and is shifted clockwise (hereinafter, “CW direction”). ), It can be seen that it is shifted by -Δf. This means that when there is a shift of + Δf,
The in-phase component signal Si and the quadrature component signal Sq are Co
sΔωt and Sin Δωt, and when −Δf shifts, it can be understood from the fact that the in-phase component signal Si and the quadrature component signal Sq are Cos Δωt and −Sin Δωt, respectively.

More specifically, in the outer product calculation unit 11, 1
The sample delay circuit 34 outputs the Sq data input immediately before, so that the multiplier (first multiplier) 31
Multiplies the component a2 and the component b1 with each other to obtain data a
2 · b1 is generated. On the other hand, a multiplier (second multiplier) 3
2 indicates that the one-sample delay circuit 33 outputs the S
By outputting the i data, the component a1 and the component b2 are multiplied by each other to generate data a1 and b2. Next, the subtractor 35 subtracts the data output from the multiplier 31 from the data output from the multiplier 32. That is, in this case, the subtractor 35 outputs the cross product value data (a1
B2-a2b1) is generated. In this case, when the value of the outer product value data is positive, the b vector rotates in the CCW direction (see FIG. 7B), and the high-frequency signal fR becomes + Δf.
When the value of the cross product value data is negative, the b vector is rotating in the CW direction (see FIG. 3C), and the high-frequency signal fR is shifted by -Δf. Means that

The decision control unit 12 compares the value of the outer product value data with the threshold value to determine which of the binary data the high-frequency signal fR is shifted in frequency. As shown in FIG. 3, the determination control unit 12 includes a threshold value setting circuit (reference value generation means, reference value update means, local oscillation frequency control means) 41 for setting a threshold value, and modulation data from the cross product value data. A one-modulation section detection circuit (modulation section detection means) 42 for detecting one modulation section, and a data determination circuit 43 for determining whether the modulation data is binary data based on the outer product value data and the threshold value. And a comparison circuit 44 for comparing the threshold value with the value of the subtraction value data.

The threshold value setting circuit 41 includes two multipliers 51 and 52, an adder 53, a RAM (reference value storage means) 54, and a one-sample delay circuit 55, as shown in FIG. The threshold value setting circuit 41 updates the threshold value based on both the threshold value already stored in the RAM 54 and the value of the input cross product value data, and stores a new threshold value in the RAM 54. Let it. In particular,
When the cross product value data is input, the multiplier 51 multiplies the cross product value data by the value (1−α). In this case, the value α is a forgetting coefficient for determining how much the weight is applied to the threshold value already stored in the RAM 54 when setting the threshold value. Are not used for threshold setting, and when the value is 0, the threshold is set based only on the latest input cross product value data.

The threshold value stored in the RAM 54 is
The signal is output to the multiplier 52 by the one-sample delay circuit 55. Multiplier 52 multiplies the threshold value by forgetting coefficient α, and outputs the multiplied data to adder 53. Adder 5
3 adds the output data of the multiplier 51 and the output data of the multiplier 52 and stores the result in the RAM 54 as a new threshold value. As a result, when a large number of cross product value data is input, the forgetting coefficient α is made closer to the value 1 (for example, 0.
9) As a result, the threshold value approaches the value “0”, which is the average value of the cross product value data.
No. 3 can perform accurate determination of binary data. When the power is turned on, the RAM 54 stores a value “0” as an initial threshold value.

Next, the new threshold value stored in the RAM 54 is output as threshold value data to the one modulation section detection circuit 42, the comparison circuit 44, and the AFC processing unit 10, respectively. As a result, the threshold data is converted into an analog signal by the AFC processing unit 10 and then output to the PLL unit 9 so that the oscillation frequency of the PLL unit 9 is automatically controlled so as to be equal to the carrier frequency of the high frequency signal fR. Is done. As a result, the threshold value is updated based on the outer product value data that is input thereafter, and thus, the threshold value is almost 0V.
Transition to the vicinity. The present invention is not limited to this. For example, a configuration may be used in which a window comparator is used and the oscillation frequency of the PLL unit 9 is changed so that the threshold value falls within the window width of the window comparator. In this case, P
The oscillation frequency of the LL unit 9 is changed for the following reason. That is, for example, when the carrier frequency of the high-frequency signal fR shifts to the higher side, the vector has a larger rotation angle when + Δω frequency shifts than when −Δω frequency shift. Therefore, in such a case, the value of the cross product value data also tends to increase as a positive value and decrease as a negative value. As a result, the threshold gradually increases in the positive direction. Even in such a case, the data determination circuit 43 can determine whether the modulation data is binary data. However, if the value of the cross product value data is inverted in the positive or negative direction due to a large shift in the carrier frequency, the rotation direction of the vector may be erroneously determined (see FIG. 7D), and the data determination is performed. Circuit 4
No. 3 cannot make an accurate determination of binary data.
Therefore, in such a case, by making the oscillation frequency of the PLL unit 9 equal to the carrier frequency of the high-frequency signal fR, the vector rotation angle at the time of + Δω frequency shift and that at the time of −Δω frequency shift are the same. be able to. When the frequency of the high frequency signal fR shifts to the lower side, the vector becomes + Δ when the frequency shifts by −Δω.
Although the rotation angle becomes larger than when the ω frequency shifts, in such a case, the oscillation frequency of the PLL unit 9 is made equal to the carrier frequency of the high frequency signal fR in the same manner, thereby shifting the frequency by + Δω. The rotation angle at the time and at the time of -Δω frequency shift can be the same.

The one modulation section detection circuit 42 detects whether the value of the cross product value data has moved up or down with respect to the threshold value by comparing the threshold value with the value of the cross product value data. Thus, one modulation section of the input high-frequency signal fR, that is, the transmission rate of the modulated data is detected. By detecting one cycle of the transmission rate, for example, when a network is constructed by combining various devices, it is possible to synchronize with each device. Further, the one modulation period detection circuit 42 outputs a synchronization detection signal corresponding to the detected one modulation section to the comparison circuit 44.

The data determination circuit 43 determines that the binary data is "0" when the value of the cross product value data is larger than the threshold value, and determines that the binary data is "1" when the value of the cross product value data is smaller than the threshold value. The judgment data (0 or 1) is stored in an external device (not shown).
Is output.

The comparison circuit 44 has a window comparator for changing the sampling frequency of the setting control section 13. Although the window comparator is not particularly limited, a plurality of windows having a predetermined voltage width whose window width is symmetric with respect to a voltage value of 0 V are provided. The comparison circuit 44 outputs the rate signal to the setting control unit 13 so that the difference between the positive and negative values of the outer product value data and the threshold value falls within the window width where the difference is the maximum, and outputs the frequency signal of the sampling signal. To change. Controlling to increase the difference between the value of the outer product value data and the threshold value in this manner may cause the data determination circuit 43 to make an erroneous determination if the difference becomes extremely small. Because there is.

The comparison circuit 44 sets the synchronization detection signal output from the one modulation section detection circuit 42 within one pulse width of the synchronization detection signal.
A rate signal is output so that four consecutive cross product value data having a value larger than the threshold value are continuously output and four cross product value data having a value smaller than the threshold value are continuously output. To change the sampling frequency. this is,
For example, if the vector is rotated by 2π within one modulation section when the modulation rate is a constant value, this means that the rotation angle of the vector in one outer product operation is set to π / 2 or less. The reason for this is that if the vector is rotated by π or more in one cross product operation, the sign of the cross product value is reversed, and accurate determination cannot be performed. In order to maximize the value of the cross product, it is more preferable to make the rotation angle of the vector close to π / 2.

The setting control unit 13 has an oscillator for generating a sampling signal therein, and has an oscillation frequency of the oscillator according to the rate signal output from the determination control unit 12.
That is, the frequency of the sampling clock is changed. The setting control unit 13 outputs a band control signal to set and control the cutoff frequency of the LPF units 3 and 4 so as to be equal to or less than half the frequency of the sampling clock. This is based on the Nyquist band theory, whereby the C / N ratio of the in-phase and quadrature component signals Si and Sq can be improved.

Next, the overall operation of the FSK demodulator 1 will be described.

The input high-frequency signal fR is quadrature-demodulated by the receiver 2 into in-phase and quadrature component signals Si and Sq. The two component signals Si and Sq are respectively filtered by the LPF units 3 and 4 and then sampled by the S / H units 5 and 6 in synchronization with the sampling clock. Sampled both component signals Si, Sq
Are converted into Si data and Sq data by the A / D converters 7 and 8, respectively, and then output to the outer product calculation unit 11. Next, the cross product calculation unit 11 calculates the cross product of the vector based on the both Si and Sq data sampled immediately before and the vector sampled most recently, and outputs the cross product value data to the determination control unit 12 as cross product value data. Next, the determination control unit 12 determines the rotation direction of the vector by comparing the value of the cross product value data with the threshold value. If the outer product value data is larger, the determination control unit 12 determines that the vector is rotating in the CCW direction, and determines that the modulation data is a value “0”. On the other hand, when the outer product value data is smaller, the determination control unit 12 determines that the vector is CW
It is determined that the rotation is performed in the direction, and the modulation data is determined to be the value “1”.

In this case, when sampling the first two component signals Si and Sq, the setting control unit 13 sets the frequency of the sampling clock to the highest frequency, for example, 100
KHz, and the frequency of the sampling clock is gradually reduced so that the values of both Si and Sq data fall within the maximum window width of the window comparator in the threshold value setting circuit 41. Thus, even if the transmission rate of the modulated data is unknown, it is possible to reliably determine whether the modulated data is binary data. As described later, Si, S sampled in one modulation section of the modulation data detected by one modulation section detection circuit 42.
The q data may be added, and the frequency of the sampling clock may be gradually reduced so that the added values of both the Si and Sq data fall within the maximum window width of the window comparator in the threshold value setting circuit 41. .

When the frequency of the high-frequency signal fR is shifted to a higher frequency, the rotation angle of the vector becomes larger in the CCW direction and smaller in the CW direction, and becomes smaller in the direction of the lower frequency of the high-frequency signal fR. If it does, the reverse is true. Therefore, when the frequency of the high-frequency signal fR is shifted to the higher side, the value of the cross product value data is shifted to the positive side as a whole, so that the threshold value is also a high voltage. In such a case, the threshold data is stored in the AFC processor 10 before the frequency control of the sampling signal by the comparison circuit 44.
And the threshold voltage of the analog signal is input to the PLL unit 9. As a result, the PLL unit 9 sets the local oscillation signal fL to the same frequency as the carrier frequency of the high frequency signal fR. Conversely, when the high frequency signal fR shifts to the lower side,
In the same manner, the PLL unit 9 sets the local oscillation signal fL to the same frequency as the carrier frequency of the high frequency signal fR. Thus, the FSK demodulation device 1 can reliably detect the rotation direction of the vector even if the carrier frequency of the high-frequency signal fR is shifted, so that it is possible to reliably determine which of the binary data the modulation data is. can do.

On the other hand, when the threshold value fluctuates similarly, the comparison circuit 44 changes the oscillation frequency of the sampling clock in the setting control unit 13 by the rate signal so that the threshold value falls within the predetermined window width. Let it. Thus, with the same configuration, high-frequency signals fR from devices having different transmission rates can be reliably received, and binary data can be reliably determined.
Note that the threshold value fluctuates in both cases where the frequency of the high-frequency signal fR shifts and the transmission rate changes, but depending on the value of the outer product value data that moves up and down around the threshold value, Can be determined. That is, in the former case, for example, when the carrier frequency of the high-frequency signal fR is shifted to a higher one,
Since the difference voltage between the threshold value and the value of the cross product value data is larger when the modulation data is “0” than when the modulation data is “1”, it can be easily determined. By the way, in the latter case, even if the modulation data is either “0” or “1”, the difference voltage is equal, and both the threshold value and the value of the cross product value data are totally positive or negative. Shift.

As described above, according to the FSK demodulator 1 of the present embodiment, the carrier frequency of the high frequency signal fR or the carrier frequency
When either or both of the frequencies of the local oscillation signal fL of the LL unit 9 are shifted or when the transmission rate of the modulation data changes, the local oscillation frequency of the PLL unit 9 is changed. By making the sampling frequency of the setting control unit 13 variable,
2 can easily and reliably determine whether the modulation data is binary data.

In this embodiment, the value of the outer product value data is compared with the threshold value one by one, but the present invention is not limited to this. For example, as shown in FIG. 6, an adder 61, a one-sample delay circuit 62, a two-sample delay circuit 63, and a three-sample delay circuit 64 constitute a cross product value addition circuit 60 that adds values of four cross product value data to each other. By arranging this immediately before the data determination circuit 43, the addition output of the adder 61 may be compared with a threshold value. This figure shows a circuit for explaining the invention according to claim 7. In this cross product value adding circuit 60, an adder 61
Four cross product value data sampled within one modulation section detected by one modulation section detection circuit 42, that is, the cross product value data input most recently and the cross product input immediately before and delayed by one sample delay circuit 62 The value data, the cross product value data input before and delayed by the two-sample delay circuit 63 and the cross product value data input three times before and delayed by the three-sample delay circuit 64 are added to each other and output. . As a result, the data determination circuit 43 compares the added value with the threshold to determine that the modulation data is 2
The value can be more reliably determined. That is, in such a case, the margin of the added value with respect to the threshold value increases, so that the determination error rate can be significantly reduced. Further, by adding the outer product value data, noise included in the in-phase and quadrature component signals Si and Sq can be canceled, so that the C / N ratio of both component signals Si and Sq can be further improved. As a result, the determination error rate can be reduced.

In this embodiment, the high-frequency signal f
Although the case where R is in the 900 MHz band has been described, it is needless to say that the present invention is not particularly limited and can be applied to higher frequency signals and lower frequency signals. Also, an example has been described in which a binary FSK modulated wave signal is demodulated. However, the present invention is not limited to this.
The present invention is also applicable to the case where the high frequency signal fR which has been K-demodulated is demodulated. In such a case, by providing a plurality of threshold values and comparing the magnitude of each of the threshold values with the cross product value data, it is possible to easily and reliably determine which of the multi-value data is. The threshold value does not necessarily need to be updated. The modulation data is composed of binary data, the modulation rate of the modulation data is predetermined, and the carrier frequency of the high-frequency signal fR matches the local oscillation frequency. In such a case, it is determined whether the value of the cross product value data is positive or negative (this is equivalent to setting the threshold value to 0 V), so that the modulation data is 2
Which of the value data can be easily determined.

Further, in this embodiment, the hardware configuration has been described to facilitate the understanding.
DSP configuration for parts 3 and 4 or after
(Digital Signal Processor) and its functions can be executed by software. Further, in the present embodiment, the outer product value is obtained by digital calculation, but it is also possible to perform analog calculation without A / D conversion.

[0054]

As described above, according to the FSK demodulator according to the present invention, when making a decision on modulated data, the decision means compares the reference value stored by the reference value storage means with the subtracted value. By doing so, it is possible to determine whether the modulated data is binary data, and when the modulated data is transmitted at a high transmission rate or when the carrier frequency of the FSK modulated wave signal is shifted. However, it is possible to reliably determine the modulation data. Further, even when the carrier frequency of the FSK modulated wave signal is largely shifted, the local oscillation frequency control means controls the oscillation frequency of the local oscillation signal generation means so that the reference value falls within a predetermined allowable range. This makes it possible to reliably determine the modulation data.

[Brief description of the drawings]

FIG. 1 is a block diagram of an FSK demodulation device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a receiving unit according to the embodiment of the present invention.

FIG. 3 is a block diagram of a determination control unit according to the embodiment of the present invention.

FIG. 4 is a block diagram of an outer product calculation unit according to the embodiment of the present invention.

FIG. 5 is a block diagram of a threshold value setting circuit according to the embodiment of the present invention.

FIG. 6 is a block diagram of an outer product value adding circuit according to another embodiment of the present invention.

7A is a diagram for explaining the concept of vector display, FIG. 7B is a diagram illustrating a relationship between a cross product value and a rotation direction of the vector, and FIG. FIG. 7D is a diagram illustrating a relationship between the rotation direction of the high frequency signal and the vector direction when the carrier frequency of the high frequency signal is shifted.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 FSK demodulator 2 reception unit 3 LPF unit 4 LPF unit 5 S / H unit 6 S / H unit 9 PLL unit 11 outer product calculation unit 12 decision control unit 13 setting control unit 31 multiplier 32 multiplier 35 subtractor 41 threshold Value setting circuit 42 1 modulation section detection circuit 54 RAM 60 Outer product value addition circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-122260 (JP, A) JP-A-6-244880 (JP, A) JP-A-3-101344 (JP, A) 38941 (JP, A) JP-A-3-157703 (JP, A) JP-A-5-48659 (JP, A) JP-A-7-107128 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H04L 27/00-27/38

Claims (9)

(57) [Claims] 1. Two local oscillation signals orthogonal to each other and F
An SK modulation wave signal is mixed to generate an in-phase component signal and a quadrature component signal, respectively, and F based on the two component signals demodulates modulation data from the FSK modulation wave signal.
In the SK demodulator, a sampling signal generating means for generating a sampling signal, a sampling means for sampling the in-phase component signal and the quadrature component signal in synchronization with the sampling signal, a value of the sampled in-phase signal, A first multiplier for multiplying each other by the value of the quadrature component signal sampled immediately before, and the value of the sampled quadrature component signal and the value of the in-phase component signal sampled immediately before each other. A second multiplier for multiplying, a subtractor for subtracting a multiplied value of the first multiplier from a multiplied value of the second multiplier, and a subtractor for determining a reference value for determining the modulation data Reference value generating means for generating based on the subtracted value of the reference value, reference value storing means for storing the generated reference value, the reference value and the subtracted value And a determination unit for determining the modulation data by comparing the FSK demodulation data. 2. A local oscillation signal generating means for generating the local oscillation signal; a local oscillation frequency control means for controlling an oscillation frequency of the local oscillation signal generating means so that the reference value falls within a predetermined allowable range; The FSK demodulator according to claim 1, further comprising: 3. A sampling signal frequency setting means for setting a frequency of the sampling signal so that the subtraction value falls within a predetermined setting range with respect to the reference value. FSK demodulator. 4. The FSK demodulator according to claim 3, wherein the sampling signal frequency setting means changes the sampling signal frequency of the sampling signal generation means from a preset frequency to a lower frequency. 5. The local oscillation frequency control means, when the reference value is out of the predetermined allowable range, prior to setting the frequency of the sampling signal by the sampling signal frequency setting means, 5. The FSK demodulator according to claim 3, wherein the oscillation frequency of the generating means is controlled. 6. A reference value update for updating a reference value of the reference value storage means based on the latest subtraction value output from the subtractor and the reference value stored in the reference value storage means. 2. The method according to claim 1, further comprising:
6. The FSK demodulator according to any one of claims 1 to 5. 7. A modulation section detecting section for detecting one modulation section of the modulation data, wherein the determination section performs the modulation based on an added value obtained by adding the subtracted values in the detected one modulation section to each other. 7. The FSK demodulator according to claim 1, wherein data is determined. 8. A low-pass filter configured to allow the in-phase component signal and the quadrature component signal to pass therethrough and to be able to set a cutoff frequency based on the sampling frequency. The FSK demodulator according to any one of the above. 9. The FSK demodulator according to claim 8, wherein a cut-off frequency of the low-pass filter is set to be equal to or less than 1/2 of the sampling frequency.