JP3413902B2 - Frequency shift keying data demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency shift keying data demodulator mainly applied to a direct conversion receiver for wireless communication.

[0002]

2. Description of the Related Art Recently, in wireless communication, frequency shift keying (FSK) is performed.
A direct conversion receiver using an ng (frequency shift keying) signal has been studied as a configuration suitable for integration into an integrated circuit.

For example, the configuration described in Japanese Patent Laid-Open No. 58-19038 is known. Hereinafter, a conventional FSK data demodulator will be briefly described with reference to FIG.

In FIG. 11, F applied to input 60
The SK reception signal is supplied to the mixer 61 and, at the same time, 9
The signals are supplied to the mixer 63 through the 0-degree phase shifter 62, down-converted by mixing with the signal of the local oscillator 64, respectively, and passed through low-pass filters 65 and 66 that pass only the baseband signal, and the I signal 67 and Q The signal 68 is obtained. The I signal 67 is converted into a digital signal 70 by the amplitude limiting amplifier 69, and the Q signal 68 is converted into a digital signal 73 by the amplitude limiting amplifier 72 after being phase-shifted by the 90-degree phase shifter 71. Then, the logical operation circuit 74, which receives the digital signals 70 and 73 as input, decodes the data.

[0005]

However, in the case of high-speed data communication in which the symbol rate of the transmission data becomes equal to or higher than the frequency deviation, the accurate demodulation of the receiver described in the section of the prior art. Requires a very wide band 90-degree phase shifter because it is necessary to shift the phase from a low frequency to a frequency on the order of the sum of the modulation frequency shift and the symbol rate. Generally, a 90-degree phase shifter capable of shifting a phase from a low frequency needs to use a large capacitor in a constituent circuit, and thus it is difficult to integrate it, which causes an obstacle to low power consumption and miniaturization. Become. The main reason for adopting the configuration of the direct conversion receiver is that the circuit configuration is simple and thus the circuit can be easily integrated. However, the above problem is contrary to the purpose.

Further, in an actual receiver having a conventional configuration, when receiving a high-speed modulated signal as described above, the signal to be phase-shifted contains many discontinuities, so that the 90-degree phase shifter causes a phase shift. However, there is a problem that the demodulation becomes difficult because it is not completely performed.

The present invention solves the above-mentioned problems, and is compatible with high-speed data communication in which the symbol rate of transmission data is higher than the frequency deviation, and has a simple circuit configuration suitable for integrated circuits. FSK for direct conversion receiver
The purpose is to realize a data demodulator.

[0008]

In order to achieve the above object, the present invention provides a first voltage and a second voltage for detecting whether the I and Q signals obtained by direct conversion of a modulation signal are respectively increased or decreased. Change detecting means and first and second multiplying each voltage change signal and I signal or Q signal
And a switching signal generating means for comparing the I signal and the Q signal and outputting a switching signal.
And a switching means for switching and outputting the output signal from the second multiplication means.

[0009]

The first multiplication means obtains the decoding result from the voltage change signal of the I signal and the Q signal. The second multiplication means obtains the decoding result of the voltage change signal of the Q signal and the I signal. The switching means switches these decoding results according to the magnitude of comparison between the I signal and the Q signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 is a main part of a receiver to which the data demodulator of the present invention is applied. In FIG. 1, 1a is an antenna, 1b is an amplifier, and 1 is a received FS.
K modulation signal, 2 is a local oscillator, 3 is a 90 degree phase shifter for shifting the signal of the local oscillator 2, 4 is a first mixer for mixing the modulation signal 1 with the signal of the local oscillator 2, and 5 is a modulation signal 1 to 9
A second mixer 6, which mixes with the output signal of the 0 degree phase shifter 3,
Reference numeral 7 denotes first and second low-pass filters for obtaining baseband I and Q signals from the output signals of the mixers 4 and 5.

In the first mixer 4, the modulated signal 1 and
The output signal of the local oscillator 2 is supplied, the output of the mixer 4 is passed through a first low pass filter, and an I signal 8 is obtained as a first baseband signal. The modulation signal 1 and a signal obtained by phase-shifting the output signal of the local oscillator 2 by the 90-degree phase shifter 3 are supplied to the second mixer 5, and the output of the mixer 5 is passed through a second reduction pass filter. As the second baseband signal, Q
Get signal 9. A first voltage change detection circuit 10 receives the I signal 8 as an input and outputs a voltage change signal 11 as a voltage change determination result. Reference numeral 12 is a first multiplication circuit, which inputs the voltage change signal 11 and the Q signal 9 and outputs the signal 1 as the multiplication result.
3 is output. A second voltage change detection circuit 14 receives the Q signal 9 as an input and outputs a voltage change signal 15 as a voltage determination result.
Is output. Reference numeral 16 is a second multiplication circuit, which is a voltage change signal 1
5 and the I signal 8 are input and a signal 17 is output as a multiplication result. Reference numeral 22 is a switching signal generating means for inputting the I signal 8 and the Q signal 9, comparing the amplitudes and outputting the switching signal 23. The switching circuit 18 outputs the output signal 1 according to the switching signal 23.
3 and the output signal 17 are switched to output the signal 19.
Reference numeral 20 is a demodulation means, which inputs the signal 19 and outputs a demodulated signal 21.

Details of signal processing by the above circuit configuration will be described. The received modulated signal 1 is defined as R (t) and is defined by the following (Equation 1).

[0013]

[Equation 1]

However, in (Equation 1), A is the amplitude of the received wave, ωc is the carrier frequency, ωd is the frequency shift, and D (t).
Is a function representing the transmission data at time t.

The output of the local oscillator 2 is L (t) and is defined by the following (Equation 2).

[0016]

[Equation 2]

However, in (Equation 2), Δω is a carrier wave,
The frequency difference between the local oscillators, φ is the phase difference between the received signal at t = 0 and the output of the local oscillator.

Then, I (t) and Q (t) shown in the following (Equation 3) are obtained as the I signal 8 and the Q signal 9.

[0019]

[Equation 3]

For simplification, it is assumed that the carrier wave, the frequency difference between the local oscillators, Δω = 0, and the phase difference between the received signal and the output of the local oscillator, φ = 0. This setting shows an ideal situation at the time of reception and has no influence on the description of the operation essence of the demodulator.

In the present embodiment, the phase quadrant of the I signal is determined by detecting the voltage change direction of the signal, and the mark or space of the transmission signal is determined based on the relationship between the determined phase quadrant and the voltage sign of the Q signal. Issue. Each quadrant of the I signal,
The voltage change of the signal in each quadrant and the voltage state of the signal whose phase is shifted by 90 degrees are shown in (Table 1).

[0022]

[Table 1]

Therefore, (1) the phase quadrant of the I signal is 0 to π.
In the case of, the direction of the voltage change of the I signal becomes negative. At this time, if the voltage of the Q signal is positive, it can be determined as a mark, and if it is negative, it can be determined as a space.

(2) When the phase quadrant of the I signal is π to 2π, the direction of the voltage change of the I signal is positive. At this time, Q
If the signal voltage is negative, it can be judged as a mark, and if it is positive, it can be judged as a space.

That is, the increase / decrease direction of the I signal 8 is detected by the voltage change detection circuit 10, and the voltage change signal 1 which is an output signal is detected.
1 is multiplied by the Q signal 9, and if the result is positive, it is determined to be a space, and if negative, it is determined to be a mark.

Further, the phase quadrant of the Q signal is determined by detecting the voltage change direction of the signal, and the mark and space of the transmission signal are determined and decoded based on the relationship between the determined phase quadrant and the voltage code of the I signal. Is also possible. The increase / decrease direction of the Q signal 9 is detected by the voltage change detection circuit 14, and the output voltage change signal 15 and the I signal 8 are multiplied. If the result is negative, it is determined to be a space, and if positive, it is determined to be a mark. .

Therefore, by effectively using the decoding result obtained from the phase quadrant of the I signal and the voltage of the Q signal, and the decoding result obtained from the phase quadrant of the Q signal and the voltage of the I signal, the respective results can be obtained. The effect of canceling in-phase noise generated in the process is obtained. Also, the reliability of the decoding result can be improved due to the redundancy of the signal processing.

The operating principle will be described. In FIG.
It is possible to perform digital processing by using an XOR circuit instead of the multiplication circuits 12 and 16. Although it is necessary to binarize the input of the XOR circuit, the XOR circuit can be easily integrated into an IC as compared with an analog multiplication circuit. As shown in FIG.
The switching signal 23 (c in the figure) is obtained by comparing the amplitudes of the signal 8 (a in the figure) and the Q signal 9 (b in the figure). When I signal 8> Q signal 9, the I signal 8 is easily affected by noise in the first voltage change detection circuit 10 at the inflection point (for example, t1 in the drawing). At the same time, the Q signal also becomes a zero-cross point, and is easily affected by noise at this time. Therefore, when I signal 8> Q signal 9 as described above, the output signal 13 of the first multiplication (XOR circuit) 12 is easily affected by noise (e in the figure), and the second multiplication circuit (XOR circuit) 16 is provided. The output signal 17 (d in the figure) is used for demodulation. When I signal 8> Q signal 9, the switching signal 23 becomes High and the switching circuit 18
Is an output signal 17 of the second multiplication circuit (XOR circuit) 16
(D in the figure) is output to the demodulation means 20 (f in the figure). When I signal 8 <Q signal 9, the switching signal 23 becomes Low, and the switching circuit 24 outputs the output signal 13 of the first multiplication circuit (XOR circuit) 12 to the demodulation means 20. As described above, the switching signal generating means 22 and the switching circuit 18 can select the one less susceptible to the influence of noise to improve the reliability of the demodulation result. If the carrier frequency of the modulated signal 1 and the frequency of the output signal of the local oscillator 2 deviate, the I signal 8,
The cycle of the Q signal 9 changes together. Even in this case,
Since the switching signal 23 is obtained by comparing the amplitudes of the I signal 8 and the Q signal 9, it is effective since it can cope with the change in the cycle.

Next, the switching signal generating means 22 will be described with reference to FIG.
The configuration of will be described. In FIG. 3, 41 is a signal inverter for inverting and outputting the Q signal 9, and 42 is the I signal 8 and Q.
A first comparison circuit for comparing the signal 9 with 43; a second comparison circuit 43 for comparing the I signal 8 with the output signal of the signal inverter 41;
Reference numeral 44 is composed of an XOR circuit that calculates the XOR of the output signal of the first comparison circuit 42 and the output signal of the second comparison circuit 43 and outputs the switching signal 23. I in the first comparison circuit
The result of comparing the magnitudes of the signal 8 and the Q signal 9 and the result of comparing the magnitudes of the inverted signals of the I signal 8 and the Q signal 9 in the second comparing circuit are both larger in the I signal 8. When and when it is small, the switching signal 23 becomes High. This is I
This is when the amplitudes of the signal 8 and the Q signal 9 are compared, and the I signal 8 is larger. The signal inverter 41 can be easily realized by an arithmetic element, and the comparison circuits 42, 43 can be easily realized by comparators. Alternatively, the absolute value of the signal voltage of the I signal is compared with the absolute value of the signal voltage of the Q signal, or the square of the signal voltage of the I signal is calculated by the mixer 51a as shown in FIG. The squared power is calculated by the mixer 51b, and this is compared
The same effect can be obtained even if the configuration is compared and the switching signal is output.

Next, the configuration of the switching circuit 24 will be described with reference to FIG. In FIG. 5, reference numeral 45 is a NOT circuit that inverts and outputs the switching signal 23, 46 is a first NAND circuit that calculates the NAND of the multiplication signal 13 and the switching signal 23 and outputs a signal 49, and 47 is a multiplication signal 17 Is a third NAND circuit that calculates and outputs a NAND of the output signal from the NOT circuit 45. The switching circuit 24 switches the output signal according to the switching signal 23, and outputs the multiplication signal 13 when the switching signal 23 is High and outputs the multiplication signal 17 when the switching signal 23 is Low. It should be noted that the configuration does not have to be the same as this, as long as the same operation is performed.

Furthermore, in order to facilitate IC integration, a circuit configuration with one multiplication circuit is conceivable. A second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 6, two switching circuits are prepared and the first switching circuit 18 is provided.
a and the second switching circuit 18b. First switching circuit 18
A switches between the I signal 8 and its voltage change signal 11 in response to the switching signal 23. The second switching circuit 18b switches between the Q signal 9 and its voltage change signal 15 according to the switching signal 23. When the switching signal 23 is High, the first switching circuit 18a outputs the voltage change signal 11 of the I signal, and the second switching circuit 18b outputs the Q signal 9. The two signals are multiplied by the multiplication circuit 12, and the multiplication signal is output to the demodulation means 20. When the switching signal 23 is Low, the first switching circuit 18a outputs the I signal 8 and the second switching circuit 18b outputs the voltage change signal 15 of the Q signal. The two signals are multiplied by the multiplication circuit 12, and the multiplication signal is output to the demodulation means 20. Since the number of multiplication circuits is reduced by one, power consumption can be reduced.

Next, the configuration of the voltage change detection circuit will be described. In FIG. 7, 31 is a delay circuit and 32 is a subtraction circuit. The delay circuit 31 delays the input signal I signal 8 by a predetermined amount Δt. The subtraction circuit 32 uses the I signal 8 and the delay circuit 3
The output signal of 1 is compared to determine the sign of the signal difference ΔV, and the voltage change signal 11 is output.

Here, the voltage change signal 11 is delayed by (Δt / 2) time compared with the I signal 8, and a time shift occurs between the voltage change signal 11 and the Q signal 9 in the first multiplication circuit 12. Since this time lag causes a demodulation error, Δt has been conventionally set to a minute amount. Further, since Δt is minute, ΔV was easily affected by noise in the subtraction circuit 32 in the voltage change detection circuit 10. Therefore, in the present invention, the time lag between the voltage change signal 11 and the Q signal 9 does not matter even when Δt is large. As a result, noise resistance is improved by increasing Δt. By inserting a delay circuit 31 as shown in FIG. 8, the I signal 8 and the Q signal 9 are delayed by (Δt / 2). Further, if the configuration uses two decoding results as shown in FIG. 1, the configuration shown in FIG. 9 is more practical. First voltage change detection circuit 1
Within 0, the delay circuits 31a and 31b have a two-stage configuration (Δt
Signal 8 delayed by (/ 2) each and delayed by (Δt / 2) time 8
a is input to the NAND circuit 16. .DELTA.t has the same value for the second voltage detection circuit. By increasing Δt, ΔV becomes large, and the voltage change signal 11 can be obtained even when the I signal 8 contains a large noise component. When Δt is ½ cycle of the modulation frequency, ΔV becomes maximum and the S / N characteristic is the best. On the other hand, however, delaying Δt causes a demodulation error (maximum Δt), and it is not sufficient to simply increase Δt. Therefore, it is conceivable to provide a low-pass filter in the demodulation means 20 and set the maximum time length at which errors can be corrected by this filter to Δt. When a roll filter is used as the low pass filter, this maximum time length is 1
It is 1/2 of the bit length. However, in reality, a demodulation error also occurs due to noise, so Δt is 1 / bit length 1 /
Must be 2 or less. Considering these points, it is preferable that both the first voltage change detection circuit 10 and the second voltage change detection circuit 14 have Δt = 1/4 of one bit length.

Further, a configuration is conceivable in which Δt is changed according to a signal such as a noise level to adjust the balance between noise resistance and demodulation error. For example, the voltage change detection circuit is configured as shown in FIG. Delay circuit system 3 with different Δt
A plurality of 3 are prepared and Δt is selected by the selection circuit 34. A noise level is input to the selection circuit 34 to adjust Δt according to the magnitude of noise, or when the transmission rate changes, Δt is changed according to the transmission rate. Further, in the delay circuit, Δt may be changed by using a variable resistance or a variable capacitance.

The voltage change detection circuit may output a voltage change signal by numerical comparison with a microcomputer using analog / digital conversion means. The noise removal process can be performed by the calculation process in the microcomputer. For example, Δ that changes within the time of Δt
The maximum value of V can be estimated. When the numerically compared value exceeds this maximum value, the effect of noise is judged and removed. This makes it possible to perform accurate voltage change detection resistant to noise without increasing Δt. In addition, it is easy to adjust Δt according to the magnitude of noise at that time because it is a numerical comparison.

Finally, in order to improve the reliability of the decoding result even if the carrier frequency of the modulated signal 1 and the frequency of the output signal of the local oscillator 2 are different, the DC voltage of the output signal of the demodulation means 20 is frequency-corrected. It is effective if the frequency of the output signal of the local oscillator 2 is controlled so that this DC voltage becomes a certain reference value by the means. The reference value is the DC voltage of the output signal from the demodulation means 20 when there is no frequency shift. The frequency correction means uses a low-pass filter composed of a resistor and a capacitor, and the frequency of the output signal of the local oscillator 2 is controlled by the output of this low-pass filter. Alternatively, the DC voltage of the output signal of the demodulation means 20 can be converted to analog /
After the digital conversion, the microcomputer process controls the DC voltage that controls the frequency of the output signal of the local oscillator 2.

[0037]

As is apparent from the above description, the frequency shift keying data demodulator of the present invention has the following advantages.

(1) By effectively using the outputs from the two decoding paths,
The effect of canceling in-phase noise is obtained. Also, the reliability of the decoding result can be improved due to the redundancy of the signal processing. Further, the number of multiplication circuits can be one in order to facilitate integration into an IC.

(2) Delay amount Δ in the voltage change detection process
Regarding t, it is possible to take a value that is less susceptible to noise and has few demodulation errors. Further, it is possible to make Δt variable and adjust it according to the reception situation.

(3) When the carrier frequency of the modulated signal deviates from the frequency of the output signal of the local oscillator, this is detected to adjust the frequency of the output signal of the local oscillator to the carrier frequency to eliminate the influence of the frequency deviation. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a frequency shift keying data demodulator according to a first embodiment of the present invention.

FIG. 2 is an output diagram of each signal in FIG. 1 above.

FIG. 3 is a block diagram of a switching means generating circuit shown in FIG.

FIG. 4 is a block diagram of another switching means generating circuit shown in FIG.

5 is a block diagram of the switching circuit of FIG.

FIG. 6 is a block diagram of a frequency shift keying data demodulator according to a second embodiment of the present invention.

7 is a block diagram of the voltage detection circuit shown in FIG.

FIG. 8 is a block diagram of a frequency shift keying data demodulator according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a frequency shift keying data demodulator according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram of another voltage change detection circuit of the present invention.

FIG. 11 is a block diagram of a conventional frequency shift keying data demodulator.

[Explanation of symbols]

1a receiving antenna 1b amplifier 2 local oscillator 3 90 degree phase shifter 4 First mixer 5 Second mixer 6 First low pass filter 7 Second low pass filter 10 First voltage change detection circuit 12 First multiplication circuit 14 Second voltage change detection circuit 16 Second multiplication circuit 18 Switching circuit 20 Demodulation means 22 Switching signal generating means 31 Delay circuit 32 subtraction circuit 33 Delay circuit system 34 Selection circuit 41 Signal Inverter 42 First Comparison Circuit 43 Second Comparison Circuit 44 XOR circuit 45 NOT circuit 46 First NAND Circuit 47 Second NAND circuit 48 Third NAND Circuit 51 mixer 52 Comparison circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Mimura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-191463 (JP, A) JP-A-1- 162402 (JP, A) JP 4-364525 (JP, A) JP 64-74850 (JP, A) JP 5-205409 (JP, A) JP 3-76382 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27/14

Claims (10)

(57) [Claims] 1. A first baseband signal and a second baseband signal whose phases are orthogonal to each other and whose phase relationship is relatively inverted due to up and down of frequency deviation from a carrier frequency of a signal which is frequency shift keying. On the other hand, first voltage change detection means for inputting the first baseband signal, detecting increase / decrease of the signal voltage, and outputting a first voltage change signal, the first voltage change signal and the second voltage change signal. First multiplication with the baseband signal of
Multiplying means, second voltage change detecting means for inputting the second baseband signal, detecting increase / decrease of a signal voltage, and outputting a second voltage change signal, the second voltage change signal and the second voltage change signal. A second base that inputs and multiplies the first baseband signal
Means for multiplying the first baseband signal and the second baseband signal
Switching signal generating means for inputting the baseband signal of the above and comparing amplitudes and outputting a switching signal, and an output signal of the first multiplying means and an output signal of the second multiplying means according to the switching signal. A frequency shift keying data demodulator comprising switching means for switching and outputting and a demodulation means for demodulating data using the output signal of the switching means. 2. A first baseband signal and a second baseband signal whose phases are orthogonal to each other and whose phase relationship is relatively inverted due to up and down frequency deviation from a carrier frequency of a signal which is frequency shift keying. On the other hand, switching signal generating means for inputting the first baseband signal and the second baseband signal, comparing amplitudes and outputting a switching signal, and a signal for inputting the first baseband signal First to detect the increase and decrease of voltage
First voltage change detection means for outputting the voltage change signal of
First switching means for switching and outputting the first baseband signal and the first voltage change signal according to the switching signal, and inputting the second baseband signal to increase or decrease the signal voltage. Second detecting and outputting a second voltage change signal
Of the voltage change detection means, the second switching means for switching and outputting the second baseband signal and the second voltage change signal in response to the switching signal, and the first switching means. A frequency shift keying data demodulator including a multiplication means for inputting and multiplying an output signal and an output signal from the second switching means, and a demodulation means for demodulating data using the output signal of the multiplication means. . 3. The switching signal generating means compares the square of the signal voltage of the first baseband signal with the square of the signal voltage of the second baseband signal, and outputs the switching signal. The described frequency shift keying data demodulator. 4. A first baseband signal and a second baseband signal whose phases are orthogonal to each other and whose phase relationship is relatively inverted due to up and down frequency deviation from a carrier frequency of a signal that is frequency shift keying. On the other hand, by inputting the first baseband signal and inputting the second baseband signal by inputting the second baseband signal and the voltage change detecting means for detecting an increase or decrease in the signal voltage from the voltage change amount when delayed by Δt. / 2) delaying means for delaying, multiplying means for multiplying the output signal of the voltage change detecting means and the output signal of the delaying means, and demodulating means for demodulating data using the output signal of the multiplying means Frequency shift keying data demodulator. 5. A first baseband signal and a second baseband signal whose phases are orthogonal to each other and whose phase relationship is relatively inverted by the frequency shift from a carrier frequency of a signal which is frequency shift keying. On the other hand, first delay means for inputting the first baseband signal to delay it by (Δt / 2) and second delay means for inputting the output signal of the first delay means to delay it by (Δt / 2) Delay means, first subtraction means for detecting an increase or decrease in the signal voltage from the voltage change amount of the output signal of the first baseband signal and the second delay means, and the second baseband signal as input. (Δt / 2) The third delay means for delaying and the output signal of the third delay means are input, and (Δt / 2)
t / 2) fourth delay means for delaying, second subtraction means for detecting an increase or decrease in signal voltage from the voltage change amount of the second baseband signal and the output signal of the fourth delay means, and the second delay means. Multiplying means for multiplying the output signal of the first or second voltage change detecting means by the output signal of the third or first delay means, and demodulating means for performing data demodulation using the output signal of the multiplying means. , Equipped with frequency shift keying
Data demodulator. 6. The frequency shift keying data demodulator according to claim 4, wherein Δt is 1/2 or less of one bit length. 7. The frequency shift keying data demodulator according to claim 4, 5 or 6, wherein .DELTA.t is variable by an external signal. 8. A frequency shift keying data demodulator according to claim 7, wherein a plurality of delay means having different Δt are provided, and Δt is made variable by selecting an output signal from said delay means. 9. The frequency shift keying data demodulator according to claim 7, wherein the voltage change detecting means is an analog / digital converting means, and Δt is variable by digital arithmetic processing. 10. The first and second baseband signals are signals of the frequency difference between the received signal and the output signal from the local oscillator, and the output signal from the demodulating means is the output signal from the local oscillator means. Frequency shift keying data demodulation according to any one of claims 1, 2, 3, 4, 5, 6, 7, 8 or 9, further comprising: frequency correction means for controlling the frequency of 1 to be equal to the carrier frequency of the received signal. vessel.